Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008100
M. Sunohara, Tomonori Fujii, M. Hoshino, H. Yonemura, M. Tomisaka, Kenji Takahashi
The three-dimensional (3D) chip stacking technology has been developed extensively recently for the next generation packaging technology. The technology includes thorough electrode fabrication, wafer thinning, wafer backside processing, testing, and chip stacking. Wafer thinning and wafer backside processing are important technologies among them, because these technologies accommodate small and thin form factor, enable thin chip stacking, and enhances electrical and mechanical reliability of the stacked module. In this paper, novel technologies of wafer thinning and wafer backside processes that include insulation film formation and bumping on the backside of the thinned wafer are described.
{"title":"Development of wafer thinning and double-sided bumping technologies for the three-dimensional stacked LSI","authors":"M. Sunohara, Tomonori Fujii, M. Hoshino, H. Yonemura, M. Tomisaka, Kenji Takahashi","doi":"10.1109/ECTC.2002.1008100","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008100","url":null,"abstract":"The three-dimensional (3D) chip stacking technology has been developed extensively recently for the next generation packaging technology. The technology includes thorough electrode fabrication, wafer thinning, wafer backside processing, testing, and chip stacking. Wafer thinning and wafer backside processing are important technologies among them, because these technologies accommodate small and thin form factor, enable thin chip stacking, and enhances electrical and mechanical reliability of the stacked module. In this paper, novel technologies of wafer thinning and wafer backside processes that include insulation film formation and bumping on the backside of the thinned wafer are described.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125542065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008110
M. Iwase, T. Shirai, Y. Ishikawa, T. Nomura, A. Izawa, H. Mori, N. Shimoji, M. Shiino, R. Yuguchi
An eight channel optical parallel transmitter/receiver module, for the optical parallel interconnection over VSR (Very Short Reach), which consists of an optical sub assembly (OSA), lead frame package with an IC on the heat spreader and newly designed low height receptacle was demonstrated. Using single mode fiber provided low skew and low height dimension of the receptacle system which is suitable for application to the small pitch between the printed circuit boards in a system rack of the equipment. To reduce the distortion of the signal and crosstalk between the channels, the microstrip line structure consisted of polyimide material and thin metal layers applied in the optical subassembly. Transmission bit rate as high as 3.125 Gbps/ch are achieved.
介绍了一种用于VSR (Very Short Reach)光并行互连的八通道光并行发送/接收模块，该模块由光学子组件(OSA)、带散热片IC的引线框架封装和新设计的低高度插座组成。采用单模光纤提供了低斜度和低高度尺寸的插座系统，适合应用于设备系统机架中印刷电路板之间的小间距。为了减少信号失真和通道间的串扰，将聚酰亚胺材料和薄金属层组成的微带线结构应用于光学组件中。传输比特率高达3.125 Gbps/ch。
{"title":"3.125 Gbps /spl times/ 8 channels parallel interconnection module with low height MT receptacle connector for single mode fibers","authors":"M. Iwase, T. Shirai, Y. Ishikawa, T. Nomura, A. Izawa, H. Mori, N. Shimoji, M. Shiino, R. Yuguchi","doi":"10.1109/ECTC.2002.1008110","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008110","url":null,"abstract":"An eight channel optical parallel transmitter/receiver module, for the optical parallel interconnection over VSR (Very Short Reach), which consists of an optical sub assembly (OSA), lead frame package with an IC on the heat spreader and newly designed low height receptacle was demonstrated. Using single mode fiber provided low skew and low height dimension of the receptacle system which is suitable for application to the small pitch between the printed circuit boards in a system rack of the equipment. To reduce the distortion of the signal and crosstalk between the channels, the microstrip line structure consisted of polyimide material and thin metal layers applied in the optical subassembly. Transmission bit rate as high as 3.125 Gbps/ch are achieved.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131780107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008224
I. Jeong, Choong-Mo Nam, Chang Yup Lee, Jung-Hoon Moon, Jongsoo Lee, Dong-Wook Kim, Y. Kwon
The strong pressure of cost and size reduction in wireless industry makes the phone makers find new and revolutionary solutions for their products. Among the various approaches, the passive integration is the most attractive way. To achieve both goals of dramatic size reduction and additional cost reduction, we developed low cost manufacturing technology for RF substrate and high performance process technology for RF integrated passive devices by electrochemically forming thick oxide on Si wafer and using Cu metal and BCB material for metal interconnection and interlayer. The fabricated substrate is conventional 6" Si wafer with SiO/sub 2/ thickness of 25 /spl mu/m on the surface. This substrate showed the very good insertion loss of 0.03 dB/mm at 4 GHz, including conductive metal loss, in case of 50 /spl Omega/ coplanar transmission line (W=50 /spl mu/m, G=20 /spl mu/m), and provided cost-effective solution in RF passive integration. Based on these process technologies, we fabricated ultra high Q inductor on Si, which showed the maximum quality factor of 120. Several RFIPD (Integrated Passive Device) were also fabricated on thick oxide silicon and they showed good RF performances in spite of small chip size. In case of power divider, the insertion loss is below 0.5 dB and isolation is more than 25 dB. The 900 MHz low pass filter has 0.5 dB insertion loss and more than 25 dB attenuation at second and third harmonics. These will be widely utilized in hand-held module and system where the size or volumetric efficiency is a critical buying criterion.
{"title":"High quality RF passive integration using 35 /spl mu/m thick oxide manufacturing technology","authors":"I. Jeong, Choong-Mo Nam, Chang Yup Lee, Jung-Hoon Moon, Jongsoo Lee, Dong-Wook Kim, Y. Kwon","doi":"10.1109/ECTC.2002.1008224","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008224","url":null,"abstract":"The strong pressure of cost and size reduction in wireless industry makes the phone makers find new and revolutionary solutions for their products. Among the various approaches, the passive integration is the most attractive way. To achieve both goals of dramatic size reduction and additional cost reduction, we developed low cost manufacturing technology for RF substrate and high performance process technology for RF integrated passive devices by electrochemically forming thick oxide on Si wafer and using Cu metal and BCB material for metal interconnection and interlayer. The fabricated substrate is conventional 6\" Si wafer with SiO/sub 2/ thickness of 25 /spl mu/m on the surface. This substrate showed the very good insertion loss of 0.03 dB/mm at 4 GHz, including conductive metal loss, in case of 50 /spl Omega/ coplanar transmission line (W=50 /spl mu/m, G=20 /spl mu/m), and provided cost-effective solution in RF passive integration. Based on these process technologies, we fabricated ultra high Q inductor on Si, which showed the maximum quality factor of 120. Several RFIPD (Integrated Passive Device) were also fabricated on thick oxide silicon and they showed good RF performances in spite of small chip size. In case of power divider, the insertion loss is below 0.5 dB and isolation is more than 25 dB. The 900 MHz low pass filter has 0.5 dB insertion loss and more than 25 dB attenuation at second and third harmonics. These will be widely utilized in hand-held module and system where the size or volumetric efficiency is a critical buying criterion.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130413624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008222
J. Lau, S. Erasmus, S. Pan
In this study, the effects of voids on the solder joint reliability of bump chip carrier (BCC++) packages on a printed circuit board are investigated. Emphasis is placed on the void size, void location, and void percentage. The solder is assumed to obey the Garofalo-Arrhenius creep constitutive equation. A total of 12 different cases are studied. In addition, the effects of voids on the crack growth in the BCC++ solder joint are studied by the fracture mechanics method. Emphasis is placed on the demonstration that a crack in the solder joint may be stopped by a void in front of it.
{"title":"Effects of voids on bump chip carrier (BCC++) solder joint reliability","authors":"J. Lau, S. Erasmus, S. Pan","doi":"10.1109/ECTC.2002.1008222","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008222","url":null,"abstract":"In this study, the effects of voids on the solder joint reliability of bump chip carrier (BCC++) packages on a printed circuit board are investigated. Emphasis is placed on the void size, void location, and void percentage. The solder is assumed to obey the Garofalo-Arrhenius creep constitutive equation. A total of 12 different cases are studied. In addition, the effects of voids on the crack growth in the BCC++ solder joint are studied by the fracture mechanics method. Emphasis is placed on the demonstration that a crack in the solder joint may be stopped by a void in front of it.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115025141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008159
Jeong H. Park, Selah Choe Park, M. Shin, C.C. Lee
The most important aspects of GaN-based devices are high breakdown field and high operating temperature. One highspeed device structure is the HFET (heterojunction field effect transistor) where two-dimensional electron gas (2DEG) is formed on AlGaN/GaN heterointerface. The electrons in 2DEG have significantly higher mobility than that in the conduction channel of a conventional metal-semiconductor field effect transistor (MESFET). Traditionally, GaN-based devices are fabricated on sapphire substrates. Since the sapphire substrate has relatively low thermal conductivity (0.28 W/cmK), it is necessary to carry out thermal analysis to ensure that the peak operating temperature of the device is within the acceptable range. Much effort has been exerted to provide sufficient thermal analysis in the past. In this paper, we present our thermal simulation using codes previously developed based on analytical solutions in our laboratory and compare the result of thermal simulation to actual thermal measurement results using nematic liquid crystal. Thermal simulation results agree reasonably well with measurement profiles.
{"title":"Thermal study of GaN-based HFET devices","authors":"Jeong H. Park, Selah Choe Park, M. Shin, C.C. Lee","doi":"10.1109/ECTC.2002.1008159","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008159","url":null,"abstract":"The most important aspects of GaN-based devices are high breakdown field and high operating temperature. One highspeed device structure is the HFET (heterojunction field effect transistor) where two-dimensional electron gas (2DEG) is formed on AlGaN/GaN heterointerface. The electrons in 2DEG have significantly higher mobility than that in the conduction channel of a conventional metal-semiconductor field effect transistor (MESFET). Traditionally, GaN-based devices are fabricated on sapphire substrates. Since the sapphire substrate has relatively low thermal conductivity (0.28 W/cmK), it is necessary to carry out thermal analysis to ensure that the peak operating temperature of the device is within the acceptable range. Much effort has been exerted to provide sufficient thermal analysis in the past. In this paper, we present our thermal simulation using codes previously developed based on analytical solutions in our laboratory and compare the result of thermal simulation to actual thermal measurement results using nematic liquid crystal. Thermal simulation results agree reasonably well with measurement profiles.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114997783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008254
J. Weidler, R. Newman, C. Zhai
As die have increased in complexity and density, there has been an associated growth in the number of die layers. To maximize field reliability interlayer die stress over use conditions should be minimized, which will minimize the occurrence of die layer delamination and associated die cracking failures. Interlayer die stress is affected by various packaging and assembly parameters, such as die thickness, die attach epoxy fillet geometry, molding compound, and saw cut process. Twenty-four lots of plastic ball-grid array (PBGA) packages were assembled in a 35/spl times/35 mm PBGA-352, as separate legs of a design of experiments (DOE). The die thickness was varied between 6 and 14 mils, in increments of 2 mils. The die were attached with three different fillet height geometries; standard fillet height (50% all around with no mismatch), hi/low fillet height (90% on one side of the die and 25% fillet height on the side opposite), and hi/even fillet height (90% all around with no mismatch). Each lot was subjected to reliability testing to determine which combination of assembly parameters yielded the most robust PBGA package. A PBGA package assembled with a 12 mil thick die and standard fillet produced the most robust product. The data indicates that the molding compound type and saw cut process did not affect the robustness of the package over the range of molding compounds and saw cut processes studied. The data also indicates that the thickness of the die is the parameter that most directly affects die cracking. In addition, the geometry of the fillet height also contributes to mechanical stress on the die, though the magnitude of its contribution is not as great. Two-dimensional mechanical modeling supports the experimental results. Furthermore, mechanical modeling provides a qualitative analysis of the stress induced on the die from the fillet geometry as well as the relationship between die thickness and package induced die stress.
{"title":"Optimizing assembly factors to minimize interlayer die stress in a PBGA package","authors":"J. Weidler, R. Newman, C. Zhai","doi":"10.1109/ECTC.2002.1008254","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008254","url":null,"abstract":"As die have increased in complexity and density, there has been an associated growth in the number of die layers. To maximize field reliability interlayer die stress over use conditions should be minimized, which will minimize the occurrence of die layer delamination and associated die cracking failures. Interlayer die stress is affected by various packaging and assembly parameters, such as die thickness, die attach epoxy fillet geometry, molding compound, and saw cut process. Twenty-four lots of plastic ball-grid array (PBGA) packages were assembled in a 35/spl times/35 mm PBGA-352, as separate legs of a design of experiments (DOE). The die thickness was varied between 6 and 14 mils, in increments of 2 mils. The die were attached with three different fillet height geometries; standard fillet height (50% all around with no mismatch), hi/low fillet height (90% on one side of the die and 25% fillet height on the side opposite), and hi/even fillet height (90% all around with no mismatch). Each lot was subjected to reliability testing to determine which combination of assembly parameters yielded the most robust PBGA package. A PBGA package assembled with a 12 mil thick die and standard fillet produced the most robust product. The data indicates that the molding compound type and saw cut process did not affect the robustness of the package over the range of molding compounds and saw cut processes studied. The data also indicates that the thickness of the die is the parameter that most directly affects die cracking. In addition, the geometry of the fillet height also contributes to mechanical stress on the die, though the magnitude of its contribution is not as great. Two-dimensional mechanical modeling supports the experimental results. Furthermore, mechanical modeling provides a qualitative analysis of the stress induced on the die from the fillet geometry as well as the relationship between die thickness and package induced die stress.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125778799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Studies the strength distribution of semiconductor chips on a wafer, and the influence of the back-side grinding process on the chip strength.. The three-point bending test, complying with the ASTM standard E855, was adopted to measure the chip strength. The first set of test vehicles is from three 8-inch wafers. One is of 28 mils thick without backside grinding, and the other two are backside ground to 18 mils and 11 mils thick. Then, four 6-inch wafers were used as the second set of test vehicles. The first two were 22 mils thick which were backside ground and the other two wafers were 27 mils in thickness without grinding. The third set of test vehicles was formed by three 8-inch wafers of identical thickness (11-mil) and size, but they were backside ground by different factories. It is found that, whereas the chip strength distributed randomly on a wafer which did not experience any backside grinding, any wafers that were subjected to backside grinding always resulted in weak regions. The averaged strength for the chips in the weak region was approximately 30% lower than the averaged strength calculated from the whole wafer, regardless of the chip dimension.
{"title":"Influence of grinding process on semiconductor chip strength","authors":"Enboa Wu, I.G. Shih, Y.N. Chen, S.C. Chen, C.Z. Tsai, C. Shao","doi":"10.1109/ECTC.2002.1008323","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008323","url":null,"abstract":"Studies the strength distribution of semiconductor chips on a wafer, and the influence of the back-side grinding process on the chip strength.. The three-point bending test, complying with the ASTM standard E855, was adopted to measure the chip strength. The first set of test vehicles is from three 8-inch wafers. One is of 28 mils thick without backside grinding, and the other two are backside ground to 18 mils and 11 mils thick. Then, four 6-inch wafers were used as the second set of test vehicles. The first two were 22 mils thick which were backside ground and the other two wafers were 27 mils in thickness without grinding. The third set of test vehicles was formed by three 8-inch wafers of identical thickness (11-mil) and size, but they were backside ground by different factories. It is found that, whereas the chip strength distributed randomly on a wafer which did not experience any backside grinding, any wafers that were subjected to backside grinding always resulted in weak regions. The averaged strength for the chips in the weak region was approximately 30% lower than the averaged strength calculated from the whole wafer, regardless of the chip dimension.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129705339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008227
A. M. Lyons, A. Becker, Young-Min Lee, C. Metz, S.-E. Shih, P. Auernhammer, S. Weisser
The electrical performance of Sub-Miniature Coaxial Connector (SMCC) interconnections to transmission lines was investigated in a frequency range up to 50 GHz. A family of test coupons was built to evaluate the following design parameters of SMCC connector interfaces: transmission line structures, solder pad shapes and structures, SMCC connector structures and grounding of the SMCC housing. Electromagnetic 3D full-wave solver (HFSS) was used not only to elucidate the main design factors affecting the electrical performance of the interconnection but also to compare between model results and measured S-parameters. Low-loss SMCC interconnections to well designed Grounded Co-Planar Waveguide (GCPW) and microstrip transmission lines were achieved without significant resonances up to a frequency range of 50 GHz. Grounding between the SMCC connector housing and bottom ground plane of the transmission line was found to be the most critical factor for electrical loss. Transmission line design and connector structure details were also found to have a significant impact on performance.
{"title":"Connector interconnections to transmission lines for 40 Gb/s broadband applications","authors":"A. M. Lyons, A. Becker, Young-Min Lee, C. Metz, S.-E. Shih, P. Auernhammer, S. Weisser","doi":"10.1109/ECTC.2002.1008227","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008227","url":null,"abstract":"The electrical performance of Sub-Miniature Coaxial Connector (SMCC) interconnections to transmission lines was investigated in a frequency range up to 50 GHz. A family of test coupons was built to evaluate the following design parameters of SMCC connector interfaces: transmission line structures, solder pad shapes and structures, SMCC connector structures and grounding of the SMCC housing. Electromagnetic 3D full-wave solver (HFSS) was used not only to elucidate the main design factors affecting the electrical performance of the interconnection but also to compare between model results and measured S-parameters. Low-loss SMCC interconnections to well designed Grounded Co-Planar Waveguide (GCPW) and microstrip transmission lines were achieved without significant resonances up to a frequency range of 50 GHz. Grounding between the SMCC connector housing and bottom ground plane of the transmission line was found to be the most critical factor for electrical loss. Transmission line design and connector structure details were also found to have a significant impact on performance.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129948958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008138
N. Tanaka, T. Sato, Y. Yamaji, T. Morifuji, M. Umemoto, K. Takahashi
Mechanical effects of copper through-vias formed in silicon dies in a three dimensional module, in which four bare-dies with copper through-vias are vertically stacked and electrically connected through the copper-vias and metal bumps, were numerically and experimentally studied. To examine the mechanical effects caused by the existence of the copper through-vias in a rigid silicon-chip, a series of stress analyses, related simple mechanical tests, and reliability tests were carried out. All these results show that the copper through-via has unique effects on the stress distribution caused by thermal mismatch and on the interconnection reliability in the 3D die-stacked module. In particular, it was found that the developed micro copper through-via is reliable because the stress distribution due to thermal load is close to the hydrostatic pressure condition, and enhances chip-to-chip interconnection reliability because the copper-via restrains the plastic deformation of a gold bump during temperature cycling.
{"title":"Mechanical effects of copper through-vias in a 3D die-stacked module","authors":"N. Tanaka, T. Sato, Y. Yamaji, T. Morifuji, M. Umemoto, K. Takahashi","doi":"10.1109/ECTC.2002.1008138","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008138","url":null,"abstract":"Mechanical effects of copper through-vias formed in silicon dies in a three dimensional module, in which four bare-dies with copper through-vias are vertically stacked and electrically connected through the copper-vias and metal bumps, were numerically and experimentally studied. To examine the mechanical effects caused by the existence of the copper through-vias in a rigid silicon-chip, a series of stress analyses, related simple mechanical tests, and reliability tests were carried out. All these results show that the copper through-via has unique effects on the stress distribution caused by thermal mismatch and on the interconnection reliability in the 3D die-stacked module. In particular, it was found that the developed micro copper through-via is reliable because the stress distribution due to thermal load is close to the hydrostatic pressure condition, and enhances chip-to-chip interconnection reliability because the copper-via restrains the plastic deformation of a gold bump during temperature cycling.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133934628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008098
D. Erdahl, I. C. Ume
The advent of surface mounted devices has allowed continued size decreases in electronic packages. However, the decrease in device size has led to other manufacturing problems. Therefore, as devices decrease in size, inspection technology must be developed to maintain consistent levels of quality without increasing manufacturing process time. The focus of most inspection technology is on finding defects with solder joint interconnects, but some devices, such as multi- layer chip capacitors (MLCCs), have failures not relating to the solder connection. Defects in MLCCs, known as flex cracks, are commonly caused by manufacturing processes, and no current means of detection exists, unless the cracks cause a device to fail a functional test. A laser ultrasonic and interferometric system, providing a non-contact, nondestructive and online approach for microelectronic package quality inspection, is designed and presented. A pulsed infrared laser excites a specimen into vibration through laser-generated ultrasound, and the vibration displacement is measured using an interferometer. Differentiation between acceptable and unacceptable devices is achieved using signal-processing techniques that compare waveforms between two devices. Results are presented or a case study involving MLCCs that have intentionally induced flex cracks, causing the devices to fail. The system has the capability of detecting open connections and flex cracks in the MLCC packages.
{"title":"Online-offline laser ultrasonic quality inspection tool for multi-layer chip capacitors","authors":"D. Erdahl, I. C. Ume","doi":"10.1109/ECTC.2002.1008098","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008098","url":null,"abstract":"The advent of surface mounted devices has allowed continued size decreases in electronic packages. However, the decrease in device size has led to other manufacturing problems. Therefore, as devices decrease in size, inspection technology must be developed to maintain consistent levels of quality without increasing manufacturing process time. The focus of most inspection technology is on finding defects with solder joint interconnects, but some devices, such as multi- layer chip capacitors (MLCCs), have failures not relating to the solder connection. Defects in MLCCs, known as flex cracks, are commonly caused by manufacturing processes, and no current means of detection exists, unless the cracks cause a device to fail a functional test. A laser ultrasonic and interferometric system, providing a non-contact, nondestructive and online approach for microelectronic package quality inspection, is designed and presented. A pulsed infrared laser excites a specimen into vibration through laser-generated ultrasound, and the vibration displacement is measured using an interferometer. Differentiation between acceptable and unacceptable devices is achieved using signal-processing techniques that compare waveforms between two devices. Results are presented or a case study involving MLCCs that have intentionally induced flex cracks, causing the devices to fail. The system has the capability of detecting open connections and flex cracks in the MLCC packages.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130863019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：