Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785821
A. Yin, J. White, A. Karroy, Chun Hu
Polycide/metal capacitors with high unit area capacitance and high linearity are successfully integrated into submicron CMOS device fabrication. The capacitor implementation is modular and low cost: the capacitor dielectric is deposited at low temperature and only one additional mask is needed for patterning the capacitor top plate. High voltage-capacitance linearity is obtained for the TEOS oxide capacitors of the capacitance density at 1 fF/spl mu/m/sup 2/, with the linear voltage coefficient of capacitance LVCC <5 ppm/V and the quadratic voltage coefficient of capacitance QVCC<2 ppm/V/sup 2/. For the nitride capacitors, 1.5 fF//spl mu/m/sup 2/ unit area capacitance is obtained with the LVCC <70 ppm/V and the QVCC <20 ppm/V/sup 2/.
{"title":"Integration of polycide/metal capacitors in advanced device fabrication","authors":"A. Yin, J. White, A. Karroy, Chun Hu","doi":"10.1109/ICSICT.1998.785821","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785821","url":null,"abstract":"Polycide/metal capacitors with high unit area capacitance and high linearity are successfully integrated into submicron CMOS device fabrication. The capacitor implementation is modular and low cost: the capacitor dielectric is deposited at low temperature and only one additional mask is needed for patterning the capacitor top plate. High voltage-capacitance linearity is obtained for the TEOS oxide capacitors of the capacitance density at 1 fF/spl mu/m/sup 2/, with the linear voltage coefficient of capacitance LVCC <5 ppm/V and the quadratic voltage coefficient of capacitance QVCC<2 ppm/V/sup 2/. For the nitride capacitors, 1.5 fF//spl mu/m/sup 2/ unit area capacitance is obtained with the LVCC <70 ppm/V and the QVCC <20 ppm/V/sup 2/.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128366332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785902
Bingxin Li, Lihong Jia, H. Tenhunen
In this paper a comprehensive method of analog modeling and simulation is given, in which models at different hierarchy levels are used in an optimized combination. To meet the conflicting requirements of simulation efficiency and accuracy, analog HDL is used as the bridge between high level behavioral models and low level transistor models. In this way both requirements are satisfied. A 5th order oversampling sigma-delta modulator is employed to demonstrate the design and modeling practice.
{"title":"Optimization of analog modeling and simulation","authors":"Bingxin Li, Lihong Jia, H. Tenhunen","doi":"10.1109/ICSICT.1998.785902","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785902","url":null,"abstract":"In this paper a comprehensive method of analog modeling and simulation is given, in which models at different hierarchy levels are used in an optimized combination. To meet the conflicting requirements of simulation efficiency and accuracy, analog HDL is used as the bridge between high level behavioral models and low level transistor models. In this way both requirements are satisfied. A 5th order oversampling sigma-delta modulator is employed to demonstrate the design and modeling practice.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126462892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785793
Nie Jiping, Liu Zhongli, He Zhijing, Yu Fang, L. Guohua
A process for fabricating n-channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p/sup +/-n junction was obtained by diffusion, and the conductive channel formed by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co/sub 60/ /spl gamma/-ray irradiation experiments, we found that the devices had a good total dose radiation hardness. When the total dose was 5 Mrad(Si), their threshold voltages shift was less than 0.1 V. The variation of transconductance and the channel leakage current were also small.
{"title":"JFET/SOS devices: processing and gamma radiation effects","authors":"Nie Jiping, Liu Zhongli, He Zhijing, Yu Fang, L. Guohua","doi":"10.1109/ICSICT.1998.785793","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785793","url":null,"abstract":"A process for fabricating n-channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p/sup +/-n junction was obtained by diffusion, and the conductive channel formed by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co/sub 60/ /spl gamma/-ray irradiation experiments, we found that the devices had a good total dose radiation hardness. When the total dose was 5 Mrad(Si), their threshold voltages shift was less than 0.1 V. The variation of transconductance and the channel leakage current were also small.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126178888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786077
Wenhong Li, Jinsheng Luo
In this paper, a novel analytical physical model for a thin film SOI RESURF structure is developed, based on the 2D Poisson equation, and the influence of the field SiO/sub 2/ interface charge is considered. The thin film SOI RESURF structure is analyzed using this novel model. There are two electric field peak values at the interfaces of the p/sup +/n and n/sup +/n junctions. The potential distribution is similar to a step between the p/sup +/n and n/sup +/n junctions. The field SiO/sub 2/ interface charge makes the electric field increase at the interface of the p/sup +/n junction, and reduces the electric field at the interface of the n/sup +/n junction. The analytical results agree with the simulations of MEDICI.
{"title":"A novel analytical physical model for thin film SOI RESURF structure based on 2-D Poisson equation","authors":"Wenhong Li, Jinsheng Luo","doi":"10.1109/ICSICT.1998.786077","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786077","url":null,"abstract":"In this paper, a novel analytical physical model for a thin film SOI RESURF structure is developed, based on the 2D Poisson equation, and the influence of the field SiO/sub 2/ interface charge is considered. The thin film SOI RESURF structure is analyzed using this novel model. There are two electric field peak values at the interfaces of the p/sup +/n and n/sup +/n junctions. The potential distribution is similar to a step between the p/sup +/n and n/sup +/n junctions. The field SiO/sub 2/ interface charge makes the electric field increase at the interface of the p/sup +/n junction, and reduces the electric field at the interface of the n/sup +/n junction. The analytical results agree with the simulations of MEDICI.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125881534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785920
Zhiliang Hong
A new model is presented for an EEPROM cell using devices existing in most simulators. Transient simulation can be performed with this model when the EEPROM cells perform erase, write and read operations. The compatibility has been verified by the examples in this paper.
{"title":"A new model for EEPROM cell","authors":"Zhiliang Hong","doi":"10.1109/ICSICT.1998.785920","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785920","url":null,"abstract":"A new model is presented for an EEPROM cell using devices existing in most simulators. Transient simulation can be performed with this model when the EEPROM cells perform erase, write and read operations. The compatibility has been verified by the examples in this paper.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127399134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785852
C. Ting, D. Papapanayiotou, Mei Zhu
Copper is a promising candidate to replace aluminum for better conductivity, reliability as well as lower cost. A new electrochemical copper deposition (ECD) process has been developed for the manufacturing of ULSI damascened, or in-laid, Cu interconnects. The new Cu ECD process-is designed for filling trenches and vias with high aspect ratio (AR) conductor structures for 0.25 um device generation and beyond. The gap filling Cu deposition process is capable of high deposition rate and gives good material properties as well as good uniformity. The newly developed Cu ECD system has a standard cluster tool configuration. Its deposition modules have in-situ rinse/dry capability to achieve cassette to cassette dry wafer in and dry wafer out operations. Dual damascene structures with 0.4 um feature size and AR 5:1, which represents the most aggressive device structure being made today, have been completely filled without voids or seams. In addition, deep contact test structures with 0.25 um feature size and AR 8:1 have also been filled to demonstrate the capabilities of this new technology.
{"title":"Electro-chemical deposition technology for ULSI multilevel copper interconnects","authors":"C. Ting, D. Papapanayiotou, Mei Zhu","doi":"10.1109/ICSICT.1998.785852","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785852","url":null,"abstract":"Copper is a promising candidate to replace aluminum for better conductivity, reliability as well as lower cost. A new electrochemical copper deposition (ECD) process has been developed for the manufacturing of ULSI damascened, or in-laid, Cu interconnects. The new Cu ECD process-is designed for filling trenches and vias with high aspect ratio (AR) conductor structures for 0.25 um device generation and beyond. The gap filling Cu deposition process is capable of high deposition rate and gives good material properties as well as good uniformity. The newly developed Cu ECD system has a standard cluster tool configuration. Its deposition modules have in-situ rinse/dry capability to achieve cassette to cassette dry wafer in and dry wafer out operations. Dual damascene structures with 0.4 um feature size and AR 5:1, which represents the most aggressive device structure being made today, have been completely filled without voids or seams. In addition, deep contact test structures with 0.25 um feature size and AR 8:1 have also been filled to demonstrate the capabilities of this new technology.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127573759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785933
A. Wang, C. Tsay
A new design methodology was developed for IC on-chip ESD protection design using a full-scale, mixed-mode simulation approach. The complete design procedure and design examples are discussed and reasonably good design prediction was observed in using this novel design methodology.
{"title":"A new design methodology using simulation for on-chip ESD protection designs for integrated circuits","authors":"A. Wang, C. Tsay","doi":"10.1109/ICSICT.1998.785933","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785933","url":null,"abstract":"A new design methodology was developed for IC on-chip ESD protection design using a full-scale, mixed-mode simulation approach. The complete design procedure and design examples are discussed and reasonably good design prediction was observed in using this novel design methodology.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"229 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120881862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785914
Xiaoyan Liu, Jinfeng Kang, R. Han
Based on the studies of the two dimensional nature of electrons in inversion layer of the ultra thin gate oxide MOSFET model to describe tunneling effect and inversion layer quantization effect on deep submicron MOSFET's threshold voltage is developed. By using of this model the influence of tunneling effect and the inversion layer quantization effect on the MOSFET threshold voltage can be estimated.
{"title":"The influence of tunneling effect and inversion layer quantization effect on deep submicron MOSFET","authors":"Xiaoyan Liu, Jinfeng Kang, R. Han","doi":"10.1109/ICSICT.1998.785914","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785914","url":null,"abstract":"Based on the studies of the two dimensional nature of electrons in inversion layer of the ultra thin gate oxide MOSFET model to describe tunneling effect and inversion layer quantization effect on deep submicron MOSFET's threshold voltage is developed. By using of this model the influence of tunneling effect and the inversion layer quantization effect on the MOSFET threshold voltage can be estimated.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127602785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786540
Wang Yaqiang, Jin Zhonghe, Wang Yuelin, Ding Chun
A micromechanical resonator is proposed and realized. It consists of a single-crystal silicon beam and two P-type silicon resistors. One resistor is used to excite the vibrating beam and the other to sense vibration of the beam. The dimensions of the resonator are about 4/spl times/2.5 mm/sup 2/, the resonant frequency is about 7.8 KHz, Q factor about 190 in air and above 2500 in vacuum degree of 7.5/spl times/10/sup -4/ Pa. The theory of thermal excitation is analyzed and the characteristics of the resonator are tested. We conclude that the resonator can be applied to vacuum measurement by the means of closed-loop resonating circuit. The design and realization of the circuit are described.
{"title":"Thermally excited micromechanical vacuum resonator","authors":"Wang Yaqiang, Jin Zhonghe, Wang Yuelin, Ding Chun","doi":"10.1109/ICSICT.1998.786540","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786540","url":null,"abstract":"A micromechanical resonator is proposed and realized. It consists of a single-crystal silicon beam and two P-type silicon resistors. One resistor is used to excite the vibrating beam and the other to sense vibration of the beam. The dimensions of the resonator are about 4/spl times/2.5 mm/sup 2/, the resonant frequency is about 7.8 KHz, Q factor about 190 in air and above 2500 in vacuum degree of 7.5/spl times/10/sup -4/ Pa. The theory of thermal excitation is analyzed and the characteristics of the resonator are tested. We conclude that the resonator can be applied to vacuum measurement by the means of closed-loop resonating circuit. The design and realization of the circuit are described.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"57 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114033935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785873
Honghao Ji, Qiuxia Xu
In this paper, the Co-SALICIDE process has been investigated intensively for the application to deep sub-micron CMOS VLSI. Adopting a Co/Ti/Si structure, epitaxial growth of a single crystal CoSi/sub 2/ film on the [100] Si substrate through two-step RTA has been demonstrated in detail. The heat-reaction characteristics of the Co/Ti/Si structure for forming the single crystal CoSi/sub 2/ film have been studied. We have applied the single crystal CoSi/sub 2/ to SALICIDE process post junction fabrication to obtain a smoother interface. Focusing on the disadvantage of a large leakage current that Co-salicided diodes usually suffer, ultra-shallow junctions especially, we found the leakage current to be large and investigated several methods to reduce diode leakage. The experiments show that PAI can improve the inverse I-V characteristics remarkably. A leakage current density of a Co-salicided diode as low as 8/spl times/10/sup -8/ A/cm/sup 2/ (V=5 v) was obtained for a junction depth of 107 nm. The resistivity of the single crystal CoSi/sub 2/ film is 16.5 /spl mu//spl Omega//sub (BH)/cm.
{"title":"An investigation of single crystal Co-SALICIDE (self-aligned silicide) process for deep sub-micrometer CMOS devices","authors":"Honghao Ji, Qiuxia Xu","doi":"10.1109/ICSICT.1998.785873","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785873","url":null,"abstract":"In this paper, the Co-SALICIDE process has been investigated intensively for the application to deep sub-micron CMOS VLSI. Adopting a Co/Ti/Si structure, epitaxial growth of a single crystal CoSi/sub 2/ film on the [100] Si substrate through two-step RTA has been demonstrated in detail. The heat-reaction characteristics of the Co/Ti/Si structure for forming the single crystal CoSi/sub 2/ film have been studied. We have applied the single crystal CoSi/sub 2/ to SALICIDE process post junction fabrication to obtain a smoother interface. Focusing on the disadvantage of a large leakage current that Co-salicided diodes usually suffer, ultra-shallow junctions especially, we found the leakage current to be large and investigated several methods to reduce diode leakage. The experiments show that PAI can improve the inverse I-V characteristics remarkably. A leakage current density of a Co-salicided diode as low as 8/spl times/10/sup -8/ A/cm/sup 2/ (V=5 v) was obtained for a junction depth of 107 nm. The resistivity of the single crystal CoSi/sub 2/ film is 16.5 /spl mu//spl Omega//sub (BH)/cm.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127751268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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