Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364494
M. Riffiod, P. Caspi, C. Piala, J. Voirin
This second technical session illustrates the methodological dimensions of technology transfer. It elaborates on some methodologies deployed in critical steps of the whole embedded systems development process, particularly to specify safety critical embedded systems, to manage obsolescence of components and to certify the airworthiness of the final solutions
{"title":"Hot Topic 2: Development and Industrialisation","authors":"M. Riffiod, P. Caspi, C. Piala, J. Voirin","doi":"10.1109/DATE.2007.364494","DOIUrl":"https://doi.org/10.1109/DATE.2007.364494","url":null,"abstract":"This second technical session illustrates the methodological dimensions of technology transfer. It elaborates on some methodologies deployed in critical steps of the whole embedded systems development process, particularly to specify safety critical embedded systems, to manage obsolescence of components and to certify the airworthiness of the final solutions","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128848374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364638
Matthias Krause, O. Bringmann, A. Hergenhan, Gökhan Tabanoglu, W. Rosenstiel
AUTOSAR is a recent specification initiative which focuses on a model-driven architecture like methodology for automotive applications. However, needed engineering steps, or how-to-come from a logical to a technical architecture respectively implementation, are not well supported by tools, yet. In contrast, SystemC offers a comprehensive way to simulate, analyze, and verify software. Furthermore, it is even able to take the timing behavior of underlying hardware and communication paths into account. Already at a first glance, there are many similarities with respect to the modeling structure between the both concepts. Therefore, this paper discusses approaches on how to use SystemC during the design process of AUTOSAR-conform systems
{"title":"Timing Simulation of Interconnected AUTOSAR Software-Components","authors":"Matthias Krause, O. Bringmann, A. Hergenhan, Gökhan Tabanoglu, W. Rosenstiel","doi":"10.1109/DATE.2007.364638","DOIUrl":"https://doi.org/10.1109/DATE.2007.364638","url":null,"abstract":"AUTOSAR is a recent specification initiative which focuses on a model-driven architecture like methodology for automotive applications. However, needed engineering steps, or how-to-come from a logical to a technical architecture respectively implementation, are not well supported by tools, yet. In contrast, SystemC offers a comprehensive way to simulate, analyze, and verify software. Furthermore, it is even able to take the timing behavior of underlying hardware and communication paths into account. Already at a first glance, there are many similarities with respect to the modeling structure between the both concepts. Therefore, this paper discusses approaches on how to use SystemC during the design process of AUTOSAR-conform systems","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129130144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364428
E. Bondarev, M. Chaudron, P. D. With
Solid frameworks and toolkits for design and analysis of embedded systems are of high importance, since they enable early reasoning about critical properties of a system. This paper presents a software toolkit that supports the design and performance analysis of real-time component-based software architectures deployed on heterogeneous multiprocessor platforms. The tooling environment contains a set of integrated tools for (a) component storage and retrieval, (b) graphics-based design of software and hardware architectures, (c) performance analysis of the designed architectures and, (d) automated code generation. The cornerstone of the toolkit is a performance analysis framework that automates composition of the individual component models into a system executable model, allows simulation of the system model and gives design-time predictions of key performance properties like response time, data throughput, and usage of hardware resources. The efficiency of this toolkit was illustrated on a car radio navigation benchmark system
{"title":"CARAT: a Toolkit for Design and Performance Analysis of Component-Based Embedded Systems","authors":"E. Bondarev, M. Chaudron, P. D. With","doi":"10.1109/DATE.2007.364428","DOIUrl":"https://doi.org/10.1109/DATE.2007.364428","url":null,"abstract":"Solid frameworks and toolkits for design and analysis of embedded systems are of high importance, since they enable early reasoning about critical properties of a system. This paper presents a software toolkit that supports the design and performance analysis of real-time component-based software architectures deployed on heterogeneous multiprocessor platforms. The tooling environment contains a set of integrated tools for (a) component storage and retrieval, (b) graphics-based design of software and hardware architectures, (c) performance analysis of the designed architectures and, (d) automated code generation. The cornerstone of the toolkit is a performance analysis framework that automates composition of the individual component models into a system executable model, allows simulation of the system model and gives design-time predictions of key performance properties like response time, data throughput, and usage of hardware resources. The efficiency of this toolkit was illustrated on a car radio navigation benchmark system","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117034556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364574
Christopher Ostler, Karam S. Chatha
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to support the high performance requirements of networking applications. The paper presents an automated system-level design technique for application development on such architectures. The technique incorporates process transformations and block multi-threading aware data mapping to maximize the worst case throughput of the application. We propose integer linear programming formulations for process allocation and data mapping on SMP and block multi-threading based network processors. The paper presents experimental results that evaluate the technique by implementing representative network processing applications on the Intel IXP 2400 architecture. The results demonstrate that our technique is able to generate high-quality mappings of realistic applications on the target architecture within a short time
{"title":"An ILP Formulation for System-Level Application Mapping on Network Processor Architectures","authors":"Christopher Ostler, Karam S. Chatha","doi":"10.1109/DATE.2007.364574","DOIUrl":"https://doi.org/10.1109/DATE.2007.364574","url":null,"abstract":"Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to support the high performance requirements of networking applications. The paper presents an automated system-level design technique for application development on such architectures. The technique incorporates process transformations and block multi-threading aware data mapping to maximize the worst case throughput of the application. We propose integer linear programming formulations for process allocation and data mapping on SMP and block multi-threading based network processors. The paper presents experimental results that evaluate the technique by implementing representative network processing applications on the Intel IXP 2400 architecture. The results demonstrate that our technique is able to generate high-quality mappings of realistic applications on the target architecture within a short time","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116137877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364432
F. Fummi, G. Perbellini, R. Pietrangeli, D. Quaglia
The paper focuses on the design of networked embedded systems which cooperate to provide complex distributed applications. A milestone in the effort of simplifying the implementation of such applications has been the introduction of a service layer, named middleware, which abstracts from the peculiarities of the operating system and HW components. However, the presence of the middleware has not been yet introduced in the design flow as an explicit dimension. This work presents an abstract model of middleware supporting different programming paradigms; it can be used as component in the design flow and allows to simulate and develop the application without doing premature assumptions on the actual HW/SW platform. At the end of the design flow the abstract middleware can be mapped to an actual middleware. The methodology has been analyzed both theoretically and practically with the actual application on a wireless sensor network
{"title":"A Middleware-centric Design Flow for Networked Embedded Systems","authors":"F. Fummi, G. Perbellini, R. Pietrangeli, D. Quaglia","doi":"10.1109/DATE.2007.364432","DOIUrl":"https://doi.org/10.1109/DATE.2007.364432","url":null,"abstract":"The paper focuses on the design of networked embedded systems which cooperate to provide complex distributed applications. A milestone in the effort of simplifying the implementation of such applications has been the introduction of a service layer, named middleware, which abstracts from the peculiarities of the operating system and HW components. However, the presence of the middleware has not been yet introduced in the design flow as an explicit dimension. This work presents an abstract model of middleware supporting different programming paradigms; it can be used as component in the design flow and allows to simulate and develop the application without doing premature assumptions on the actual HW/SW platform. At the end of the design flow the abstract middleware can be mapped to an actual middleware. The methodology has been analyzed both theoretically and practically with the actual application on a wireless sensor network","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125262842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364564
Q. Zhou, K. J. Balakrishnan
A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed in this paper. A broadcast scan based test compression algorithm for parallel testing of cores with multiple scan chains is used to reduce the test data of the SoC. Unlike other test compression schemes, the proposed algorithm doesn't require specialized test generation or fault simulation and is applicable with intellectual property (IP) cores. The core testing schedule with compression enabled is decided using a generalized strip packing algorithm. The hardware architecture to implement the proposed scheme is very simple. By using the combined approach, the total test data volume and test application time of the SoC is reduced to a level comparable with the test data volume and test application time of the largest core in the SoC
{"title":"Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling","authors":"Q. Zhou, K. J. Balakrishnan","doi":"10.1109/DATE.2007.364564","DOIUrl":"https://doi.org/10.1109/DATE.2007.364564","url":null,"abstract":"A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed in this paper. A broadcast scan based test compression algorithm for parallel testing of cores with multiple scan chains is used to reduce the test data of the SoC. Unlike other test compression schemes, the proposed algorithm doesn't require specialized test generation or fault simulation and is applicable with intellectual property (IP) cores. The core testing schedule with compression enabled is decided using a generalized strip packing algorithm. The hardware architecture to implement the proposed scheme is very simple. By using the combined approach, the total test data volume and test application time of the SoC is reduced to a level comparable with the test data volume and test application time of the largest core in the SoC","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126999119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364531
A. Nardi, E. Tuncer, S. Naidu, A. Antonau, S. Gradinaru, Tao Lin, J. Song
A vast literature has been published on statistical static timing analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, very limited literature exists on the applicability and the usage models of this new technology on real designs. This work focuses on the use of SSTA in real designs and its practical benefits and limitations over the traditional design flow. The authors introduce two new metrics to drive the optimization: skew criticality and aggregate sensitivity. Practical benefits of SSTA are demonstrated for clock tree analysis, and correct modeling of on-chip-variations. The use of SSTA to cover the traditional corner analysis and to drive optimization is also discussed. Results are reported on three designs implemented on a 90nm technology
{"title":"Use of Statistical Timing Analysis on Real Designs","authors":"A. Nardi, E. Tuncer, S. Naidu, A. Antonau, S. Gradinaru, Tao Lin, J. Song","doi":"10.1109/DATE.2007.364531","DOIUrl":"https://doi.org/10.1109/DATE.2007.364531","url":null,"abstract":"A vast literature has been published on statistical static timing analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, very limited literature exists on the applicability and the usage models of this new technology on real designs. This work focuses on the use of SSTA in real designs and its practical benefits and limitations over the traditional design flow. The authors introduce two new metrics to drive the optimization: skew criticality and aggregate sensitivity. Practical benefits of SSTA are demonstrated for clock tree analysis, and correct modeling of on-chip-variations. The use of SSTA to cover the traditional corner analysis and to drive optimization is also discussed. Results are reported on three designs implemented on a 90nm technology","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126178529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364425
S. Srivastava, J. Roychowdhury
Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(tau) = 0 derived using state-transition functions, and then solving this equation by Newton-Raphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for accurate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C2MOS latch/register structures, obtaining speedups of 4-10times over the current standard of binary search
{"title":"Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times","authors":"S. Srivastava, J. Roychowdhury","doi":"10.1109/DATE.2007.364425","DOIUrl":"https://doi.org/10.1109/DATE.2007.364425","url":null,"abstract":"Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(tau) = 0 derived using state-transition functions, and then solving this equation by Newton-Raphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for accurate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C2MOS latch/register structures, obtaining speedups of 4-10times over the current standard of binary search","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126688183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364645
O. Sinanoglu, Philip Schremmer
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of manufactured chips. In this paper, we propose a set of techniques that enable the accurate pinpointing of hold time violating scan cells, their modeling and tolerance, paving the way for the generation of valid test data that can be used to test chips with such systematic failures. The process yield is thus restored, as chips that are functional in mission mode can still be identified and shipped out, despite the existence of scan chain hold time failures. The techniques that we propose are non-intrusive, as they utilize only basic scan capabilities, and thus impose no design changes. Scan cells with hold time violations can be identified with maximal possible resolution, enabling the incorporation of the associated impact during the ATPG process and thus the generation of valid test data for the chips with such systematic failures
{"title":"Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations","authors":"O. Sinanoglu, Philip Schremmer","doi":"10.1109/DATE.2007.364645","DOIUrl":"https://doi.org/10.1109/DATE.2007.364645","url":null,"abstract":"Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of manufactured chips. In this paper, we propose a set of techniques that enable the accurate pinpointing of hold time violating scan cells, their modeling and tolerance, paving the way for the generation of valid test data that can be used to test chips with such systematic failures. The process yield is thus restored, as chips that are functional in mission mode can still be identified and shipped out, despite the existence of scan chain hold time failures. The techniques that we propose are non-intrusive, as they utilize only basic scan capabilities, and thus impose no design changes. Scan cells with hold time violations can be identified with maximal possible resolution, enabling the incorporation of the associated impact during the ATPG process and thus the generation of valid test data for the chips with such systematic failures","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126711434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364604
Hiren D. Patel, S. Shukla
The growing SystemC community for system level design exploration is a result of SystemC's capability of modeling at RTL and above RTL abstraction levels. However, managing shared state concurrency using multi-threading in large SystemC models is error prone. A recent extension of SystemC called Bluespec-SystemC (BS-ESL) counters this difficulty with its model of computation employing atomic rule-based specifications. However, for simulating a model that is partly designed in SystemC and partly using BS-ESL, an interoperability semantics and implementation of such a semantic is required. This paper views the interoperability problem as an abstraction gap closure problem. To illustrate the problem, the simulation semantics of BS-ESL and discrete-event simulation of RTL SystemC were formalized and provide a solution based on this formalization
{"title":"Tackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESL","authors":"Hiren D. Patel, S. Shukla","doi":"10.1109/DATE.2007.364604","DOIUrl":"https://doi.org/10.1109/DATE.2007.364604","url":null,"abstract":"The growing SystemC community for system level design exploration is a result of SystemC's capability of modeling at RTL and above RTL abstraction levels. However, managing shared state concurrency using multi-threading in large SystemC models is error prone. A recent extension of SystemC called Bluespec-SystemC (BS-ESL) counters this difficulty with its model of computation employing atomic rule-based specifications. However, for simulating a model that is partly designed in SystemC and partly using BS-ESL, an interoperability semantics and implementation of such a semantic is required. This paper views the interoperability problem as an abstraction gap closure problem. To illustrate the problem, the simulation semantics of BS-ESL and discrete-event simulation of RTL SystemC were formalized and provide a solution based on this formalization","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121492537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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