Pub Date : 2021-12-22DOI: 10.1109/IICM55040.2021.9730293
A. Abootorabian, A. Y. Goharrizi
Germanene is a two-dimensional material similar to graphene with a honeycomb structure in which carbon atoms are replaced by germanium atoms, the difference is that the distances between the atoms (in a perpendicular direction to the plate) are larger and they have a buckled structure. In this paper, the band-gap engineering of armchair germanene nanoribbons is performed by changing the passivation of the edge atoms. By increasing the width of the ribbons, the band-gap size is decreased according to three different trends. Also, changing the edge passivating atoms at any given width causes various changes in the band-gap size.
{"title":"Bandgap Engineering of Armchair Germanene Nanoribbons by Edge Passivation: A First Principles Study","authors":"A. Abootorabian, A. Y. Goharrizi","doi":"10.1109/IICM55040.2021.9730293","DOIUrl":"https://doi.org/10.1109/IICM55040.2021.9730293","url":null,"abstract":"Germanene is a two-dimensional material similar to graphene with a honeycomb structure in which carbon atoms are replaced by germanium atoms, the difference is that the distances between the atoms (in a perpendicular direction to the plate) are larger and they have a buckled structure. In this paper, the band-gap engineering of armchair germanene nanoribbons is performed by changing the passivation of the edge atoms. By increasing the width of the ribbons, the band-gap size is decreased according to three different trends. Also, changing the edge passivating atoms at any given width causes various changes in the band-gap size.","PeriodicalId":299499,"journal":{"name":"2021 Iranian International Conference on Microelectronics (IICM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127445216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-22DOI: 10.1109/IICM55040.2021.9730149
Amirali Chalechale, M. Shalchian, F. Jazaeri
Gate-lag induced trapping effects due to donor-like surface traps located in the access regions between the electrodes of AIGaN/GaN HEMTs are investigated through TCAD transient simulations. The effects of variation in trap energy level and temperature on the current collapse transient characteristics have been studied. A simple physical model is proposed (based on the Arrhenius relation) to obtain the emission time constants versus trap energy level and temperature which is in a good agreement with TCAD simulations.
{"title":"Study of Donor-like Surface Trap Emission in GaNHEMTs","authors":"Amirali Chalechale, M. Shalchian, F. Jazaeri","doi":"10.1109/IICM55040.2021.9730149","DOIUrl":"https://doi.org/10.1109/IICM55040.2021.9730149","url":null,"abstract":"Gate-lag induced trapping effects due to donor-like surface traps located in the access regions between the electrodes of AIGaN/GaN HEMTs are investigated through TCAD transient simulations. The effects of variation in trap energy level and temperature on the current collapse transient characteristics have been studied. A simple physical model is proposed (based on the Arrhenius relation) to obtain the emission time constants versus trap energy level and temperature which is in a good agreement with TCAD simulations.","PeriodicalId":299499,"journal":{"name":"2021 Iranian International Conference on Microelectronics (IICM)","volume":"319 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127778694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-22DOI: 10.1109/IICM55040.2021.9730157
M. Mohammadi, M. Yargholi
In this article, we are going to design and propose a mixer for 5G applications. The proposed mixer has a noise figure (NF) between 10- 11dB and an achieved gain of 15–17 dB in the operating Frequency of 30 GHz. The proposed mixer is designed in TSMC 180nm which has a reversed isolation of -47 dB in this frequency, and it has an OP1dB of 30 dBm in the RF port of 20dBm. The IP3 of the proposed mixer is about 60dBm. The techniques used for designing the proposed mixer are the current mirror PMOS transistors to enhance the gain and the inductive degeneration in RF transistors to increase the linearity.
{"title":"Design of high linear CMOS Mixer for 5G Applications","authors":"M. Mohammadi, M. Yargholi","doi":"10.1109/IICM55040.2021.9730157","DOIUrl":"https://doi.org/10.1109/IICM55040.2021.9730157","url":null,"abstract":"In this article, we are going to design and propose a mixer for 5G applications. The proposed mixer has a noise figure (NF) between 10- 11dB and an achieved gain of 15–17 dB in the operating Frequency of 30 GHz. The proposed mixer is designed in TSMC 180nm which has a reversed isolation of -47 dB in this frequency, and it has an OP1dB of 30 dBm in the RF port of 20dBm. The IP3 of the proposed mixer is about 60dBm. The techniques used for designing the proposed mixer are the current mirror PMOS transistors to enhance the gain and the inductive degeneration in RF transistors to increase the linearity.","PeriodicalId":299499,"journal":{"name":"2021 Iranian International Conference on Microelectronics (IICM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116114768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-22DOI: 10.1109/IICM55040.2021.9730303
Negar Choupan, Armin Amirkhani, A. Nabavi
This paper presents a class AB power amplifier (PA) with a pre-distortion linearizer for 28GHz mobile communications in TSMC $0.18-mu mathrm{m}$ CMOS technology. To achieve high linear output, a parasitic diode at the common source (CS) input is employed to reduce the variation of the input capacitance and improve the Pout characteristic. The simulation results show that the proposed PA consumes 163.36 mW, and the power gain (S21) of 18 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 17.62 dBm and maximum PAE of about %21 with an output 1-dB compression point (OP1dB) of 16.21 dBm. By pre-distortion linearization, the output power at the 1dB compression point increases by 3.55dB, with an efficient gain compensation performance.
本文提出了一种采用TSMC 0.18- m / m / m CMOS技术的带预失真线性化器的AB类功率放大器，用于28GHz移动通信。为了实现高线性输出，在共源(CS)输入端采用了寄生二极管，以减小输入电容的变化，改善Pout特性。仿真结果表明，该放大器功耗为163.36 mW，在28 GHz时功率增益(S21)为18 dB。该放大器的饱和功率(Psat)为17.62 dBm，最大PAE约为%21，输出1 db压缩点(OP1dB)为16.21 dBm。通过预失真线性化，1dB压缩点的输出功率增加了3.55dB，并具有有效的增益补偿性能。
{"title":"Millimeter-wave Power Amplifier with Linearization Technique in $0.18-mu mathrm{m}$ CMOS Process","authors":"Negar Choupan, Armin Amirkhani, A. Nabavi","doi":"10.1109/IICM55040.2021.9730303","DOIUrl":"https://doi.org/10.1109/IICM55040.2021.9730303","url":null,"abstract":"This paper presents a class AB power amplifier (PA) with a pre-distortion linearizer for 28GHz mobile communications in TSMC $0.18-mu mathrm{m}$ CMOS technology. To achieve high linear output, a parasitic diode at the common source (CS) input is employed to reduce the variation of the input capacitance and improve the Pout characteristic. The simulation results show that the proposed PA consumes 163.36 mW, and the power gain (S21) of 18 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 17.62 dBm and maximum PAE of about %21 with an output 1-dB compression point (OP1dB) of 16.21 dBm. By pre-distortion linearization, the output power at the 1dB compression point increases by 3.55dB, with an efficient gain compensation performance.","PeriodicalId":299499,"journal":{"name":"2021 Iranian International Conference on Microelectronics (IICM)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130741586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-22DOI: 10.1109/IICM55040.2021.9730136
Mohamadreza Eslami, F. Marvi, Kian Jafari Dinani
Prototypes of computers, or processors, were based almost exclusively on mechanical devices. Although electronic processors have become increasingly dominant over the past few decades, Recent advances in the technology of manufacturing 3D electromechanical components in micro and nano sizes have created new techniques for building complex microstructures that are of interest to researchers in new research In the field of mechanical computing. In this paper, we present a new XNOR logic gate design approach that can be built based on micro-electro-mechanical logic gates. One of the main advantages of this method is the ability to combine multi-physical as well as compatibility with the CMOS manufacturing process, as well as lower power consumption compared to logic gates consisting of several CMOS transistors. In this design, we have designed and simulated an XNOR logic gate using the multi-physics capability of Comsol-software and as well as using optical, electronic, mechanical and electro-static physics, whose inputs will be both electrical and optical signals. In this paper, according to the above selected design, by modeling and simulating different input modes of this logic gate, we examine the effect of each mode on the output of the gate as well as other features such as structure life, power consumption and resonant frequency. The proposed gate structure has a resonant frequency of 46 kHz and is highly reliable because it can operate without mechanical connection of the MEMS operator to logic inputs.
{"title":"Design and Simulation of Optical XNOR Logic Gate Based on MEMS Technology","authors":"Mohamadreza Eslami, F. Marvi, Kian Jafari Dinani","doi":"10.1109/IICM55040.2021.9730136","DOIUrl":"https://doi.org/10.1109/IICM55040.2021.9730136","url":null,"abstract":"Prototypes of computers, or processors, were based almost exclusively on mechanical devices. Although electronic processors have become increasingly dominant over the past few decades, Recent advances in the technology of manufacturing 3D electromechanical components in micro and nano sizes have created new techniques for building complex microstructures that are of interest to researchers in new research In the field of mechanical computing. In this paper, we present a new XNOR logic gate design approach that can be built based on micro-electro-mechanical logic gates. One of the main advantages of this method is the ability to combine multi-physical as well as compatibility with the CMOS manufacturing process, as well as lower power consumption compared to logic gates consisting of several CMOS transistors. In this design, we have designed and simulated an XNOR logic gate using the multi-physics capability of Comsol-software and as well as using optical, electronic, mechanical and electro-static physics, whose inputs will be both electrical and optical signals. In this paper, according to the above selected design, by modeling and simulating different input modes of this logic gate, we examine the effect of each mode on the output of the gate as well as other features such as structure life, power consumption and resonant frequency. The proposed gate structure has a resonant frequency of 46 kHz and is highly reliable because it can operate without mechanical connection of the MEMS operator to logic inputs.","PeriodicalId":299499,"journal":{"name":"2021 Iranian International Conference on Microelectronics (IICM)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117340414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-22DOI: 10.1109/IICM55040.2021.9730413
A. Hodaei, S. P. Abbasi
The practical importance of 1064 nm single-mode beams in fiber lasers as a source has led to extensive research into increasing the power of these lasers. In this paper, by using an asymmetric structure in a 1064 nm laser, the internal loss of the laser is reduced. The increase in the number of quantum wells (QWs) in the active region was also investigated. The results show that in the case of high thickness waveguide, where the confinement factor is low, increasing the number of QWs will increase the power, but the power portion of the fundamental mode is decreased and higher order modes are excited. Therefore, using of the active region including single-quantum well (SQW) is the best case for circular single mode beam.
{"title":"Effect of the QW number to produce circular single-mode beam in 1060 nm laser diodes","authors":"A. Hodaei, S. P. Abbasi","doi":"10.1109/IICM55040.2021.9730413","DOIUrl":"https://doi.org/10.1109/IICM55040.2021.9730413","url":null,"abstract":"The practical importance of 1064 nm single-mode beams in fiber lasers as a source has led to extensive research into increasing the power of these lasers. In this paper, by using an asymmetric structure in a 1064 nm laser, the internal loss of the laser is reduced. The increase in the number of quantum wells (QWs) in the active region was also investigated. The results show that in the case of high thickness waveguide, where the confinement factor is low, increasing the number of QWs will increase the power, but the power portion of the fundamental mode is decreased and higher order modes are excited. Therefore, using of the active region including single-quantum well (SQW) is the best case for circular single mode beam.","PeriodicalId":299499,"journal":{"name":"2021 Iranian International Conference on Microelectronics (IICM)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133537741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-22DOI: 10.1109/IICM55040.2021.9730239
M. Rashtian, Ali Najd
A non-Miller high bandwidth (BW) two-stage class A-AB operational transconductance amplifier (OTA) is presented. A nulling resistor with a series compensating capacitor is applied at the output node, extending the gain-bandwidth product (GBW) by introducing a left-half-plane (LHP) zero. Also, simple circuitry included an analog inverter is applied to achieve class A-AB. The proposed circuit is simulated using a $boldsymbol{0.18mu} mathbf{m} boldsymbol{1.8}mathbf{V}$ CMOS process standard technology. Simulation results with a 10pF capacitance load show that DC gain, GBW, average SR, average 1% settling time, and phase margin (PM) are 56.0 dB, 145.2 MHz, 89.8 $mathbf{V}/mumathbf{s}, boldsymbol{25.0}$ ns, and 58.2°, respectively. The PM, GBW, and average SR change to 79.1°,26.7 MHz, and $boldsymbol{17.1}mathbf{V}/boldsymbol{mu}mathbf{S}$, respectively, when driving a 100 pF capacitance load. Small signal analysis and simulation results indicate that the proposed OTA has a good performance at a large capacitive load. The proposed amplifier consumes 0.54mW @ 1.8V, which makes it a high current efficiency two-stage amplifier.
{"title":"A New Configuration for Two-Stage OTA LHP Zeroes","authors":"M. Rashtian, Ali Najd","doi":"10.1109/IICM55040.2021.9730239","DOIUrl":"https://doi.org/10.1109/IICM55040.2021.9730239","url":null,"abstract":"A non-Miller high bandwidth (BW) two-stage class A-AB operational transconductance amplifier (OTA) is presented. A nulling resistor with a series compensating capacitor is applied at the output node, extending the gain-bandwidth product (GBW) by introducing a left-half-plane (LHP) zero. Also, simple circuitry included an analog inverter is applied to achieve class A-AB. The proposed circuit is simulated using a $boldsymbol{0.18mu} mathbf{m} boldsymbol{1.8}mathbf{V}$ CMOS process standard technology. Simulation results with a 10pF capacitance load show that DC gain, GBW, average SR, average 1% settling time, and phase margin (PM) are 56.0 dB, 145.2 MHz, 89.8 $mathbf{V}/mumathbf{s}, boldsymbol{25.0}$ ns, and 58.2°, respectively. The PM, GBW, and average SR change to 79.1°,26.7 MHz, and $boldsymbol{17.1}mathbf{V}/boldsymbol{mu}mathbf{S}$, respectively, when driving a 100 pF capacitance load. Small signal analysis and simulation results indicate that the proposed OTA has a good performance at a large capacitive load. The proposed amplifier consumes 0.54mW @ 1.8V, which makes it a high current efficiency two-stage amplifier.","PeriodicalId":299499,"journal":{"name":"2021 Iranian International Conference on Microelectronics (IICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131405212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-22DOI: 10.1109/IICM55040.2021.9730246
Armin Amirkhani, Negar Choupan, A. Nabavi
In this paper, a 28 GHz fully on-chip Doherty power amplifier with harmonic injection is presented in 65 nm CMOS technology. In order to improve the linearity, two injection amplifier stages biased in class C are used. In this method, injection of the second harmonic compensates the gain compression phenomena and improves the output $mathrm{P}_{-}1text{dB}$ and PAE at $mathrm{P}_{-}1text{dB}$ by more than 6 dB and 9 %, respectively. Post-Layout EM (electromagnetic) simulation of PA illustrates maximum PAE of 19.6%, output $mathrm{P}_{-}1text{dB}$ of 15.76 dBm, PAE of 14% at 6dB back-off, 6 dB gain, and 19 dBm saturated output power. The layout area is 0.445 mm2.
{"title":"A 28GHz Harmonic Injection Doherty Power Amplifier","authors":"Armin Amirkhani, Negar Choupan, A. Nabavi","doi":"10.1109/IICM55040.2021.9730246","DOIUrl":"https://doi.org/10.1109/IICM55040.2021.9730246","url":null,"abstract":"In this paper, a 28 GHz fully on-chip Doherty power amplifier with harmonic injection is presented in 65 nm CMOS technology. In order to improve the linearity, two injection amplifier stages biased in class C are used. In this method, injection of the second harmonic compensates the gain compression phenomena and improves the output $mathrm{P}_{-}1text{dB}$ and PAE at $mathrm{P}_{-}1text{dB}$ by more than 6 dB and 9 %, respectively. Post-Layout EM (electromagnetic) simulation of PA illustrates maximum PAE of 19.6%, output $mathrm{P}_{-}1text{dB}$ of 15.76 dBm, PAE of 14% at 6dB back-off, 6 dB gain, and 19 dBm saturated output power. The layout area is 0.445 mm2.","PeriodicalId":299499,"journal":{"name":"2021 Iranian International Conference on Microelectronics (IICM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127786771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-22DOI: 10.1109/IICM55040.2021.9730570
Fazel Ziraksaz, A. Hassanzadeh
This paper presents a reconfigurable differential amplifier for 26GHz and 28GHz frequencies. This research uses the RF-MEMS switches to adjust different frequencies. The proposed structure is capable of achieving an output power of 22dBm and about 2.9V output swing. Simulation results of the proposed Tunable Wideband Differential Amplifier (TWDA) in 180 nm TSMC-CMOS technology shows the attenuation of the second to fifth harmonics between -20.7dBm and -43.75dBm for the frequency of 26GHz, and between -21.11dBm and-46.96dBm for the frequency of 28GHz, which indicates the appropriate linearity of the structure. Electrical and mechanical simulations in the Advance Design System (ADS) and COMSOL simulation software indicate the proposed structure's ability to adjust different frequencies for TWDA using RF-MEMS switches.
{"title":"Design of a Tunable Wideband Differential Amplifier Based on RF-MEMS Switches","authors":"Fazel Ziraksaz, A. Hassanzadeh","doi":"10.1109/IICM55040.2021.9730570","DOIUrl":"https://doi.org/10.1109/IICM55040.2021.9730570","url":null,"abstract":"This paper presents a reconfigurable differential amplifier for 26GHz and 28GHz frequencies. This research uses the RF-MEMS switches to adjust different frequencies. The proposed structure is capable of achieving an output power of 22dBm and about 2.9V output swing. Simulation results of the proposed Tunable Wideband Differential Amplifier (TWDA) in 180 nm TSMC-CMOS technology shows the attenuation of the second to fifth harmonics between -20.7dBm and -43.75dBm for the frequency of 26GHz, and between -21.11dBm and-46.96dBm for the frequency of 28GHz, which indicates the appropriate linearity of the structure. Electrical and mechanical simulations in the Advance Design System (ADS) and COMSOL simulation software indicate the proposed structure's ability to adjust different frequencies for TWDA using RF-MEMS switches.","PeriodicalId":299499,"journal":{"name":"2021 Iranian International Conference on Microelectronics (IICM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128473205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-22DOI: 10.1109/IICM55040.2021.9730268
Seyedeh Yasamin Hojat, H. F. Baghtash, E. N. Aghdam
A μW power low noise amplifier for low voltage direct-conversion receiver such as IOT applications is reported. The proposed structure features a cascode topology with capacitor cross coupling technique. Utilizing forward body bias technique enables the structure to operate at a very low supply voltage down to 0.4 V. The reduced power supply, on the other hand, eliminates the requirement for additional biasing circuits, that helps to further reduce the power consumption. Simulation results with 0.13μm CMOS technology shows the 1.37 dB NF along with high gain of 28.4 dB and a good input impedance matching of -23 dB in the 2.4 GHz operating center frequency.
{"title":"A 350μW Low Noise Amplifier for IOT Applications","authors":"Seyedeh Yasamin Hojat, H. F. Baghtash, E. N. Aghdam","doi":"10.1109/IICM55040.2021.9730268","DOIUrl":"https://doi.org/10.1109/IICM55040.2021.9730268","url":null,"abstract":"A μW power low noise amplifier for low voltage direct-conversion receiver such as IOT applications is reported. The proposed structure features a cascode topology with capacitor cross coupling technique. Utilizing forward body bias technique enables the structure to operate at a very low supply voltage down to 0.4 V. The reduced power supply, on the other hand, eliminates the requirement for additional biasing circuits, that helps to further reduce the power consumption. Simulation results with 0.13μm CMOS technology shows the 1.37 dB NF along with high gain of 28.4 dB and a good input impedance matching of -23 dB in the 2.4 GHz operating center frequency.","PeriodicalId":299499,"journal":{"name":"2021 Iranian International Conference on Microelectronics (IICM)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117066808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：