Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962750
M. Muller, M. Wohrmann, O. Wittler, V. Bader, M. Topper, K. Lang
For WLP (Wafer Level Packaging) thin film polymers play a key role in respect to board level reliability. This paper introduces a reliability indicator giving a tendency of the polymer material to crack initiation around the UBM pad. This indicator derived from Finite Element simulated maximum stress in polymer layer and the material specific tensile strength. Comparing the simulation results with the experimental data we see the same impact of the mechanical material properties on the reliability. This proves the described reliability indicator as suitable for estimating thermal cycle reliability of RDL polymer materials gives application engineers and manufacturers a new tool for selecting the most suitable RDL material for e.g. flip chip and WLP applications.
{"title":"Impact of RDL polymer on reliability of flip chip interconnects in thermal cycling — Correlation of experiments with finite element simulations","authors":"M. Muller, M. Wohrmann, O. Wittler, V. Bader, M. Topper, K. Lang","doi":"10.1109/ESTC.2014.6962750","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962750","url":null,"abstract":"For WLP (Wafer Level Packaging) thin film polymers play a key role in respect to board level reliability. This paper introduces a reliability indicator giving a tendency of the polymer material to crack initiation around the UBM pad. This indicator derived from Finite Element simulated maximum stress in polymer layer and the material specific tensile strength. Comparing the simulation results with the experimental data we see the same impact of the mechanical material properties on the reliability. This proves the described reliability indicator as suitable for estimating thermal cycle reliability of RDL polymer materials gives application engineers and manufacturers a new tool for selecting the most suitable RDL material for e.g. flip chip and WLP applications.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124356197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962717
K. Grigoras, J. Keskinen, J. Ahopelto, M. Prunnila
We demonstrate high performance porous Si based supercapacitor electrodes that can be utilized in integrated micro supercapacitors. The key enabler here is ultra-thin TiN coating of the porous Si matrix leading to high power and stability. The TiN layer is deposited by atomic layer deposition (ALD), which provides sufficient conformality to reach the bottom of the high aspect ratio pores. Our porous Si supercapacitor devices exhibit almost ideal double layer capacitor characteristic with electrode volumetric capacitance of 7.3 F/cm. Several orders of magnitude increase in power and energy density is obtained comparing to uncoated porous silicon electrodes. Good stability of devices is confirmed performing over 5 000 charge/discharge cycles.
{"title":"Porous silicon electrodes for high performance integrated supercapacitors","authors":"K. Grigoras, J. Keskinen, J. Ahopelto, M. Prunnila","doi":"10.1109/ESTC.2014.6962717","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962717","url":null,"abstract":"We demonstrate high performance porous Si based supercapacitor electrodes that can be utilized in integrated micro supercapacitors. The key enabler here is ultra-thin TiN coating of the porous Si matrix leading to high power and stability. The TiN layer is deposited by atomic layer deposition (ALD), which provides sufficient conformality to reach the bottom of the high aspect ratio pores. Our porous Si supercapacitor devices exhibit almost ideal double layer capacitor characteristic with electrode volumetric capacitance of 7.3 F/cm. Several orders of magnitude increase in power and energy density is obtained comparing to uncoated porous silicon electrodes. Good stability of devices is confirmed performing over 5 000 charge/discharge cycles.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114881295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962830
Zhefeng Xu, K. Matsugi, Yongbum Choi, Keigo Terada, K. Suetsugu
The effectiveness of the electronic parameter was evaluated in order to predict the mechanical properties of zinc system alloys for high temperature application. Firstly, the relation of ultimate tensile strength or elongation and s-orbital energy level (Δ Mk) of already reported Zn system multicomponent alloys were investigated. According to this relation, the lead-free Zn-Al-Sn system alloys have been proposed in order to satisfy both the tensile strength of 200 MPa and elongation of 5 %. Promising compositions of alloys were Zn-4Al-7Sn, Zn-10Al-0.5Sn and Zn-10Al-2Sn in mass % and their Δ Mk values were 0.079, 0.080 and 0.089, respectively. Proposed alloys showed tensile strength of 195-225 MPa depending on increment of Δ Mk values, and elongation of 4.5-5.1 %. The optimization of compositions on Zn alloys was found to be speedy and precisely achieved using the Δ Mk parameter. The proposed alloys also showed liquidus temperatures of 645-700K, indicating that the high temperature lead-free solders can be applied for power semiconductor devices packages, etc. In addition, the contact angles between Cu plate and the proposed alloys Zn-4Al-7Sn, Zn-10Al-0.5Sn and Zn-10Al-2Sn at 973 K in the Ar stream are 33.8°, 73.5°and 50.1°, respectively.
{"title":"Prediction of mechanical properties on zinc system alloys and their application to high temperature lead-free solder","authors":"Zhefeng Xu, K. Matsugi, Yongbum Choi, Keigo Terada, K. Suetsugu","doi":"10.1109/ESTC.2014.6962830","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962830","url":null,"abstract":"The effectiveness of the electronic parameter was evaluated in order to predict the mechanical properties of zinc system alloys for high temperature application. Firstly, the relation of ultimate tensile strength or elongation and s-orbital energy level (Δ Mk) of already reported Zn system multicomponent alloys were investigated. According to this relation, the lead-free Zn-Al-Sn system alloys have been proposed in order to satisfy both the tensile strength of 200 MPa and elongation of 5 %. Promising compositions of alloys were Zn-4Al-7Sn, Zn-10Al-0.5Sn and Zn-10Al-2Sn in mass % and their Δ Mk values were 0.079, 0.080 and 0.089, respectively. Proposed alloys showed tensile strength of 195-225 MPa depending on increment of Δ Mk values, and elongation of 4.5-5.1 %. The optimization of compositions on Zn alloys was found to be speedy and precisely achieved using the Δ Mk parameter. The proposed alloys also showed liquidus temperatures of 645-700K, indicating that the high temperature lead-free solders can be applied for power semiconductor devices packages, etc. In addition, the contact angles between Cu plate and the proposed alloys Zn-4Al-7Sn, Zn-10Al-0.5Sn and Zn-10Al-2Sn at 973 K in the Ar stream are 33.8°, 73.5°and 50.1°, respectively.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116401287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962738
J. Souriau, L. Castagné, G. Parat, P. Nicolas, P. Charvet, G. Simon, Karima Amara, Philippe D'hiver, B. Boutaud, R. Dal Molin
Progressive cardiac diseases due to population aging lead to stimulate research and innovation. Moreover, recent development in the miniaturization of microsystem offers a tremendous opportunity for medical implantable application. This paper introduces a new technology that integrates a Micro Electro-Mechanical Systems (MEMS) accelerometer and an Application-Specific Integrated Circuit (ASIC) inside a hermetic silicon box that could be embedded in a cardiac lead in order to monitor the endocardial acceleration signal. The electronic components are attached on a wafer silicon interposer and encapsulated in a wafer silicon lid which is bonded using eutectic AuSi. The originality of the approach consists in using an interposer and a lid, both made of conductive doped silicon, to connect the device. The process is performed at the wafer level. The silicon box is finally connected to the electrical generator outside the heart thanks to two conductor wires. A prototype is described in this paper. The gas content and hermeticity of the package were analyzed using different techniques such as Residual Gas Analysis (RGA) and Helium or Krypton 85 testing. An estimate of the leak rate, which is assessed based on the formation of water droplet condensation in our package after 20 years, was evaluated.
{"title":"Characterization of a hermetic silicon box fitted in a cardiac lead in order to measure the endocardial acceleration signal","authors":"J. Souriau, L. Castagné, G. Parat, P. Nicolas, P. Charvet, G. Simon, Karima Amara, Philippe D'hiver, B. Boutaud, R. Dal Molin","doi":"10.1109/ESTC.2014.6962738","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962738","url":null,"abstract":"Progressive cardiac diseases due to population aging lead to stimulate research and innovation. Moreover, recent development in the miniaturization of microsystem offers a tremendous opportunity for medical implantable application. This paper introduces a new technology that integrates a Micro Electro-Mechanical Systems (MEMS) accelerometer and an Application-Specific Integrated Circuit (ASIC) inside a hermetic silicon box that could be embedded in a cardiac lead in order to monitor the endocardial acceleration signal. The electronic components are attached on a wafer silicon interposer and encapsulated in a wafer silicon lid which is bonded using eutectic AuSi. The originality of the approach consists in using an interposer and a lid, both made of conductive doped silicon, to connect the device. The process is performed at the wafer level. The silicon box is finally connected to the electrical generator outside the heart thanks to two conductor wires. A prototype is described in this paper. The gas content and hermeticity of the package were analyzed using different techniques such as Residual Gas Analysis (RGA) and Helium or Krypton 85 testing. An estimate of the leak rate, which is assessed based on the formation of water droplet condensation in our package after 20 years, was evaluated.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128903989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962848
S. Lahokallio, J. Kiilunen, L. Frisk
Radio frequency identification (RFID) tags are typically used for object identification in environments in which they are not exposed to very harsh conditions. However, there is an increasing demand for inexpensive RFID tags for use in harsh industrial environments, but the adequate performance of the materials used in them needs to be verified in such conditions. This paper reports the reliability of passive RFID tags studied in a high temperature cycling test combined with water immersion. According to the threshold power measurements taken in between the test periods, the RFID tags were able to withstand high temperature cycling. However, cycling testing combined with frequent water immersion impaired their reliability, leading mostly to intermittent failures.
{"title":"Performance of passive RFID tags in a high temperature cycling test","authors":"S. Lahokallio, J. Kiilunen, L. Frisk","doi":"10.1109/ESTC.2014.6962848","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962848","url":null,"abstract":"Radio frequency identification (RFID) tags are typically used for object identification in environments in which they are not exposed to very harsh conditions. However, there is an increasing demand for inexpensive RFID tags for use in harsh industrial environments, but the adequate performance of the materials used in them needs to be verified in such conditions. This paper reports the reliability of passive RFID tags studied in a high temperature cycling test combined with water immersion. According to the threshold power measurements taken in between the test periods, the RFID tags were able to withstand high temperature cycling. However, cycling testing combined with frequent water immersion impaired their reliability, leading mostly to intermittent failures.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"110 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131073484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962801
Tan Wei Hing, Paing Samsun, W. Teng
In power device package development, super high thermal performance adhesive either solder or polymeric adhesive are highly desired for better thermal resistance and RDSON. High thermal polymeric adhesive consists of high silver loading, unique thermoset resin, and solvent. Solvent evaporates during oven curing, silver flakes will be compacted to generate high thermal and electrical conductivity. Thermal and electrical properties increase directly with degree of compactness. This paper reveals 23.5W/K.m adhesive, applying average thin bondline, minimize creation of voids, good interfacial adhesion are essential to meet TO and SOIC package thermal resistance. Furthermore, proper selection of leadframe finishing is essential to prevent package delamination and also improves package thermal resistance by 12%. Working principle of high thermal adhesive increases the challenges of processability. Solvent raises the concern of voids, high silver loading increases the risk of dispensability and reliability test, lower basic resin content may reduce the adhesion strength. Solvent is added in to improve dispensability, however solvent evaporation in oven may causing channeling voids. Thus, optimizing curing profile by isothermal TGA is essential to ensure curability and elastic modulus properties are maintained. Isothermal TGA shows that higher hold temperature and longer hold time is needed to drive out all the solvent before the adhesive is fully cured. Staging time (open time) is another crucial control to minimize void formation. Two types of staging time, which are duration between epoxy dispensing to die attach & duration between die attach to curing control are established to ensure good dispensability, glue coverage, void formation and die shear strength. Higher filler loading in adhesive increases the probability of needle clogging, `missing dot' and inconsistency of dispensing. Thus resulting insufficient glue coverage, voids and high yield loss. Proper selection of nozzle size improves `missing dot' and dispensing consistency. The internal design of shower head is important factor to improve dispensability. Shower head dispensing and writing methodology are studies, result reveals that writing method on high filler loading adhesive give comparable result with shower head dispensing method. Despites the challenges of die bond process on high filler loading adhesives, high thermal adhesive has its advantage to achieve thicker bond line thickness due to high silver loading. This enhances reliability performance and process yield.
{"title":"Challenges of super high thermal performance adhesive in power device application","authors":"Tan Wei Hing, Paing Samsun, W. Teng","doi":"10.1109/ESTC.2014.6962801","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962801","url":null,"abstract":"In power device package development, super high thermal performance adhesive either solder or polymeric adhesive are highly desired for better thermal resistance and RDSON. High thermal polymeric adhesive consists of high silver loading, unique thermoset resin, and solvent. Solvent evaporates during oven curing, silver flakes will be compacted to generate high thermal and electrical conductivity. Thermal and electrical properties increase directly with degree of compactness. This paper reveals 23.5W/K.m adhesive, applying average thin bondline, minimize creation of voids, good interfacial adhesion are essential to meet TO and SOIC package thermal resistance. Furthermore, proper selection of leadframe finishing is essential to prevent package delamination and also improves package thermal resistance by 12%. Working principle of high thermal adhesive increases the challenges of processability. Solvent raises the concern of voids, high silver loading increases the risk of dispensability and reliability test, lower basic resin content may reduce the adhesion strength. Solvent is added in to improve dispensability, however solvent evaporation in oven may causing channeling voids. Thus, optimizing curing profile by isothermal TGA is essential to ensure curability and elastic modulus properties are maintained. Isothermal TGA shows that higher hold temperature and longer hold time is needed to drive out all the solvent before the adhesive is fully cured. Staging time (open time) is another crucial control to minimize void formation. Two types of staging time, which are duration between epoxy dispensing to die attach & duration between die attach to curing control are established to ensure good dispensability, glue coverage, void formation and die shear strength. Higher filler loading in adhesive increases the probability of needle clogging, `missing dot' and inconsistency of dispensing. Thus resulting insufficient glue coverage, voids and high yield loss. Proper selection of nozzle size improves `missing dot' and dispensing consistency. The internal design of shower head is important factor to improve dispensability. Shower head dispensing and writing methodology are studies, result reveals that writing method on high filler loading adhesive give comparable result with shower head dispensing method. Despites the challenges of die bond process on high filler loading adhesives, high thermal adhesive has its advantage to achieve thicker bond line thickness due to high silver loading. This enhances reliability performance and process yield.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132003960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962736
E. Andreassen, M. Mielnik
We present a new heterogeneous integration method which enables direct incorporation of silicon-based microfluidic components in an injection-moulded polymer lab-on-a-chip (LOC). The integration is performed as part of the injection moulding process, forming direct fluidic junctions between the polymer and the silicon chip while embedding the silicon chip in the polymer chip. We have demonstrated that such fluidic junctions can withstand at least 3 bars of liquid pressure. With this integration method, the fluidic interface between the silicon chip and the polymer chip can be made compact and free of dead-volume. The method opens for mass fabrication of highly functional, heterogeneous LOC systems containing MEMS and NEMS components such as biosensors and actuators integrated in the polymer chip.
{"title":"BioMEMS meets lab-on-a-chip: Heterogeneous integration of silicon MEMS and NEMS in polymer microfluidics","authors":"E. Andreassen, M. Mielnik","doi":"10.1109/ESTC.2014.6962736","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962736","url":null,"abstract":"We present a new heterogeneous integration method which enables direct incorporation of silicon-based microfluidic components in an injection-moulded polymer lab-on-a-chip (LOC). The integration is performed as part of the injection moulding process, forming direct fluidic junctions between the polymer and the silicon chip while embedding the silicon chip in the polymer chip. We have demonstrated that such fluidic junctions can withstand at least 3 bars of liquid pressure. With this integration method, the fluidic interface between the silicon chip and the polymer chip can be made compact and free of dead-volume. The method opens for mass fabrication of highly functional, heterogeneous LOC systems containing MEMS and NEMS components such as biosensors and actuators integrated in the polymer chip.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130816029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962751
D. Jiang, Shuangxi Sun, W. Mu, Yifeng Fu, Johan Liu
A carbon nanotube (CNT)/Solder hybrid bump structure is proposed in this work in order to overcome the drawbacks of high CNT resistivity while retaining the advantages of CNTs in terms of interconnect reliability. Lithographically defined hollow CNT moulds are grown by thermal chemical vapor deposition (TCVD). The space inside the CNT moulds is filled up with Sn-Au-Cu (SAC) solder spheres of around 10 μm in diameter. This CNT/Solder hybrid material is then reflowed and transferred onto target indium coated substrate. The reflow melts the small solder spheres into large single solder balls thus forming a hybrid interconnect bump together with the surrounding densified CNT walls, which the CNT and the solder serve as resistors in parallel. The electrical resistance of such a CNT/Solder structure is measured to be around 6 folds lower than pure CNT bumps.
{"title":"Carbon nanotube/solder hybrid structure for interconnect applications","authors":"D. Jiang, Shuangxi Sun, W. Mu, Yifeng Fu, Johan Liu","doi":"10.1109/ESTC.2014.6962751","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962751","url":null,"abstract":"A carbon nanotube (CNT)/Solder hybrid bump structure is proposed in this work in order to overcome the drawbacks of high CNT resistivity while retaining the advantages of CNTs in terms of interconnect reliability. Lithographically defined hollow CNT moulds are grown by thermal chemical vapor deposition (TCVD). The space inside the CNT moulds is filled up with Sn-Au-Cu (SAC) solder spheres of around 10 μm in diameter. This CNT/Solder hybrid material is then reflowed and transferred onto target indium coated substrate. The reflow melts the small solder spheres into large single solder balls thus forming a hybrid interconnect bump together with the surrounding densified CNT walls, which the CNT and the solder serve as resistors in parallel. The electrical resistance of such a CNT/Solder structure is measured to be around 6 folds lower than pure CNT bumps.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129231490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962720
A. Goldberg, M. Ihle, S. Ziesche, Robert Kulls
The Low-Temperature Cofired Ceramic Technology (LTCC) based package shown here is an example of a special customized surface mount device (SMD) solution following the requirements of a high-g acceleration sensor. The main focus was the development of an economically viable packaging-solution. For achieving this goal attention was paid to the aspects of cost reduction by miniaturization and to the use of cost-effective materials. LTCC was chosen as the preferred manufacturing technology because of the possibility to integrate electrical wiring inside the ceramic. Using this technology a ceramic packaging with gas-tight sealing, solderable SMD contacts and an electrically and mechanically stable solution could be developed and manufactured [5].
{"title":"Development of a robust, ceramic MEMS-package for hermetically sealed and highly shock-resistant SMD-devices","authors":"A. Goldberg, M. Ihle, S. Ziesche, Robert Kulls","doi":"10.1109/ESTC.2014.6962720","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962720","url":null,"abstract":"The Low-Temperature Cofired Ceramic Technology (LTCC) based package shown here is an example of a special customized surface mount device (SMD) solution following the requirements of a high-g acceleration sensor. The main focus was the development of an economically viable packaging-solution. For achieving this goal attention was paid to the aspects of cost reduction by miniaturization and to the use of cost-effective materials. LTCC was chosen as the preferred manufacturing technology because of the possibility to integrate electrical wiring inside the ceramic. Using this technology a ceramic packaging with gas-tight sealing, solderable SMD contacts and an electrically and mechanically stable solution could be developed and manufactured [5].","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116765301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962859
Aylin Bicakci, Ronald Eisele, F. Osterwald, K. Olesen
A study and comparison of substrates with ceramic and organic electrically insulating and thermally conductive layers for power electronic packages is presented. Reference is made to the “die on leadframe”-technology, to compare these structures with a commercial ceramic substrate. The focus of the study is on the thermal properties of the structures. Furthermore, a comprehensive overview of test methods and results for the breakdown voltage and the sheer strengths of the tested organic layers is given. The test results will be evaluated, if organic layers could be used as a substitute for standard ceramic substrates.
{"title":"Comparison between organic and ceramic substrate insulation","authors":"Aylin Bicakci, Ronald Eisele, F. Osterwald, K. Olesen","doi":"10.1109/ESTC.2014.6962859","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962859","url":null,"abstract":"A study and comparison of substrates with ceramic and organic electrically insulating and thermally conductive layers for power electronic packages is presented. Reference is made to the “die on leadframe”-technology, to compare these structures with a commercial ceramic substrate. The focus of the study is on the thermal properties of the structures. Furthermore, a comprehensive overview of test methods and results for the breakdown voltage and the sheer strengths of the tested organic layers is given. The test results will be evaluated, if organic layers could be used as a substitute for standard ceramic substrates.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125215857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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