Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962728
Y. Araga, Ranto Miura, M. Nagata, C. Neve, J. de Vos, G. van der Plas, E. Beyne
A 3D-integrated test vehicle that emulates noise generation and propagation in a heterogeneous integrated system has been developed. In-stack waveform capturers are embedded on each tier which captured the generation and propagation of noise. A consistent analytical model is created and analysis using that model has allowed us to develop a design strategy for the power delivery network to attenuate noise propagation in the stacked system.
{"title":"A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring","authors":"Y. Araga, Ranto Miura, M. Nagata, C. Neve, J. de Vos, G. van der Plas, E. Beyne","doi":"10.1109/ESTC.2014.6962728","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962728","url":null,"abstract":"A 3D-integrated test vehicle that emulates noise generation and propagation in a heterogeneous integrated system has been developed. In-stack waveform capturers are embedded on each tier which captured the generation and propagation of noise. A consistent analytical model is created and analysis using that model has allowed us to develop a design strategy for the power delivery network to attenuate noise propagation in the stacked system.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126996274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962861
J. Strogies, K. Wilke
This article outlines the realization of a universal joining technology that provides high temperature compliant solder joints. Major achievement of provided solutions is to overcome the conflict of objectives concerning low thermal budget to joining partners during assembly processes and high melting points of the resultant joints during operation. One cost effective approach to solve this conflict is diffusion soldering. In contrast to thermal solidification this soldering variant uses concentration change of materials to achieve at least locally high-melting intermetallic phases. Comprehensive evaluations of potential material systems led to a simple binary system of Sn and Cu with eutectic composition at SnCu0.7 (melting temperature 227°C) and high melting-temperature phases Cu6Sn5 (Tm about 415°C) and Cu3Sn (Tm about 670°C). Diffusion soldering is used already in wafer to wafer and chip to lead frame soldering technologies. To achieve a universal joining technology with focus on wide range of chip to ceramic and second level assembly in the field of surface mount technology the challenge of short bridgeable distances has to be solved by technical creases. This article outlines technical solutions of dispersed Cu particles and special topographic elements that provide the potential to increase joining zones up to 100 μm. Process flows and equipment for major technological solutions are described. Potential adaption in mass production and results of technical reliability are shown. In addition comprehensive analysis results of metallographic investigations are shown to give an introduction to new challenges of diffusion soldered interconnects.
{"title":"Universal high-temperature suitable joint adapting diffusion soldering","authors":"J. Strogies, K. Wilke","doi":"10.1109/ESTC.2014.6962861","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962861","url":null,"abstract":"This article outlines the realization of a universal joining technology that provides high temperature compliant solder joints. Major achievement of provided solutions is to overcome the conflict of objectives concerning low thermal budget to joining partners during assembly processes and high melting points of the resultant joints during operation. One cost effective approach to solve this conflict is diffusion soldering. In contrast to thermal solidification this soldering variant uses concentration change of materials to achieve at least locally high-melting intermetallic phases. Comprehensive evaluations of potential material systems led to a simple binary system of Sn and Cu with eutectic composition at SnCu0.7 (melting temperature 227°C) and high melting-temperature phases Cu6Sn5 (Tm about 415°C) and Cu3Sn (Tm about 670°C). Diffusion soldering is used already in wafer to wafer and chip to lead frame soldering technologies. To achieve a universal joining technology with focus on wide range of chip to ceramic and second level assembly in the field of surface mount technology the challenge of short bridgeable distances has to be solved by technical creases. This article outlines technical solutions of dispersed Cu particles and special topographic elements that provide the potential to increase joining zones up to 100 μm. Process flows and equipment for major technological solutions are described. Potential adaption in mass production and results of technical reliability are shown. In addition comprehensive analysis results of metallographic investigations are shown to give an introduction to new challenges of diffusion soldered interconnects.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127932067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962833
Z. Sárkány, A. Vass-Várnai, M. Rencz
Power cycling is a widely used accelerated lifetime testing method to evaluate the reliability of power modules and discrete components. Based on the accelerated test results one can deduce the lifetime of these devices in normal operation conditions. Although, we have to be careful, because not only the initial parameters, but the control strategy used during the cycling tests may also affect the measured lifetime. In this paper we present the results of a power cycling experiment, which was carried out using three different cycling strategies. Several electrical parameters were measured in each cycle and thermal transient results were captured at regular intervals to enable evaluating how the failures evolve in the different cycling strategies.
{"title":"Comparison of different power cycling strategies for accelerated lifetime testing of power devices","authors":"Z. Sárkány, A. Vass-Várnai, M. Rencz","doi":"10.1109/ESTC.2014.6962833","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962833","url":null,"abstract":"Power cycling is a widely used accelerated lifetime testing method to evaluate the reliability of power modules and discrete components. Based on the accelerated test results one can deduce the lifetime of these devices in normal operation conditions. Although, we have to be careful, because not only the initial parameters, but the control strategy used during the cycling tests may also affect the measured lifetime. In this paper we present the results of a power cycling experiment, which was carried out using three different cycling strategies. Several electrical parameters were measured in each cycle and thermal transient results were captured at regular intervals to enable evaluating how the failures evolve in the different cycling strategies.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"93 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132947052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962829
Åsmund Sandvand, E. Halvorsen, K. Aasmundtveit
A MEMS pressure-sensor, including its vacuum reference cavity, is modelled with focus on resulting stress from a glass frit bonding process. Based on CT-scans of bonded samples, a parametric model for FEM analysis of observed variations in bonding material distribution has been developed. Simulations show a high influence of amount and distribution of excess glass frit material on the zero-point as well as a good correlation with manufacturing data. Simulated variations of glass frit material distribution shows a variation of the zero-point of -1.5 % full scale (FS) to -7.2 %FS, depending on configuration.
{"title":"Finite element modelling of influence of bonding material distribution in precision piezoresistive MEMS pressure-sensors","authors":"Åsmund Sandvand, E. Halvorsen, K. Aasmundtveit","doi":"10.1109/ESTC.2014.6962829","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962829","url":null,"abstract":"A MEMS pressure-sensor, including its vacuum reference cavity, is modelled with focus on resulting stress from a glass frit bonding process. Based on CT-scans of bonded samples, a parametric model for FEM analysis of observed variations in bonding material distribution has been developed. Simulations show a high influence of amount and distribution of excess glass frit material on the zero-point as well as a good correlation with manufacturing data. Simulated variations of glass frit material distribution shows a variation of the zero-point of -1.5 % full scale (FS) to -7.2 %FS, depending on configuration.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"47 38","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134225587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962815
T. Tilford, A. Cook, H. Lu, A. Ramambasoa, F. Conseil
An inverse analysis approach combining numerical and experimental analyses has been utilised to determine the in-situ effective material properties of Highly Oriented Pyrolytic Graphite (HOPG) in a microelectronics test assembly. The approach adopted uses a Finite Element analysis package to determine temperature distribution over a thermal test assembly. A Virtual Design of Experiments approach is used to define a series of analyses with discrete thermal material properties which is used in conjunction with a particle swarm optimisation algorithm to form a response surface function relating temperature to material property values at a number of monitoring points. Experimental data is used to form an error metric which is subsequently minimised to determine effective material properties of the HOPG material. Subsequently a series of studies contrasting the performance of the HOPG material with common heat spreader materials were performed. Results show that the effective thermal property values of the HOPG material seem to be greater than suggested in existing literature and that the HOPG material reduces peak assembly temperatures by a significant amount.
{"title":"Numerical analysis of the performance of highly oriented pyrolytic graphite heat spreader in thermal management of microelectronics assemblies","authors":"T. Tilford, A. Cook, H. Lu, A. Ramambasoa, F. Conseil","doi":"10.1109/ESTC.2014.6962815","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962815","url":null,"abstract":"An inverse analysis approach combining numerical and experimental analyses has been utilised to determine the in-situ effective material properties of Highly Oriented Pyrolytic Graphite (HOPG) in a microelectronics test assembly. The approach adopted uses a Finite Element analysis package to determine temperature distribution over a thermal test assembly. A Virtual Design of Experiments approach is used to define a series of analyses with discrete thermal material properties which is used in conjunction with a particle swarm optimisation algorithm to form a response surface function relating temperature to material property values at a number of monitoring points. Experimental data is used to form an error metric which is subsequently minimised to determine effective material properties of the HOPG material. Subsequently a series of studies contrasting the performance of the HOPG material with common heat spreader materials were performed. Results show that the effective thermal property values of the HOPG material seem to be greater than suggested in existing literature and that the HOPG material reduces peak assembly temperatures by a significant amount.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132731494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962850
M. Mostofizadeh, L. Frisk
Most of the commonly used lead-free solders have a high melting temperature. However, in many applications a lower processing temperature would be beneficial. Therefore a demand has arisen for reliable lead-free solder with a lower melting temperature. Among the low temperature lead-free solders, Sn-9Zn and Sn-8Zn-3Bi (wt.%) are suitable candidates for many applications, since they offer good mechanical reliability and melting temperature similar to that of Sn-Pb solders. However, because they contain an active element (Zn), they need to be used with caution, especially in corrosive environments and in high-temperature applications. In this paper the corrosion behavior of Sn-8Zn-3Bi lead-free solder was studied using a salt spray test. The microstructure of the solder was studied at different time intervals during the salt spray test. Sn-36Pb-2Ag (wt.%) solder joints were also studied as reference samples. It was found that Sn-8Zn-3Bi suffered from galvanic corrosion earlier than the Sn-Pb-2Ag solders. However, considerable corrosion was observed after the salt spray test in both solders. Moreover, it seemed that the corrosion performance of Sn-Pb-2Ag solder was better than that of Sn-8Zn-3Bi solder.
{"title":"Corrosion behavior of Sn-Zn-Bi and Sn-Pb-Ag solders in a salt spray test","authors":"M. Mostofizadeh, L. Frisk","doi":"10.1109/ESTC.2014.6962850","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962850","url":null,"abstract":"Most of the commonly used lead-free solders have a high melting temperature. However, in many applications a lower processing temperature would be beneficial. Therefore a demand has arisen for reliable lead-free solder with a lower melting temperature. Among the low temperature lead-free solders, Sn-9Zn and Sn-8Zn-3Bi (wt.%) are suitable candidates for many applications, since they offer good mechanical reliability and melting temperature similar to that of Sn-Pb solders. However, because they contain an active element (Zn), they need to be used with caution, especially in corrosive environments and in high-temperature applications. In this paper the corrosion behavior of Sn-8Zn-3Bi lead-free solder was studied using a salt spray test. The microstructure of the solder was studied at different time intervals during the salt spray test. Sn-36Pb-2Ag (wt.%) solder joints were also studied as reference samples. It was found that Sn-8Zn-3Bi suffered from galvanic corrosion earlier than the Sn-Pb-2Ag solders. However, considerable corrosion was observed after the salt spray test in both solders. Moreover, it seemed that the corrosion performance of Sn-Pb-2Ag solder was better than that of Sn-8Zn-3Bi solder.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121055404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962780
V. Giagka, A. Vanhoestenberghe, N. Donaldson, A. Demosthenous
We are developing an active implant for epidural spinal cord stimulation. A thin application specific integrated circuit (ASIC) (~80 μm) is to be embedded within it. The laser patterned tracks are electrically and mechanically thermosonically bonded on the ASIC pads using gold ball studs, forming micro-rivets through holes in the foil of the tracks, an interconnection method called electrical rivet bonding, or microflex [1]. In this work, we sought to characterize and optimize the technique, with respect to its bonding strength. The technique is relatively new and, so far, the mechanical strength of the bonds has only been investigated for interconnection on gold tracks. Standard ASICs however, normally come with aluminium pads. We ran a series of pull tests on the bonds between the metal tracks and aluminium ASIC pads. In these tests, we were concerned with the effect of the different parameters on the bond strength, and more specifically the size of the gold balls and the size of the holes in the foil. We recorded the maximum force (stress) before bond failure for different combinations of parameters. Our results indicate that average stress values can vary between 9.6 and 60 cN, depending on the process parameters. Different failure mechanisms have been identified and these are discussed. Overall, we conclude that larger holes provide larger contact areas with the substrate and generally result in stronger bonds, but the right combination of ball and hole sizes, could lead to strong bonds even with smaller holes.
{"title":"Evaluation and optimization of the mechanical strength of bonds between metal foil and aluminium pads on thin ASICs using gold ball studs as micro-rivets","authors":"V. Giagka, A. Vanhoestenberghe, N. Donaldson, A. Demosthenous","doi":"10.1109/ESTC.2014.6962780","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962780","url":null,"abstract":"We are developing an active implant for epidural spinal cord stimulation. A thin application specific integrated circuit (ASIC) (~80 μm) is to be embedded within it. The laser patterned tracks are electrically and mechanically thermosonically bonded on the ASIC pads using gold ball studs, forming micro-rivets through holes in the foil of the tracks, an interconnection method called electrical rivet bonding, or microflex [1]. In this work, we sought to characterize and optimize the technique, with respect to its bonding strength. The technique is relatively new and, so far, the mechanical strength of the bonds has only been investigated for interconnection on gold tracks. Standard ASICs however, normally come with aluminium pads. We ran a series of pull tests on the bonds between the metal tracks and aluminium ASIC pads. In these tests, we were concerned with the effect of the different parameters on the bond strength, and more specifically the size of the gold balls and the size of the holes in the foil. We recorded the maximum force (stress) before bond failure for different combinations of parameters. Our results indicate that average stress values can vary between 9.6 and 60 cN, depending on the process parameters. Different failure mechanisms have been identified and these are discussed. Overall, we conclude that larger holes provide larger contact areas with the substrate and generally result in stronger bonds, but the right combination of ball and hole sizes, could lead to strong bonds even with smaller holes.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116355138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962832
Hao Zhang, S. Nagao, Sungwon Park, Shunsuke Koga, T. Sugahara, K. Suganuma
Low temperature and low pressure sintering Ag paste composed by sub-micro Ag particle and organic solvent was presented. The apparent improvement of bonding strength was realized by adding small amount of nano thickness Ag flake. Optimum proportion of sub-micro particle and nano thickness flake was determined. Nano-SiC particles were added into the optimized paste for sake of the possibility of properties advancement. The electrical property of newly developed Ag paste was measured by an improved test method. SiC die attachment and DBC (Direct Bonding Cu) substrate was conducted to test the practical application prospect of newly developed Nano-SiC added Ag paste.
{"title":"Nano-SiC added Ag paste sintering die-attach for SiC power devices","authors":"Hao Zhang, S. Nagao, Sungwon Park, Shunsuke Koga, T. Sugahara, K. Suganuma","doi":"10.1109/ESTC.2014.6962832","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962832","url":null,"abstract":"Low temperature and low pressure sintering Ag paste composed by sub-micro Ag particle and organic solvent was presented. The apparent improvement of bonding strength was realized by adding small amount of nano thickness Ag flake. Optimum proportion of sub-micro particle and nano thickness flake was determined. Nano-SiC particles were added into the optimized paste for sake of the possibility of properties advancement. The electrical property of newly developed Ag paste was measured by an improved test method. SiC die attachment and DBC (Direct Bonding Cu) substrate was conducted to test the practical application prospect of newly developed Nano-SiC added Ag paste.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115226664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962760
Younsu Jung, Hyejin Park, Jin-Ah Park, J. Noh, Yunchang Choi, M. Jung, Kyunghwan Jung, Myungho Pyo, Kevin Chen, A. Javey, Gyoujin Cho
For the first time, fully gravure printed wireless cyclic voltammetry (CV) tag is reported as a platform for the disposable wireless sensor tags by utilizing Ag nano-particle based conducting ink, BaTiO3 nano-particle based dielectric ink and single-walled carbon nanotube based semiconducting ink. The printed CV tag contains four functional units for the disposable wireless sensor tag: the rectenna to generate polarized DC volt through coupled 13.56 MHz AC, triangle wave generator to scan electrochemical cell by ±500 mV at lower frequency (<; 500 mHz), amplifier to enhance the output signal and signage to indicate detected level of specimens. Those printed four units will be used as a platform to further develop disposable wireless sensor tags by simply replacing sensor unit.
{"title":"Fully gravure printed wireless cyclic voltammetry tags","authors":"Younsu Jung, Hyejin Park, Jin-Ah Park, J. Noh, Yunchang Choi, M. Jung, Kyunghwan Jung, Myungho Pyo, Kevin Chen, A. Javey, Gyoujin Cho","doi":"10.1109/ESTC.2014.6962760","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962760","url":null,"abstract":"For the first time, fully gravure printed wireless cyclic voltammetry (CV) tag is reported as a platform for the disposable wireless sensor tags by utilizing Ag nano-particle based conducting ink, BaTiO3 nano-particle based dielectric ink and single-walled carbon nanotube based semiconducting ink. The printed CV tag contains four functional units for the disposable wireless sensor tag: the rectenna to generate polarized DC volt through coupled 13.56 MHz AC, triangle wave generator to scan electrochemical cell by ±500 mV at lower frequency (<; 500 mHz), amplifier to enhance the output signal and signage to indicate detected level of specimens. Those printed four units will be used as a platform to further develop disposable wireless sensor tags by simply replacing sensor unit.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116691218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962809
Markus Jarn, Chueh-An Hsieh, Yu-Chi Pai, Tsaiying Wang, J. Hunt
Wafer level packaging (WLP) of electronic components has become increasingly popular in recent years. The WLP package has the same foot print as the die and is therefore the smallest package possible. This is important for applications where maximum functionality is required in a small space, especially for mobile devices. The largest package sizes and pin counts used for WLP components have steadily increased in recent years. As the mechanical stresses in WLP packages increase with die size as well, board level reliability becomes a major concern. As such, the questions arise: what is the maximum die size possible for a WLP to meet board level reliability requirements and, for a given package size, how can the board level reliability be improved? To start to answer these questions, we have designed a large die test vehicle based on a dummy wafer (8×8 mm in size with 444 connections at 0.4mm pitch) with features in the package that are common to devices in production today, such as redistribution traces, polymer passivation layers, under bump metallization, and solder balls for interconnection to the test board. Using wafer level processes, we have assembled the test vehicles under different conditions in a design of experiment. We varied the parameters of polymer passivation thickness, redistribution trace thickness, and final die thickness and then characterized the board level reliability under temperature cycling and drop test conditions for a statistically significant sample size.
{"title":"Reliability investigations of large die wafer level packages: Optimization of package structure and materials to improve board level reliability","authors":"Markus Jarn, Chueh-An Hsieh, Yu-Chi Pai, Tsaiying Wang, J. Hunt","doi":"10.1109/ESTC.2014.6962809","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962809","url":null,"abstract":"Wafer level packaging (WLP) of electronic components has become increasingly popular in recent years. The WLP package has the same foot print as the die and is therefore the smallest package possible. This is important for applications where maximum functionality is required in a small space, especially for mobile devices. The largest package sizes and pin counts used for WLP components have steadily increased in recent years. As the mechanical stresses in WLP packages increase with die size as well, board level reliability becomes a major concern. As such, the questions arise: what is the maximum die size possible for a WLP to meet board level reliability requirements and, for a given package size, how can the board level reliability be improved? To start to answer these questions, we have designed a large die test vehicle based on a dummy wafer (8×8 mm in size with 444 connections at 0.4mm pitch) with features in the package that are common to devices in production today, such as redistribution traces, polymer passivation layers, under bump metallization, and solder balls for interconnection to the test board. Using wafer level processes, we have assembled the test vehicles under different conditions in a design of experiment. We varied the parameters of polymer passivation thickness, redistribution trace thickness, and final die thickness and then characterized the board level reliability under temperature cycling and drop test conditions for a statistically significant sample size.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122384159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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