Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962754
K. Elian, H. Theuss
This paper introduces a novel assembly and manufacturing technology for integrating permanent magnets into magnet sensor modules by use of plastic bonded magnets. High precision speed sensors in automotive applications, e.g. in anti-blocking-system or engine management, are based on a magnetic measurement principle [1]. Typical sensor modules contain a semiconductor based sensor chip and a permanent magnet providing the necessary bias field (see Fig. 1). This field is modulated by a passing external gear wheel out of material with high magnetic permeability, which is part of the magnetic circuit. The wheel speed can directly be determined by measuring the frequency of the magnetic field modulation. Permanent magnets are often assembled in a sequential pick and place process. We report a novel assembly technology by direct molding of thermoplast bonded magnets onto a chip carrier containing pre-assembled sensors. We will show, that this offers the following advantages: - Highest accuracy - Optimum working point, in particular for GMR sensors - High throughput by efficient parallel process - Simplification of the module assembly.
{"title":"Integration of polymer bonded magnets into magnetic sensors","authors":"K. Elian, H. Theuss","doi":"10.1109/ESTC.2014.6962754","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962754","url":null,"abstract":"This paper introduces a novel assembly and manufacturing technology for integrating permanent magnets into magnet sensor modules by use of plastic bonded magnets. High precision speed sensors in automotive applications, e.g. in anti-blocking-system or engine management, are based on a magnetic measurement principle [1]. Typical sensor modules contain a semiconductor based sensor chip and a permanent magnet providing the necessary bias field (see Fig. 1). This field is modulated by a passing external gear wheel out of material with high magnetic permeability, which is part of the magnetic circuit. The wheel speed can directly be determined by measuring the frequency of the magnetic field modulation. Permanent magnets are often assembled in a sequential pick and place process. We report a novel assembly technology by direct molding of thermoplast bonded magnets onto a chip carrier containing pre-assembled sensors. We will show, that this offers the following advantages: - Highest accuracy - Optimum working point, in particular for GMR sensors - High throughput by efficient parallel process - Simplification of the module assembly.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122462572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962762
H. Majumdar, J. Leppaniemi, K. Ojanpera, Olli‐Heikki Huttunen, A. Alastalo
This paper focuses on ultra-violet (UV)-curing of solution-processed metal-oxide (MO) semiconductors for application in thin film transistors (TFTs). The goal is to combine low-temperature thermal annealing with UV exposure and achieve printable transistors on flexible plastic substrates. In this paper we focus on the use of two different wavelengths of UV and clarify their effect on the performance of the metal-oxide semiconductors. The electrical properties of TFTs made with these semiconductors are characterized. The results show that wavelength of the UV exposure is critical for optimized performance of the semiconductor and the TFTs.
{"title":"Effect of UV light and low temperature on solution-processed, high-performance metal-oxide semiconductors and TFTs","authors":"H. Majumdar, J. Leppaniemi, K. Ojanpera, Olli‐Heikki Huttunen, A. Alastalo","doi":"10.1109/ESTC.2014.6962762","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962762","url":null,"abstract":"This paper focuses on ultra-violet (UV)-curing of solution-processed metal-oxide (MO) semiconductors for application in thin film transistors (TFTs). The goal is to combine low-temperature thermal annealing with UV exposure and achieve printable transistors on flexible plastic substrates. In this paper we focus on the use of two different wavelengths of UV and clarify their effect on the performance of the metal-oxide semiconductors. The electrical properties of TFTs made with these semiconductors are characterized. The results show that wavelength of the UV exposure is critical for optimized performance of the semiconductor and the TFTs.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127959875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962708
M. Broas, K. Demir, Y. Sato, V. Sundaram, R. Tummala
Interposer technologies for 2.5D and 3D integration schemes require formation of high density and reliable Through-Package-Vias (TPVs) at high throughput and low cost. Glass is proposed to be an ideal candidate material for interposer applications. Among various methods to form TPVs in glass, a variety of laser processing methods have been proposed as feasible methods. The via hole formation mechanisms of different lasers differ from each other which leads to variations in via quality. To study the effects of via quality on reliability, accelerated lifetime tests were conducted on copper-plated TPVs formed with different lasers in glass interposers. Two different lasers for the TPV formation were investigated in this study - a high power CO2 laser and an ArF-based excimer laser. Separate test vehicles containing vias drilled with each of these two methods were fabricated for thermal cycle tests (TCT). The test vehicles contained daisy chains. No failures were detected in the TCT based on a failure criterion of 10 % increase in resistance per daisy chain. TPVs were characterized with optical and electron microscopy after drilling, after fabrication, and after the tests.
{"title":"A comparative reliability study of copper-plated glass vias, drilled with CO2 and ArF excimer lasers","authors":"M. Broas, K. Demir, Y. Sato, V. Sundaram, R. Tummala","doi":"10.1109/ESTC.2014.6962708","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962708","url":null,"abstract":"Interposer technologies for 2.5D and 3D integration schemes require formation of high density and reliable Through-Package-Vias (TPVs) at high throughput and low cost. Glass is proposed to be an ideal candidate material for interposer applications. Among various methods to form TPVs in glass, a variety of laser processing methods have been proposed as feasible methods. The via hole formation mechanisms of different lasers differ from each other which leads to variations in via quality. To study the effects of via quality on reliability, accelerated lifetime tests were conducted on copper-plated TPVs formed with different lasers in glass interposers. Two different lasers for the TPV formation were investigated in this study - a high power CO2 laser and an ArF-based excimer laser. Separate test vehicles containing vias drilled with each of these two methods were fabricated for thermal cycle tests (TCT). The test vehicles contained daisy chains. No failures were detected in the TCT based on a failure criterion of 10 % increase in resistance per daisy chain. TPVs were characterized with optical and electron microscopy after drilling, after fabrication, and after the tests.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128453010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962730
D. Velenis, M. Detalle, S. Van Huylenbroeck, A. Jourdain, A. Phommahaxay, J. Slabbekoorn, Teng Wang, E. Marinissen, K. Rebibis, Andy Miller, G. Beyer, E. Beyne
The cost of 3D process flows is one of the most important aspects for the broader adoption of 3D integration by the semiconductor industry. In this paper the processing cost of the features and components that enable 3D stacking is considered and compared. Different stacking approaches are considered: D2W, W2W and interposer-based stacking. Furthermore, the impact of processing yield and pre-stack testing is evaluated when considering the system integration cost for each one of the 3D stacking methods. In addition the size of the stacked active dies is parameterized and the effect on the system integration cost is explored. Also, the impact of pre-stack testing on interposer in relation to processing yield and the size of the stacked active dies is investigated.
{"title":"Cost components for 3D system integration","authors":"D. Velenis, M. Detalle, S. Van Huylenbroeck, A. Jourdain, A. Phommahaxay, J. Slabbekoorn, Teng Wang, E. Marinissen, K. Rebibis, Andy Miller, G. Beyer, E. Beyne","doi":"10.1109/ESTC.2014.6962730","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962730","url":null,"abstract":"The cost of 3D process flows is one of the most important aspects for the broader adoption of 3D integration by the semiconductor industry. In this paper the processing cost of the features and components that enable 3D stacking is considered and compared. Different stacking approaches are considered: D2W, W2W and interposer-based stacking. Furthermore, the impact of processing yield and pre-stack testing is evaluated when considering the system integration cost for each one of the 3D stacking methods. In addition the size of the stacked active dies is parameterized and the effect on the system integration cost is explored. Also, the impact of pre-stack testing on interposer in relation to processing yield and the size of the stacked active dies is investigated.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130381335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Through silicon via (TSV) is regarded as one of the most advanced packaging technologies, however, many serious reliability issues need to be paid more concerns. The Cu pumping effect is one of the most crucial reliability problems. Due to different coefficient of thermal expansion for different packaging materials, Cu-TSV can deform and damage the wiring redistribution layers and degrade the reliability of the package as a whole during normal processing. Therefore, this work focuses on the influence which different thermal annealing processes have on Cu pumping in Cu-filled TSVs. Cu TSVs having 20μm in diameter and 120μm in depth were fabricated on 200 mm wafers by etching, insulation layer deposition, barrier layer deposition, seed layer deposition and Cu plating in sequence. Then the wafer surface was polished to remove the excessive Cu. Two anneal approaches were designed to investigate Cu TSV pumping. One was CMP first before annealing, and the other was annealing before CMP and followed by the 2nd annealing. Anneal tests were done in a nitrogen environment to protect Cu from oxidation. The annealing temperatures were set at 300°C and 400°C with a dwell time of 40min. The degree of pumping was evaluated by measuring the height and volume profiles before and after annealing by using a white light interferometer. Results show that the Cu TSV increased by 0.105μm and 0.168μm in height and 90.443μm3 and 93.993μm3 in volume at 300°C and 400°C with CMP first approach. However, the Cu TSV increased by only 0.066μm and 0.075μm and 30.797μm3 and 10.077μm3 in volume at 300°C and 400°C with anneal first approach. It can be concluded that the Cu pumping effect may be restrained by anneal first approach.
{"title":"Influence of thermal annealing on the deformation of Cu-filled TSV","authors":"Hongwen He, X. Jing, Liqiang Cao, Daquan Yu, K. Xue, Wenqi Zhang","doi":"10.1109/ESTC.2014.6962763","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962763","url":null,"abstract":"Through silicon via (TSV) is regarded as one of the most advanced packaging technologies, however, many serious reliability issues need to be paid more concerns. The Cu pumping effect is one of the most crucial reliability problems. Due to different coefficient of thermal expansion for different packaging materials, Cu-TSV can deform and damage the wiring redistribution layers and degrade the reliability of the package as a whole during normal processing. Therefore, this work focuses on the influence which different thermal annealing processes have on Cu pumping in Cu-filled TSVs. Cu TSVs having 20μm in diameter and 120μm in depth were fabricated on 200 mm wafers by etching, insulation layer deposition, barrier layer deposition, seed layer deposition and Cu plating in sequence. Then the wafer surface was polished to remove the excessive Cu. Two anneal approaches were designed to investigate Cu TSV pumping. One was CMP first before annealing, and the other was annealing before CMP and followed by the 2nd annealing. Anneal tests were done in a nitrogen environment to protect Cu from oxidation. The annealing temperatures were set at 300°C and 400°C with a dwell time of 40min. The degree of pumping was evaluated by measuring the height and volume profiles before and after annealing by using a white light interferometer. Results show that the Cu TSV increased by 0.105μm and 0.168μm in height and 90.443μm3 and 93.993μm3 in volume at 300°C and 400°C with CMP first approach. However, the Cu TSV increased by only 0.066μm and 0.075μm and 30.797μm3 and 10.077μm3 in volume at 300°C and 400°C with anneal first approach. It can be concluded that the Cu pumping effect may be restrained by anneal first approach.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130288513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962819
M. Saito, K. Matsunaga, J. Mizuno, H. Nishikawa
We investigated a low-temperature bond formation process, wherein nanoporous structures were formed on electrode surfaces by electrodeposition and dealloying. The morphology control of a nanoporous Au-Ag structure was investigated using electrochemical deposition and electrochemical methods. The ligament size of the electrodeposited Au-Ag films after dealloying increased upon annealing. The ligament size of 10-20 nm for as-deposited increased to 50-100 nm for films annealed at 150 °C. The samples that were annealed at 50 °C before dealloying indicated a finer nanoporous structure, which corresponded to the highest bond strength of the evaluated samples. The volume of selective dissolution was small on as-deposited samples despite the anodic current being the largest of the examined films. Inductively coupled plasma mass spectrometry (ICP-MS) analysis showed that the change of the Ag content of the films after dealloying of as-deposited samples was the smallest of the examined films. Small ligament size with a finer nanoporous structure resulted in high bond strength.
{"title":"Nano-porous structure control under electrodeposition and dealloying conditions for low-temperature bonding","authors":"M. Saito, K. Matsunaga, J. Mizuno, H. Nishikawa","doi":"10.1109/ESTC.2014.6962819","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962819","url":null,"abstract":"We investigated a low-temperature bond formation process, wherein nanoporous structures were formed on electrode surfaces by electrodeposition and dealloying. The morphology control of a nanoporous Au-Ag structure was investigated using electrochemical deposition and electrochemical methods. The ligament size of the electrodeposited Au-Ag films after dealloying increased upon annealing. The ligament size of 10-20 nm for as-deposited increased to 50-100 nm for films annealed at 150 °C. The samples that were annealed at 50 °C before dealloying indicated a finer nanoporous structure, which corresponded to the highest bond strength of the evaluated samples. The volume of selective dissolution was small on as-deposited samples despite the anodic current being the largest of the examined films. Inductively coupled plasma mass spectrometry (ICP-MS) analysis showed that the change of the Ag content of the films after dealloying of as-deposited samples was the smallest of the examined films. Small ligament size with a finer nanoporous structure resulted in high bond strength.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122740240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962773
A. Syed-Khaja, J. Franke
This paper gives an overview of the optimization of the present state-of-the-art soldering technologies for diffusion soldering in power electronics, in particular for Transient liquid phase soldering (TLPS) with enhancements in process conditions to reduce the void percentage in the interconnections and at the same time accelerate the rate of intermetallic phase (IMP) formation. Addressing the difficulties in realizing a void-free TLPS joint in large-area die-attach in power electronics, the variations in soldering process parameters like temperature, pressure and time are discussed. The complete transformation of thin Sn-Cu solder interlayers (15-20μm) into Cu6Sn5 and Cu3Sn IMPs and related void information for varying solder profile variants have been explained. To evaluate the potential for TLPS process, the advanced reflow soldering mechanisms like vacuum vapor-phase soldering and over-pressure convection soldering have been investigated. Depending on the void percentages and IMP formation rate, an optimized interconnection process has been introduced which is capable of realizing TLPS joints with convectional electronic production equipment.
{"title":"Investigations on advanced soldering mechanisms for transient liquid phase soldering (TLPS) in power electronics","authors":"A. Syed-Khaja, J. Franke","doi":"10.1109/ESTC.2014.6962773","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962773","url":null,"abstract":"This paper gives an overview of the optimization of the present state-of-the-art soldering technologies for diffusion soldering in power electronics, in particular for Transient liquid phase soldering (TLPS) with enhancements in process conditions to reduce the void percentage in the interconnections and at the same time accelerate the rate of intermetallic phase (IMP) formation. Addressing the difficulties in realizing a void-free TLPS joint in large-area die-attach in power electronics, the variations in soldering process parameters like temperature, pressure and time are discussed. The complete transformation of thin Sn-Cu solder interlayers (15-20μm) into Cu6Sn5 and Cu3Sn IMPs and related void information for varying solder profile variants have been explained. To evaluate the potential for TLPS process, the advanced reflow soldering mechanisms like vacuum vapor-phase soldering and over-pressure convection soldering have been investigated. Depending on the void percentages and IMP formation rate, an optimized interconnection process has been introduced which is capable of realizing TLPS joints with convectional electronic production equipment.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122579154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962765
A. Dziedzic, A. Kłossowicz, P. Winiarski, A. Stadler, W. Stęplewski
This paper presents systematic studies of electrical, noise and long-term stability parameters of resistors (thin-film or polymer thick-film) and capacitors embedded in Printed Circuit Boards (PCBs). The temperature dependence of resistance or capacitance were determined in a wide temperature range (from -180°C to 130°C) and analyzed as a function of geometry of passives and cladding process. The in-situ accelerated ageing process (basic properties of passives measured directly at ageing conditions) was carried out to perform long-term behavior analysis. Low frequency noise measurements were made in room temperature using noise spectra measurements in dc bridge configuration. The R(T) characteristics are linear with almost constant, negative value of differential TCR (of about -60 ppm/K for 100 Ω/sq Ni-P resistors). Both groups of investigated resistors revealed similar range of relative resistance changes after ageing processes but the results showed the quite different behavior of both groups versus time. It means that the dynamics of ageing changes was different. Only positive resistance changes were observed for Ni-P resistors, whereas the shape of characteristics for polymer ones were much more complex, exhibited increase as well as decrease in resistance under environmental exposure. 1/f noise generated by resistance fluctuations was found as the main noise component but the significant difference of noise level was observed for both groups of investigated resistors. The C(T) characteristics are nonlinear with larger capacitance changes at higher temperature. Capacitors exposed to elevated temperature exhibited capacitance and dissipation factor decrease. The relative changes were from the range from -12% to -2% for capacitance and up to -60% for dissipation factor. The value of relative drift of parameters was dependent strongly on dielectric composition and size. Moreover the results revealed nonlinear characteristics in temperature domain as well.
{"title":"Chosen electrical, noise and stability characteristics of passive components embedded in printed circuit boards","authors":"A. Dziedzic, A. Kłossowicz, P. Winiarski, A. Stadler, W. Stęplewski","doi":"10.1109/ESTC.2014.6962765","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962765","url":null,"abstract":"This paper presents systematic studies of electrical, noise and long-term stability parameters of resistors (thin-film or polymer thick-film) and capacitors embedded in Printed Circuit Boards (PCBs). The temperature dependence of resistance or capacitance were determined in a wide temperature range (from -180°C to 130°C) and analyzed as a function of geometry of passives and cladding process. The in-situ accelerated ageing process (basic properties of passives measured directly at ageing conditions) was carried out to perform long-term behavior analysis. Low frequency noise measurements were made in room temperature using noise spectra measurements in dc bridge configuration. The R(T) characteristics are linear with almost constant, negative value of differential TCR (of about -60 ppm/K for 100 Ω/sq Ni-P resistors). Both groups of investigated resistors revealed similar range of relative resistance changes after ageing processes but the results showed the quite different behavior of both groups versus time. It means that the dynamics of ageing changes was different. Only positive resistance changes were observed for Ni-P resistors, whereas the shape of characteristics for polymer ones were much more complex, exhibited increase as well as decrease in resistance under environmental exposure. 1/f noise generated by resistance fluctuations was found as the main noise component but the significant difference of noise level was observed for both groups of investigated resistors. The C(T) characteristics are nonlinear with larger capacitance changes at higher temperature. Capacitors exposed to elevated temperature exhibited capacitance and dissipation factor decrease. The relative changes were from the range from -12% to -2% for capacitance and up to -60% for dissipation factor. The value of relative drift of parameters was dependent strongly on dielectric composition and size. Moreover the results revealed nonlinear characteristics in temperature domain as well.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122870535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962823
J. Řeboun, T. Blecha, T. Syrový, A. Hamácek, Alexey Shlykevich
This paper deals with the research and development of printed flexible capacitors and inductors predominantly designed for the construction of RFID labels. These printed RF passive components are required for the construction of fully printed low cost passive RFID labels. The passive components are directly printed on PET substrate by the screen printing technique. The printing process was optimized in order to achieve a high yield and good electrical parameters at the frequency of 13,56 MHz. Electrical parameters of printed capacitors, such as impedance to frequency characteristic, capacity to temperature characteristic, capacity to bias voltage characteristic were measured in detail. The bending tests were also performed for verifying of printed capacitors flexibility. The performance of capacitors was verified in the real sample of resonant circuit at 13,56 MHz.
{"title":"Printed passive components for RFID labels","authors":"J. Řeboun, T. Blecha, T. Syrový, A. Hamácek, Alexey Shlykevich","doi":"10.1109/ESTC.2014.6962823","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962823","url":null,"abstract":"This paper deals with the research and development of printed flexible capacitors and inductors predominantly designed for the construction of RFID labels. These printed RF passive components are required for the construction of fully printed low cost passive RFID labels. The passive components are directly printed on PET substrate by the screen printing technique. The printing process was optimized in order to achieve a high yield and good electrical parameters at the frequency of 13,56 MHz. Electrical parameters of printed capacitors, such as impedance to frequency characteristic, capacity to temperature characteristic, capacity to bias voltage characteristic were measured in detail. The bending tests were also performed for verifying of printed capacitors flexibility. The performance of capacitors was verified in the real sample of resonant circuit at 13,56 MHz.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116882965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962744
D. Manessis, S. Karaszkiewicz, J. Kierdorf, A. Ostmann, R. Aschenbrenner, K. Lang
This paper brings into light the first prototype miniaturized system-in-package (SiP) microsystems built for wireless body-area-network medical devices which mandate low power consumption and extreme packaging miniaturization. Specifically, this paper focuses on the fabrication of a remote controller for wireless medical devices in the practical shape of an extended “microSD” card where the extended part will co-integrate a passive antenna. Actually the microSd card is a RF transceiver enclosing an advanced SoC, MEMS filters, flash memory and other passive components. The presented paper describes in detail all manufacturing steps for the realization of the extended “microSD” card and all technology developments achieved to reach this goal. Firstly, a 2-layer substrate has been successfully produced with 35μm ultra fine line copper structuring in conjunction with 75μm through-vias using subtractive technology. Subsequently, assembly technologies for heterogeneous BAN components were further developed in order to achieve the placement of the tiny IF SAW filters and BAW resonators on the substrate and to implement mixed assembly of soldered passives with fluxed chip packages. Finally, the paper highlights the embedding technology employed in the project for the manufacturing of the microSD cards on 18”x24” large panels. The extended microSD card will be used for testing, programming and controlling all vital SoC functions in the wireless medical devices. It has a size of 11mm×22mm×1.05mm with the antenna part occupying a space of 11mm×7mm×1.05mm.
{"title":"A “microSD”sized RF transceiver manufactured as an embedded system-in-package","authors":"D. Manessis, S. Karaszkiewicz, J. Kierdorf, A. Ostmann, R. Aschenbrenner, K. Lang","doi":"10.1109/ESTC.2014.6962744","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962744","url":null,"abstract":"This paper brings into light the first prototype miniaturized system-in-package (SiP) microsystems built for wireless body-area-network medical devices which mandate low power consumption and extreme packaging miniaturization. Specifically, this paper focuses on the fabrication of a remote controller for wireless medical devices in the practical shape of an extended “microSD” card where the extended part will co-integrate a passive antenna. Actually the microSd card is a RF transceiver enclosing an advanced SoC, MEMS filters, flash memory and other passive components. The presented paper describes in detail all manufacturing steps for the realization of the extended “microSD” card and all technology developments achieved to reach this goal. Firstly, a 2-layer substrate has been successfully produced with 35μm ultra fine line copper structuring in conjunction with 75μm through-vias using subtractive technology. Subsequently, assembly technologies for heterogeneous BAN components were further developed in order to achieve the placement of the tiny IF SAW filters and BAW resonators on the substrate and to implement mixed assembly of soldered passives with fluxed chip packages. Finally, the paper highlights the embedding technology employed in the project for the manufacturing of the microSD cards on 18”x24” large panels. The extended microSD card will be used for testing, programming and controlling all vital SoC functions in the wireless medical devices. It has a size of 11mm×22mm×1.05mm with the antenna part occupying a space of 11mm×7mm×1.05mm.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115334095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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