Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962809
Markus Jarn, Chueh-An Hsieh, Yu-Chi Pai, Tsaiying Wang, J. Hunt
Wafer level packaging (WLP) of electronic components has become increasingly popular in recent years. The WLP package has the same foot print as the die and is therefore the smallest package possible. This is important for applications where maximum functionality is required in a small space, especially for mobile devices. The largest package sizes and pin counts used for WLP components have steadily increased in recent years. As the mechanical stresses in WLP packages increase with die size as well, board level reliability becomes a major concern. As such, the questions arise: what is the maximum die size possible for a WLP to meet board level reliability requirements and, for a given package size, how can the board level reliability be improved? To start to answer these questions, we have designed a large die test vehicle based on a dummy wafer (8×8 mm in size with 444 connections at 0.4mm pitch) with features in the package that are common to devices in production today, such as redistribution traces, polymer passivation layers, under bump metallization, and solder balls for interconnection to the test board. Using wafer level processes, we have assembled the test vehicles under different conditions in a design of experiment. We varied the parameters of polymer passivation thickness, redistribution trace thickness, and final die thickness and then characterized the board level reliability under temperature cycling and drop test conditions for a statistically significant sample size.
{"title":"Reliability investigations of large die wafer level packages: Optimization of package structure and materials to improve board level reliability","authors":"Markus Jarn, Chueh-An Hsieh, Yu-Chi Pai, Tsaiying Wang, J. Hunt","doi":"10.1109/ESTC.2014.6962809","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962809","url":null,"abstract":"Wafer level packaging (WLP) of electronic components has become increasingly popular in recent years. The WLP package has the same foot print as the die and is therefore the smallest package possible. This is important for applications where maximum functionality is required in a small space, especially for mobile devices. The largest package sizes and pin counts used for WLP components have steadily increased in recent years. As the mechanical stresses in WLP packages increase with die size as well, board level reliability becomes a major concern. As such, the questions arise: what is the maximum die size possible for a WLP to meet board level reliability requirements and, for a given package size, how can the board level reliability be improved? To start to answer these questions, we have designed a large die test vehicle based on a dummy wafer (8×8 mm in size with 444 connections at 0.4mm pitch) with features in the package that are common to devices in production today, such as redistribution traces, polymer passivation layers, under bump metallization, and solder balls for interconnection to the test board. Using wafer level processes, we have assembled the test vehicles under different conditions in a design of experiment. We varied the parameters of polymer passivation thickness, redistribution trace thickness, and final die thickness and then characterized the board level reliability under temperature cycling and drop test conditions for a statistically significant sample size.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122384159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962780
V. Giagka, A. Vanhoestenberghe, N. Donaldson, A. Demosthenous
We are developing an active implant for epidural spinal cord stimulation. A thin application specific integrated circuit (ASIC) (~80 μm) is to be embedded within it. The laser patterned tracks are electrically and mechanically thermosonically bonded on the ASIC pads using gold ball studs, forming micro-rivets through holes in the foil of the tracks, an interconnection method called electrical rivet bonding, or microflex [1]. In this work, we sought to characterize and optimize the technique, with respect to its bonding strength. The technique is relatively new and, so far, the mechanical strength of the bonds has only been investigated for interconnection on gold tracks. Standard ASICs however, normally come with aluminium pads. We ran a series of pull tests on the bonds between the metal tracks and aluminium ASIC pads. In these tests, we were concerned with the effect of the different parameters on the bond strength, and more specifically the size of the gold balls and the size of the holes in the foil. We recorded the maximum force (stress) before bond failure for different combinations of parameters. Our results indicate that average stress values can vary between 9.6 and 60 cN, depending on the process parameters. Different failure mechanisms have been identified and these are discussed. Overall, we conclude that larger holes provide larger contact areas with the substrate and generally result in stronger bonds, but the right combination of ball and hole sizes, could lead to strong bonds even with smaller holes.
{"title":"Evaluation and optimization of the mechanical strength of bonds between metal foil and aluminium pads on thin ASICs using gold ball studs as micro-rivets","authors":"V. Giagka, A. Vanhoestenberghe, N. Donaldson, A. Demosthenous","doi":"10.1109/ESTC.2014.6962780","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962780","url":null,"abstract":"We are developing an active implant for epidural spinal cord stimulation. A thin application specific integrated circuit (ASIC) (~80 μm) is to be embedded within it. The laser patterned tracks are electrically and mechanically thermosonically bonded on the ASIC pads using gold ball studs, forming micro-rivets through holes in the foil of the tracks, an interconnection method called electrical rivet bonding, or microflex [1]. In this work, we sought to characterize and optimize the technique, with respect to its bonding strength. The technique is relatively new and, so far, the mechanical strength of the bonds has only been investigated for interconnection on gold tracks. Standard ASICs however, normally come with aluminium pads. We ran a series of pull tests on the bonds between the metal tracks and aluminium ASIC pads. In these tests, we were concerned with the effect of the different parameters on the bond strength, and more specifically the size of the gold balls and the size of the holes in the foil. We recorded the maximum force (stress) before bond failure for different combinations of parameters. Our results indicate that average stress values can vary between 9.6 and 60 cN, depending on the process parameters. Different failure mechanisms have been identified and these are discussed. Overall, we conclude that larger holes provide larger contact areas with the substrate and generally result in stronger bonds, but the right combination of ball and hole sizes, could lead to strong bonds even with smaller holes.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116355138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962762
H. Majumdar, J. Leppaniemi, K. Ojanpera, Olli‐Heikki Huttunen, A. Alastalo
This paper focuses on ultra-violet (UV)-curing of solution-processed metal-oxide (MO) semiconductors for application in thin film transistors (TFTs). The goal is to combine low-temperature thermal annealing with UV exposure and achieve printable transistors on flexible plastic substrates. In this paper we focus on the use of two different wavelengths of UV and clarify their effect on the performance of the metal-oxide semiconductors. The electrical properties of TFTs made with these semiconductors are characterized. The results show that wavelength of the UV exposure is critical for optimized performance of the semiconductor and the TFTs.
{"title":"Effect of UV light and low temperature on solution-processed, high-performance metal-oxide semiconductors and TFTs","authors":"H. Majumdar, J. Leppaniemi, K. Ojanpera, Olli‐Heikki Huttunen, A. Alastalo","doi":"10.1109/ESTC.2014.6962762","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962762","url":null,"abstract":"This paper focuses on ultra-violet (UV)-curing of solution-processed metal-oxide (MO) semiconductors for application in thin film transistors (TFTs). The goal is to combine low-temperature thermal annealing with UV exposure and achieve printable transistors on flexible plastic substrates. In this paper we focus on the use of two different wavelengths of UV and clarify their effect on the performance of the metal-oxide semiconductors. The electrical properties of TFTs made with these semiconductors are characterized. The results show that wavelength of the UV exposure is critical for optimized performance of the semiconductor and the TFTs.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127959875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962730
D. Velenis, M. Detalle, S. Van Huylenbroeck, A. Jourdain, A. Phommahaxay, J. Slabbekoorn, Teng Wang, E. Marinissen, K. Rebibis, Andy Miller, G. Beyer, E. Beyne
The cost of 3D process flows is one of the most important aspects for the broader adoption of 3D integration by the semiconductor industry. In this paper the processing cost of the features and components that enable 3D stacking is considered and compared. Different stacking approaches are considered: D2W, W2W and interposer-based stacking. Furthermore, the impact of processing yield and pre-stack testing is evaluated when considering the system integration cost for each one of the 3D stacking methods. In addition the size of the stacked active dies is parameterized and the effect on the system integration cost is explored. Also, the impact of pre-stack testing on interposer in relation to processing yield and the size of the stacked active dies is investigated.
{"title":"Cost components for 3D system integration","authors":"D. Velenis, M. Detalle, S. Van Huylenbroeck, A. Jourdain, A. Phommahaxay, J. Slabbekoorn, Teng Wang, E. Marinissen, K. Rebibis, Andy Miller, G. Beyer, E. Beyne","doi":"10.1109/ESTC.2014.6962730","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962730","url":null,"abstract":"The cost of 3D process flows is one of the most important aspects for the broader adoption of 3D integration by the semiconductor industry. In this paper the processing cost of the features and components that enable 3D stacking is considered and compared. Different stacking approaches are considered: D2W, W2W and interposer-based stacking. Furthermore, the impact of processing yield and pre-stack testing is evaluated when considering the system integration cost for each one of the 3D stacking methods. In addition the size of the stacked active dies is parameterized and the effect on the system integration cost is explored. Also, the impact of pre-stack testing on interposer in relation to processing yield and the size of the stacked active dies is investigated.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130381335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962760
Younsu Jung, Hyejin Park, Jin-Ah Park, J. Noh, Yunchang Choi, M. Jung, Kyunghwan Jung, Myungho Pyo, Kevin Chen, A. Javey, Gyoujin Cho
For the first time, fully gravure printed wireless cyclic voltammetry (CV) tag is reported as a platform for the disposable wireless sensor tags by utilizing Ag nano-particle based conducting ink, BaTiO3 nano-particle based dielectric ink and single-walled carbon nanotube based semiconducting ink. The printed CV tag contains four functional units for the disposable wireless sensor tag: the rectenna to generate polarized DC volt through coupled 13.56 MHz AC, triangle wave generator to scan electrochemical cell by ±500 mV at lower frequency (<; 500 mHz), amplifier to enhance the output signal and signage to indicate detected level of specimens. Those printed four units will be used as a platform to further develop disposable wireless sensor tags by simply replacing sensor unit.
{"title":"Fully gravure printed wireless cyclic voltammetry tags","authors":"Younsu Jung, Hyejin Park, Jin-Ah Park, J. Noh, Yunchang Choi, M. Jung, Kyunghwan Jung, Myungho Pyo, Kevin Chen, A. Javey, Gyoujin Cho","doi":"10.1109/ESTC.2014.6962760","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962760","url":null,"abstract":"For the first time, fully gravure printed wireless cyclic voltammetry (CV) tag is reported as a platform for the disposable wireless sensor tags by utilizing Ag nano-particle based conducting ink, BaTiO3 nano-particle based dielectric ink and single-walled carbon nanotube based semiconducting ink. The printed CV tag contains four functional units for the disposable wireless sensor tag: the rectenna to generate polarized DC volt through coupled 13.56 MHz AC, triangle wave generator to scan electrochemical cell by ±500 mV at lower frequency (<; 500 mHz), amplifier to enhance the output signal and signage to indicate detected level of specimens. Those printed four units will be used as a platform to further develop disposable wireless sensor tags by simply replacing sensor unit.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116691218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962815
T. Tilford, A. Cook, H. Lu, A. Ramambasoa, F. Conseil
An inverse analysis approach combining numerical and experimental analyses has been utilised to determine the in-situ effective material properties of Highly Oriented Pyrolytic Graphite (HOPG) in a microelectronics test assembly. The approach adopted uses a Finite Element analysis package to determine temperature distribution over a thermal test assembly. A Virtual Design of Experiments approach is used to define a series of analyses with discrete thermal material properties which is used in conjunction with a particle swarm optimisation algorithm to form a response surface function relating temperature to material property values at a number of monitoring points. Experimental data is used to form an error metric which is subsequently minimised to determine effective material properties of the HOPG material. Subsequently a series of studies contrasting the performance of the HOPG material with common heat spreader materials were performed. Results show that the effective thermal property values of the HOPG material seem to be greater than suggested in existing literature and that the HOPG material reduces peak assembly temperatures by a significant amount.
{"title":"Numerical analysis of the performance of highly oriented pyrolytic graphite heat spreader in thermal management of microelectronics assemblies","authors":"T. Tilford, A. Cook, H. Lu, A. Ramambasoa, F. Conseil","doi":"10.1109/ESTC.2014.6962815","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962815","url":null,"abstract":"An inverse analysis approach combining numerical and experimental analyses has been utilised to determine the in-situ effective material properties of Highly Oriented Pyrolytic Graphite (HOPG) in a microelectronics test assembly. The approach adopted uses a Finite Element analysis package to determine temperature distribution over a thermal test assembly. A Virtual Design of Experiments approach is used to define a series of analyses with discrete thermal material properties which is used in conjunction with a particle swarm optimisation algorithm to form a response surface function relating temperature to material property values at a number of monitoring points. Experimental data is used to form an error metric which is subsequently minimised to determine effective material properties of the HOPG material. Subsequently a series of studies contrasting the performance of the HOPG material with common heat spreader materials were performed. Results show that the effective thermal property values of the HOPG material seem to be greater than suggested in existing literature and that the HOPG material reduces peak assembly temperatures by a significant amount.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132731494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962708
M. Broas, K. Demir, Y. Sato, V. Sundaram, R. Tummala
Interposer technologies for 2.5D and 3D integration schemes require formation of high density and reliable Through-Package-Vias (TPVs) at high throughput and low cost. Glass is proposed to be an ideal candidate material for interposer applications. Among various methods to form TPVs in glass, a variety of laser processing methods have been proposed as feasible methods. The via hole formation mechanisms of different lasers differ from each other which leads to variations in via quality. To study the effects of via quality on reliability, accelerated lifetime tests were conducted on copper-plated TPVs formed with different lasers in glass interposers. Two different lasers for the TPV formation were investigated in this study - a high power CO2 laser and an ArF-based excimer laser. Separate test vehicles containing vias drilled with each of these two methods were fabricated for thermal cycle tests (TCT). The test vehicles contained daisy chains. No failures were detected in the TCT based on a failure criterion of 10 % increase in resistance per daisy chain. TPVs were characterized with optical and electron microscopy after drilling, after fabrication, and after the tests.
{"title":"A comparative reliability study of copper-plated glass vias, drilled with CO2 and ArF excimer lasers","authors":"M. Broas, K. Demir, Y. Sato, V. Sundaram, R. Tummala","doi":"10.1109/ESTC.2014.6962708","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962708","url":null,"abstract":"Interposer technologies for 2.5D and 3D integration schemes require formation of high density and reliable Through-Package-Vias (TPVs) at high throughput and low cost. Glass is proposed to be an ideal candidate material for interposer applications. Among various methods to form TPVs in glass, a variety of laser processing methods have been proposed as feasible methods. The via hole formation mechanisms of different lasers differ from each other which leads to variations in via quality. To study the effects of via quality on reliability, accelerated lifetime tests were conducted on copper-plated TPVs formed with different lasers in glass interposers. Two different lasers for the TPV formation were investigated in this study - a high power CO2 laser and an ArF-based excimer laser. Separate test vehicles containing vias drilled with each of these two methods were fabricated for thermal cycle tests (TCT). The test vehicles contained daisy chains. No failures were detected in the TCT based on a failure criterion of 10 % increase in resistance per daisy chain. TPVs were characterized with optical and electron microscopy after drilling, after fabrication, and after the tests.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128453010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Through silicon via (TSV) is regarded as one of the most advanced packaging technologies, however, many serious reliability issues need to be paid more concerns. The Cu pumping effect is one of the most crucial reliability problems. Due to different coefficient of thermal expansion for different packaging materials, Cu-TSV can deform and damage the wiring redistribution layers and degrade the reliability of the package as a whole during normal processing. Therefore, this work focuses on the influence which different thermal annealing processes have on Cu pumping in Cu-filled TSVs. Cu TSVs having 20μm in diameter and 120μm in depth were fabricated on 200 mm wafers by etching, insulation layer deposition, barrier layer deposition, seed layer deposition and Cu plating in sequence. Then the wafer surface was polished to remove the excessive Cu. Two anneal approaches were designed to investigate Cu TSV pumping. One was CMP first before annealing, and the other was annealing before CMP and followed by the 2nd annealing. Anneal tests were done in a nitrogen environment to protect Cu from oxidation. The annealing temperatures were set at 300°C and 400°C with a dwell time of 40min. The degree of pumping was evaluated by measuring the height and volume profiles before and after annealing by using a white light interferometer. Results show that the Cu TSV increased by 0.105μm and 0.168μm in height and 90.443μm3 and 93.993μm3 in volume at 300°C and 400°C with CMP first approach. However, the Cu TSV increased by only 0.066μm and 0.075μm and 30.797μm3 and 10.077μm3 in volume at 300°C and 400°C with anneal first approach. It can be concluded that the Cu pumping effect may be restrained by anneal first approach.
{"title":"Influence of thermal annealing on the deformation of Cu-filled TSV","authors":"Hongwen He, X. Jing, Liqiang Cao, Daquan Yu, K. Xue, Wenqi Zhang","doi":"10.1109/ESTC.2014.6962763","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962763","url":null,"abstract":"Through silicon via (TSV) is regarded as one of the most advanced packaging technologies, however, many serious reliability issues need to be paid more concerns. The Cu pumping effect is one of the most crucial reliability problems. Due to different coefficient of thermal expansion for different packaging materials, Cu-TSV can deform and damage the wiring redistribution layers and degrade the reliability of the package as a whole during normal processing. Therefore, this work focuses on the influence which different thermal annealing processes have on Cu pumping in Cu-filled TSVs. Cu TSVs having 20μm in diameter and 120μm in depth were fabricated on 200 mm wafers by etching, insulation layer deposition, barrier layer deposition, seed layer deposition and Cu plating in sequence. Then the wafer surface was polished to remove the excessive Cu. Two anneal approaches were designed to investigate Cu TSV pumping. One was CMP first before annealing, and the other was annealing before CMP and followed by the 2nd annealing. Anneal tests were done in a nitrogen environment to protect Cu from oxidation. The annealing temperatures were set at 300°C and 400°C with a dwell time of 40min. The degree of pumping was evaluated by measuring the height and volume profiles before and after annealing by using a white light interferometer. Results show that the Cu TSV increased by 0.105μm and 0.168μm in height and 90.443μm3 and 93.993μm3 in volume at 300°C and 400°C with CMP first approach. However, the Cu TSV increased by only 0.066μm and 0.075μm and 30.797μm3 and 10.077μm3 in volume at 300°C and 400°C with anneal first approach. It can be concluded that the Cu pumping effect may be restrained by anneal first approach.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130288513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962823
J. Řeboun, T. Blecha, T. Syrový, A. Hamácek, Alexey Shlykevich
This paper deals with the research and development of printed flexible capacitors and inductors predominantly designed for the construction of RFID labels. These printed RF passive components are required for the construction of fully printed low cost passive RFID labels. The passive components are directly printed on PET substrate by the screen printing technique. The printing process was optimized in order to achieve a high yield and good electrical parameters at the frequency of 13,56 MHz. Electrical parameters of printed capacitors, such as impedance to frequency characteristic, capacity to temperature characteristic, capacity to bias voltage characteristic were measured in detail. The bending tests were also performed for verifying of printed capacitors flexibility. The performance of capacitors was verified in the real sample of resonant circuit at 13,56 MHz.
{"title":"Printed passive components for RFID labels","authors":"J. Řeboun, T. Blecha, T. Syrový, A. Hamácek, Alexey Shlykevich","doi":"10.1109/ESTC.2014.6962823","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962823","url":null,"abstract":"This paper deals with the research and development of printed flexible capacitors and inductors predominantly designed for the construction of RFID labels. These printed RF passive components are required for the construction of fully printed low cost passive RFID labels. The passive components are directly printed on PET substrate by the screen printing technique. The printing process was optimized in order to achieve a high yield and good electrical parameters at the frequency of 13,56 MHz. Electrical parameters of printed capacitors, such as impedance to frequency characteristic, capacity to temperature characteristic, capacity to bias voltage characteristic were measured in detail. The bending tests were also performed for verifying of printed capacitors flexibility. The performance of capacitors was verified in the real sample of resonant circuit at 13,56 MHz.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116882965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962744
D. Manessis, S. Karaszkiewicz, J. Kierdorf, A. Ostmann, R. Aschenbrenner, K. Lang
This paper brings into light the first prototype miniaturized system-in-package (SiP) microsystems built for wireless body-area-network medical devices which mandate low power consumption and extreme packaging miniaturization. Specifically, this paper focuses on the fabrication of a remote controller for wireless medical devices in the practical shape of an extended “microSD” card where the extended part will co-integrate a passive antenna. Actually the microSd card is a RF transceiver enclosing an advanced SoC, MEMS filters, flash memory and other passive components. The presented paper describes in detail all manufacturing steps for the realization of the extended “microSD” card and all technology developments achieved to reach this goal. Firstly, a 2-layer substrate has been successfully produced with 35μm ultra fine line copper structuring in conjunction with 75μm through-vias using subtractive technology. Subsequently, assembly technologies for heterogeneous BAN components were further developed in order to achieve the placement of the tiny IF SAW filters and BAW resonators on the substrate and to implement mixed assembly of soldered passives with fluxed chip packages. Finally, the paper highlights the embedding technology employed in the project for the manufacturing of the microSD cards on 18”x24” large panels. The extended microSD card will be used for testing, programming and controlling all vital SoC functions in the wireless medical devices. It has a size of 11mm×22mm×1.05mm with the antenna part occupying a space of 11mm×7mm×1.05mm.
{"title":"A “microSD”sized RF transceiver manufactured as an embedded system-in-package","authors":"D. Manessis, S. Karaszkiewicz, J. Kierdorf, A. Ostmann, R. Aschenbrenner, K. Lang","doi":"10.1109/ESTC.2014.6962744","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962744","url":null,"abstract":"This paper brings into light the first prototype miniaturized system-in-package (SiP) microsystems built for wireless body-area-network medical devices which mandate low power consumption and extreme packaging miniaturization. Specifically, this paper focuses on the fabrication of a remote controller for wireless medical devices in the practical shape of an extended “microSD” card where the extended part will co-integrate a passive antenna. Actually the microSd card is a RF transceiver enclosing an advanced SoC, MEMS filters, flash memory and other passive components. The presented paper describes in detail all manufacturing steps for the realization of the extended “microSD” card and all technology developments achieved to reach this goal. Firstly, a 2-layer substrate has been successfully produced with 35μm ultra fine line copper structuring in conjunction with 75μm through-vias using subtractive technology. Subsequently, assembly technologies for heterogeneous BAN components were further developed in order to achieve the placement of the tiny IF SAW filters and BAW resonators on the substrate and to implement mixed assembly of soldered passives with fluxed chip packages. Finally, the paper highlights the embedding technology employed in the project for the manufacturing of the microSD cards on 18”x24” large panels. The extended microSD card will be used for testing, programming and controlling all vital SoC functions in the wireless medical devices. It has a size of 11mm×22mm×1.05mm with the antenna part occupying a space of 11mm×7mm×1.05mm.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115334095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：