Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962732
H. Schroder, L. Brusberg, G. Bottger
There is a clear tendency to integrate more and more opto-electronic and micro-optical components like optical fibers, laser diodes, modulators, isolators, beam-splitting components and micro lenses in also increasingly dense and complex assemblies. The paper will discuss thin glass as a very promising base material for that kind of photonic packaging on interposer and board level including optical interconnection using fibers.
{"title":"Strategies for glass based photonic system integration","authors":"H. Schroder, L. Brusberg, G. Bottger","doi":"10.1109/ESTC.2014.6962732","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962732","url":null,"abstract":"There is a clear tendency to integrate more and more opto-electronic and micro-optical components like optical fibers, laser diodes, modulators, isolators, beam-splitting components and micro lenses in also increasingly dense and complex assemblies. The paper will discuss thin glass as a very promising base material for that kind of photonic packaging on interposer and board level including optical interconnection using fibers.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133900922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962813
Grace L. Tsebo Simo, H. Shirangi, M. Nowottnick, Georg Konstantin
In this work, the influence of the copper pad geometry on the reliability of printed circuit board/ball grid array (PCB/BGA) assemblies under drop impact is assessed. The method employed is based on drop experiments combined with finite element simulations. For the experimental part, various test PCBs with three different pad designs were manufactured and tested under drop impact loading conditions. The lifetime of each BGA component was obtained by using suitable daisy chain circuits. For the numerical part, simulation models were implemented in Ansys v14.5 and the stresses at the critical locations of the PCB were evaluated with the help of the submodeling technique. From the experimental and simulation results, a clear dependency of the reliability of the tested samples on the copper pad geometry can be deduced. Moreover, using a lifetime model developed in a previous work [1] describing the relationship between the applied stress on the board and the number of drop to failure, predictions regarding the lifetime of the tested samples can be made. A very good correlation between the predicted and measured results can be shown. With the findings of this research work, it is therefore possible to define guidelines for the design of electronic packages with fine pitch area array interconnections.
{"title":"Influence of the pad design on the reliability of PCB/BGA assemblies under drop excitation","authors":"Grace L. Tsebo Simo, H. Shirangi, M. Nowottnick, Georg Konstantin","doi":"10.1109/ESTC.2014.6962813","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962813","url":null,"abstract":"In this work, the influence of the copper pad geometry on the reliability of printed circuit board/ball grid array (PCB/BGA) assemblies under drop impact is assessed. The method employed is based on drop experiments combined with finite element simulations. For the experimental part, various test PCBs with three different pad designs were manufactured and tested under drop impact loading conditions. The lifetime of each BGA component was obtained by using suitable daisy chain circuits. For the numerical part, simulation models were implemented in Ansys v14.5 and the stresses at the critical locations of the PCB were evaluated with the help of the submodeling technique. From the experimental and simulation results, a clear dependency of the reliability of the tested samples on the copper pad geometry can be deduced. Moreover, using a lifetime model developed in a previous work [1] describing the relationship between the applied stress on the board and the number of drop to failure, predictions regarding the lifetime of the tested samples can be made. A very good correlation between the predicted and measured results can be shown. With the findings of this research work, it is therefore possible to define guidelines for the design of electronic packages with fine pitch area array interconnections.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133196136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962793
S. Klengel, S. Brand, Christian Grose, F. Altmann, M. Petzold
Currently smart cards with integrated silicon dies have found wide application for personal authorization, security identification and payment systems. As a consequence, the complexity of electronics is increasing, thus, specifically adapted failure analysis methods and work flows are required taking the peculiarities of smart card constructions with embedded chips as well as the used polymer materials into account. The aim of the paper is to present results of developing novel methods for non-destructive defect detection as well as for selective, artifact-poor target preparation routines specifically adapted for smart card systems. These methods allow fault localization and exposing defect areas for subsequent high resolution failure analysis within reliability investigations. As for non-destructive diagnostics, specific focus was given to the evaluation and application development of Lock-in thermography (LIT) as a method to detect thermally active failures such as increased contact resistivity, shorts or leakage currents. It could be shown that Lock-in thermography can be successfully applied for fault isolation of defects within the card and on the semiconductor surface. The LIT investigations were complemented by Scanning Acoustic Microscopy (SAM) in order to find delamination and chip cracks. New signal processing methods of ultrasonic microscopy resulted in a reliable detection of these mechanical damages. Scanning Acoustic Microscopy in the GHz frequency (GHz-SAM) domain was applied for investigations on chip level. Contact-induced mechanical damage just below the only few micrometer thick optically non-transparent passivation of the IC could be detected with high lateral resolution. However, for a detailed root cause analysis of the failures localized either by Lock-in thermography or Scanning Acoustic Microscopy, further adequate preparation routines are necessary to get direct access to the failure site. Within the study, a selective exposure of the semiconductor chips from the composite laminate was achieved by laser ablation after optimizing laser frequencies and pulse widths as well as by adapted wet chemical procedures. Efficient cross section preparation was enabled by ion beam finish. A case study on how the methods can be applied for failure analysis of smart cards will be demonstrated.
{"title":"Novel failure diagnostic methods for smart card systems","authors":"S. Klengel, S. Brand, Christian Grose, F. Altmann, M. Petzold","doi":"10.1109/ESTC.2014.6962793","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962793","url":null,"abstract":"Currently smart cards with integrated silicon dies have found wide application for personal authorization, security identification and payment systems. As a consequence, the complexity of electronics is increasing, thus, specifically adapted failure analysis methods and work flows are required taking the peculiarities of smart card constructions with embedded chips as well as the used polymer materials into account. The aim of the paper is to present results of developing novel methods for non-destructive defect detection as well as for selective, artifact-poor target preparation routines specifically adapted for smart card systems. These methods allow fault localization and exposing defect areas for subsequent high resolution failure analysis within reliability investigations. As for non-destructive diagnostics, specific focus was given to the evaluation and application development of Lock-in thermography (LIT) as a method to detect thermally active failures such as increased contact resistivity, shorts or leakage currents. It could be shown that Lock-in thermography can be successfully applied for fault isolation of defects within the card and on the semiconductor surface. The LIT investigations were complemented by Scanning Acoustic Microscopy (SAM) in order to find delamination and chip cracks. New signal processing methods of ultrasonic microscopy resulted in a reliable detection of these mechanical damages. Scanning Acoustic Microscopy in the GHz frequency (GHz-SAM) domain was applied for investigations on chip level. Contact-induced mechanical damage just below the only few micrometer thick optically non-transparent passivation of the IC could be detected with high lateral resolution. However, for a detailed root cause analysis of the failures localized either by Lock-in thermography or Scanning Acoustic Microscopy, further adequate preparation routines are necessary to get direct access to the failure site. Within the study, a selective exposure of the semiconductor chips from the composite laminate was achieved by laser ablation after optimizing laser frequencies and pulse widths as well as by adapted wet chemical procedures. Efficient cross section preparation was enabled by ion beam finish. A case study on how the methods can be applied for failure analysis of smart cards will be demonstrated.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134368626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The industry saw the transition of flip chip technology from lead free solder system to Cu pillar bump a few years ago. The risk of fail location under electromigration (EM) shifts from the solder/UBM interface of the standard solder bump to the solder joint of the Cu pillar solder joint. This study investigated the performance of the Cu pillar solder interconnect under current stress testing and temperature acceleration. The EM stress test of Cu pillar bumps interconnect was designed and implemented comparing the bump solder tips joined with OSP (organic solderability preservative)-Cu (the OSP-Cu bump) substrate and ENEPIG (electroless Ni(P)/electroless Pd/immersion Au)-Cu (the ENEPIG-Cu bump) substrate. The bumps with different solder volumes, 20 μm and 50 μm in height, were investigated for EM performance comparison. The EM testing was conducted at current density 7 kA/cm2 under various temperatures of 125 °C, 135 °C and 150 °C. The EM duration time of Cu pillar bump joints were estimated for testing up to 10000 hours. The joint with smaller solder volume tends to exhibit better EM life. The experimental results showed that the Cu pillar bumps on OSP-Cu performed superior to that on ENEPIG-Cu. The cross sectional microstructure analysis indicates that the intermetallic compound (IMC) formed are mainly Cu6Sn5 and Cu3Sn for the Cu pillar bump joint on OSP-Cu substrate, while (Au, Pd)Sn4 was also detected for the ENEPIG-Cu substrate. The failure analysis of the failed joints indicated that the failure behavior closely related to the volume of IMC formed and the IMC structure within the Cu pillar joint.
{"title":"The physics of Cu pillar bump interconnect under electromigration stress testing","authors":"Yu-Hsiang Hsiao, Chien-Fan Chen, Ping-Feng Yang, Chang-Chi Lee, Min-Chi Liu, Kwang-Lung Lin, Chiao-Wen Chen, B. Factor","doi":"10.1109/ESTC.2014.6962759","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962759","url":null,"abstract":"The industry saw the transition of flip chip technology from lead free solder system to Cu pillar bump a few years ago. The risk of fail location under electromigration (EM) shifts from the solder/UBM interface of the standard solder bump to the solder joint of the Cu pillar solder joint. This study investigated the performance of the Cu pillar solder interconnect under current stress testing and temperature acceleration. The EM stress test of Cu pillar bumps interconnect was designed and implemented comparing the bump solder tips joined with OSP (organic solderability preservative)-Cu (the OSP-Cu bump) substrate and ENEPIG (electroless Ni(P)/electroless Pd/immersion Au)-Cu (the ENEPIG-Cu bump) substrate. The bumps with different solder volumes, 20 μm and 50 μm in height, were investigated for EM performance comparison. The EM testing was conducted at current density 7 kA/cm2 under various temperatures of 125 °C, 135 °C and 150 °C. The EM duration time of Cu pillar bump joints were estimated for testing up to 10000 hours. The joint with smaller solder volume tends to exhibit better EM life. The experimental results showed that the Cu pillar bumps on OSP-Cu performed superior to that on ENEPIG-Cu. The cross sectional microstructure analysis indicates that the intermetallic compound (IMC) formed are mainly Cu6Sn5 and Cu3Sn for the Cu pillar bump joint on OSP-Cu substrate, while (Au, Pd)Sn4 was also detected for the ENEPIG-Cu substrate. The failure analysis of the failed joints indicated that the failure behavior closely related to the volume of IMC formed and the IMC structure within the Cu pillar joint.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134400700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962745
C. Palesko, Amy Palesko, E. J. Vardaman
As the market drives electronic products to be smaller and faster, designers must use advanced packaging technologies. In many cases, these technologies are significantly more expensive than traditional packaging, but are necessary to meet the product requirements. Both fan-out wafer level packaging and 2.5D packaging on a silicon interposer enable designers to package multiple die in close proximity. This close proximity helps achieve miniaturization and may enable better performance since die to die interconnect is shorter. However, care must be taken to manage the total cost and yield of the system. Both of these technologies have the potential to meet the smaller and faster market requirement, but if either is used on the wrong design, the cost can be high and the yield can be low. In this paper we will compare and contrast the packaging cost drivers for multi-die fan-out wafer level packaging and 2.5D packaging on a silicon interposer. Total cost and yield plus individual activity costs and yields will be presented across a range of design characteristics including package size, die size, number of die, and number of IOs. An in depth analysis of the cost of cumulative yield loss will be presented for both technologies. A sensitivity analysis on key cost and yield drivers will also be presented in the paper.
{"title":"Cost and yield analysis of multi-die packaging using 2.5D technology compared to fan-out wafer level packaging","authors":"C. Palesko, Amy Palesko, E. J. Vardaman","doi":"10.1109/ESTC.2014.6962745","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962745","url":null,"abstract":"As the market drives electronic products to be smaller and faster, designers must use advanced packaging technologies. In many cases, these technologies are significantly more expensive than traditional packaging, but are necessary to meet the product requirements. Both fan-out wafer level packaging and 2.5D packaging on a silicon interposer enable designers to package multiple die in close proximity. This close proximity helps achieve miniaturization and may enable better performance since die to die interconnect is shorter. However, care must be taken to manage the total cost and yield of the system. Both of these technologies have the potential to meet the smaller and faster market requirement, but if either is used on the wrong design, the cost can be high and the yield can be low. In this paper we will compare and contrast the packaging cost drivers for multi-die fan-out wafer level packaging and 2.5D packaging on a silicon interposer. Total cost and yield plus individual activity costs and yields will be presented across a range of design characteristics including package size, die size, number of die, and number of IOs. An in depth analysis of the cost of cumulative yield loss will be presented for both technologies. A sensitivity analysis on key cost and yield drivers will also be presented in the paper.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132330426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962766
S. Schmitz, J. Kripfgans, M. Schneider-Ramelow, W. Muller, K. Lang
This study found that standard wire pull testing models introduced more than 20 years ago are insufficient under certain circumstances, including the larger wire bond angles used in applications for automotive control units, pressure sensor devices and COB. The techniques assessed were those given in the German industrial specification DVS Merkblatt 2811 and the international standards MIL-STD-883G and ASTM-F459-06 by comparing the calculated results with actual wire bond pull tests results. The detrimental impact of such failures on standard wire bonding quality control parameters (e.g. the typically used cpk value) can be significant. A new FEM model was developed to investigate possible solutions to the shortfall in accuracy. The data thus obtained was then fed into a new analytical model, based on the Capstan model, which is easily transferred to standard industry and research settings. All measurements, calculations and simulation results were correlated.
{"title":"Investigating wire bonding pull testing and its calculation basics","authors":"S. Schmitz, J. Kripfgans, M. Schneider-Ramelow, W. Muller, K. Lang","doi":"10.1109/ESTC.2014.6962766","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962766","url":null,"abstract":"This study found that standard wire pull testing models introduced more than 20 years ago are insufficient under certain circumstances, including the larger wire bond angles used in applications for automotive control units, pressure sensor devices and COB. The techniques assessed were those given in the German industrial specification DVS Merkblatt 2811 and the international standards MIL-STD-883G and ASTM-F459-06 by comparing the calculated results with actual wire bond pull tests results. The detrimental impact of such failures on standard wire bonding quality control parameters (e.g. the typically used cpk value) can be significant. A new FEM model was developed to investigate possible solutions to the shortfall in accuracy. The data thus obtained was then fed into a new analytical model, based on the Capstan model, which is easily transferred to standard industry and research settings. All measurements, calculations and simulation results were correlated.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133393055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962725
O. Goualard, N. Videau, Thi Bang Doan, T. Lebey, V. Bley, T. Meynard
Modern power electronics is focused on highly efficient, compact and cost-effective converters. In this paper, gallium nitride (GaN) transistors, multicell topology and integrated capacitors are combined to achieve these objectives. The first results of a 48V-to-5V DC/DC 3-level converter using integrated screen printed capacitors are presented. The power board is designed by assembling a ceramic substrate, with integrated capacitors using a Kapton® film as an insulation layer, and a multilayer PCB substrate for the active components. The integrated screen-printed capacitors technique and the proposed power board assembly allow double side cooling of the power semiconductors.
{"title":"Integrated screen printed capacitors in a GaN DC-DC converter allowing double side cooling","authors":"O. Goualard, N. Videau, Thi Bang Doan, T. Lebey, V. Bley, T. Meynard","doi":"10.1109/ESTC.2014.6962725","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962725","url":null,"abstract":"Modern power electronics is focused on highly efficient, compact and cost-effective converters. In this paper, gallium nitride (GaN) transistors, multicell topology and integrated capacitors are combined to achieve these objectives. The first results of a 48V-to-5V DC/DC 3-level converter using integrated screen printed capacitors are presented. The power board is designed by assembling a ceramic substrate, with integrated capacitors using a Kapton® film as an insulation layer, and a multilayer PCB substrate for the active components. The integrated screen-printed capacitors technique and the proposed power board assembly allow double side cooling of the power semiconductors.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"397 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114920595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962757
R. Dohle, Marek Gorywoda, A. Wirth, J. Gosler
Packaging technology has to continuously evolve in order to keep pace with the demand for smaller and lighter products. One manifestation of this is the need to drastically reduce the size of flip-chip bumps and their pitch. To make things more challenging, the changes have to be mastered with new materials in response to lead-free legislation. At the same time the reliability of the electronic devices should not be sacrificed. In this respect, a relatively new challenge is also posed by the observation, that solder connections are vulnerable to electromigration. The aim of this research was to evaluate the long-term electromigration behaviour of lead-free (SAC305) flipchip solder connections with a nominal diameter of 60 μm or 50 μm, which have been assembled in flip-chip organic packages having electroless Nickel under bump metallization with a pitch of 100 μm. Test vehicles were subjected to electromigration tests for over 25,000 hours at constant current densities of 8 kA/cm2 or 5 kA/cm2 respectively, and nominal temperatures of 125 °C, 100 °C, or 28 °C until failure. The failure data has been evaluated employing Weibull statistics as well as lognormal distribution and the mean time to failure (MTTF) has been calculated. Only three out of twelve samples have failed after 25,000 h for 50 μm solder bumps tested at a current density of 5 kA/cm2 and a temperature of 100 °C; no failures at all have been observed at an ambient temperature of 28 °C. The comparison of the MTTFs for the different bump diameters leads to the result that, under the same testing conditions of current density and temperature, the life time of smaller bumps is considerably longer. This - on first sight - surprising finding can be explained by lower heat generation due to current flow, and thus by a lower temperature of these bumps. The results were subsequently used to estimate the parameters of Black's equation. The evaluation yielded an activation energy of Ea = 1.13±0.18 eV and a current density exponent in the range of n = 4.9-2.2. The relatively high value of Ea points to a good robustness of the bump metallization investigated in our study; the variation of n indicates a change in failure mechanism.
{"title":"Investigation of electromigration behaviour in lead-free flip-chip solders connections","authors":"R. Dohle, Marek Gorywoda, A. Wirth, J. Gosler","doi":"10.1109/ESTC.2014.6962757","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962757","url":null,"abstract":"Packaging technology has to continuously evolve in order to keep pace with the demand for smaller and lighter products. One manifestation of this is the need to drastically reduce the size of flip-chip bumps and their pitch. To make things more challenging, the changes have to be mastered with new materials in response to lead-free legislation. At the same time the reliability of the electronic devices should not be sacrificed. In this respect, a relatively new challenge is also posed by the observation, that solder connections are vulnerable to electromigration. The aim of this research was to evaluate the long-term electromigration behaviour of lead-free (SAC305) flipchip solder connections with a nominal diameter of 60 μm or 50 μm, which have been assembled in flip-chip organic packages having electroless Nickel under bump metallization with a pitch of 100 μm. Test vehicles were subjected to electromigration tests for over 25,000 hours at constant current densities of 8 kA/cm2 or 5 kA/cm2 respectively, and nominal temperatures of 125 °C, 100 °C, or 28 °C until failure. The failure data has been evaluated employing Weibull statistics as well as lognormal distribution and the mean time to failure (MTTF) has been calculated. Only three out of twelve samples have failed after 25,000 h for 50 μm solder bumps tested at a current density of 5 kA/cm2 and a temperature of 100 °C; no failures at all have been observed at an ambient temperature of 28 °C. The comparison of the MTTFs for the different bump diameters leads to the result that, under the same testing conditions of current density and temperature, the life time of smaller bumps is considerably longer. This - on first sight - surprising finding can be explained by lower heat generation due to current flow, and thus by a lower temperature of these bumps. The results were subsequently used to estimate the parameters of Black's equation. The evaluation yielded an activation energy of Ea = 1.13±0.18 eV and a current density exponent in the range of n = 4.9-2.2. The relatively high value of Ea points to a good robustness of the bump metallization investigated in our study; the variation of n indicates a change in failure mechanism.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116223418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962825
K. Kielbasinski, J. Szałapak, J. Krzemiński, A. Mlozniak, E. Zwierkowska, M. Teodorczyk, O. Jeremiasz, M. Jakubowska
Aluminium busbar connectors provide high current connections between metal connectors and are widely used in electrical power industry. They are formed by clamping two or more plates of flat aluminium with the use of bolts and nuts. Plain aluminium tends to form oxide, which is known of it's very high resistivity To avoid that effect, a surface of aluminium can be electroplated with silver. The main drawback of this method is a toxic waste production. Another problem is the possibility to repair it in outdoor conditions Due to high surface energy of nano-particles, sintering of layers occurs in temperatures much below silver melting point (961°C), and which is more important below melting point of aluminium (660°C). Pastes containing nanosize silver powders were prepared. They were screen printed on etched aluminium plates and cured in several temperatures varying from 300 to 500°C. The plates were pressed towards, forming contact joint that simulates the bolted connection. The contact resistivity versus pressure was tested.
{"title":"Aluminium silvering of high current connectors using printing techniques and nanopowders","authors":"K. Kielbasinski, J. Szałapak, J. Krzemiński, A. Mlozniak, E. Zwierkowska, M. Teodorczyk, O. Jeremiasz, M. Jakubowska","doi":"10.1109/ESTC.2014.6962825","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962825","url":null,"abstract":"Aluminium busbar connectors provide high current connections between metal connectors and are widely used in electrical power industry. They are formed by clamping two or more plates of flat aluminium with the use of bolts and nuts. Plain aluminium tends to form oxide, which is known of it's very high resistivity To avoid that effect, a surface of aluminium can be electroplated with silver. The main drawback of this method is a toxic waste production. Another problem is the possibility to repair it in outdoor conditions Due to high surface energy of nano-particles, sintering of layers occurs in temperatures much below silver melting point (961°C), and which is more important below melting point of aluminium (660°C). Pastes containing nanosize silver powders were prepared. They were screen printed on etched aluminium plates and cured in several temperatures varying from 300 to 500°C. The plates were pressed towards, forming contact joint that simulates the bolted connection. The contact resistivity versus pressure was tested.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132753535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962789
F. Duval, M. Detalle, X. Sun, E. Beyne, C. Neve, D. Velenis
This paper explores the possibility to use insulating spin-on dielectric materials for 2.5D interposers. Up to 7 photosensitive materials have been investigated in terms of minimum line/space and via resolution to determine the maximum wiring density. In addition the electrical performances of the best materials were assessed in DC and RF to extract the dielectric constant and loss tangent. Finally the polymer semi-additive process was compared to a Damascene technology using the Wide I/O 2 as case study. The overall performances of each technology are assessed in terms of electrical performances, cost of ownership and wafer bowing. It was shown that the semiadditive process can compete with a conventional Damascene process. The best performing material is a phenol-based polymer, positive tone, aqueous developable, low temperature cure and with a high resolution (up to AR of 1:3).
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