Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962852
R. Klengel, S. Klengel, J. Schischka, G. Lorenz, M. Petzold
In recent years Ni wire bonding has found some interest as a contacting technology for high temperature applications or for power electronic components. In addition to high thermal stability, further advantageous properties of Ni wires are its good electrical conductivity and a high mechanical strength. On the other hand, the relatively high hardness of the wires entails the risk of defect formation, particularly if applied for bonding on semiconductor components. In the presented investigation it was tried to improve the bond process parameters to lower bond forces by sputtering the wire with nm thick aluminum layer which should support the binding mechanisms. The paper presents mechanical characterization of the wire before and after sputtering, morphology and adhesion behavior of Al sputter layer on the wire as well as the contact formation in the wire bond interface after wedge-wedge bonding on different metallization. Mechanical test methods like tensile test and nano-indentation were performed as well as high resolution preparation and analyzes methods like focused ion beam technique (FIB), scanning electron microscopy (SEM) and transmission electron microscopy (TEM).
{"title":"Improvement of nickel wire bonding using Al nano coating","authors":"R. Klengel, S. Klengel, J. Schischka, G. Lorenz, M. Petzold","doi":"10.1109/ESTC.2014.6962852","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962852","url":null,"abstract":"In recent years Ni wire bonding has found some interest as a contacting technology for high temperature applications or for power electronic components. In addition to high thermal stability, further advantageous properties of Ni wires are its good electrical conductivity and a high mechanical strength. On the other hand, the relatively high hardness of the wires entails the risk of defect formation, particularly if applied for bonding on semiconductor components. In the presented investigation it was tried to improve the bond process parameters to lower bond forces by sputtering the wire with nm thick aluminum layer which should support the binding mechanisms. The paper presents mechanical characterization of the wire before and after sputtering, morphology and adhesion behavior of Al sputter layer on the wire as well as the contact formation in the wire bond interface after wedge-wedge bonding on different metallization. Mechanical test methods like tensile test and nano-indentation were performed as well as high resolution preparation and analyzes methods like focused ion beam technique (FIB), scanning electron microscopy (SEM) and transmission electron microscopy (TEM).","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127508803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962835
T. Brunschwiler, T. Tick, Michele Castriotta, G. Schlottig, Dominic Gschwend, Ken Sato, T. Nakajima, Shidong Li, S. Oggioni
We report on the design, implementation and performance of a laminate named Thermal Power Plane and solder joints that enable dual-side electrical interconnects (EIC) to a chip stack. This novel packaging topology with a laminate on both sides of the chip stack doubles the number of EIC thus supporting increased communication bandwidth and power density. In addition, in a two-die stack, all power TSVs can be eliminated with the advantage of gained silicon active area. The use of two laminates also enables individual test & burn-in of the dies before stack formation. The TPP needs to provide efficient heat removal and current feed in the out-of-plane and in-plane direction, respectively. An 8+1 coreless build-up laminate with aligned and stacked thermal laminate vias (TLVs) was designed and implemented. Bar-, chevron- and mesh-like copper planes with varying TLV densities were characterized. The mesh design resulted in minimal warpage and voltage drop. The bar and chevron designs result in the lowest thermal resistance. In combination with rail-shaped solder interconnects interfacing between TPP and top chip, the overall thermal resistance of the junction to cold plate of the dual-side EIC approach can outperform that of the standard single-side EIC package. The electrical DC characteristics of the TPP was also evaluated experimentally. The sheet resistance of 0.21 MΩ allows the supply of the required currents within the voltage uniformity requirements. In general, the experimental evaluation supports the feasibility of the proposed dual-side EIC concept supporting further performance and efficiency scaling of high-performance chip stacks.
{"title":"Thermal power plane enabling dual-side electrical interconnects for high-performance chip stacks: Implementation","authors":"T. Brunschwiler, T. Tick, Michele Castriotta, G. Schlottig, Dominic Gschwend, Ken Sato, T. Nakajima, Shidong Li, S. Oggioni","doi":"10.1109/ESTC.2014.6962835","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962835","url":null,"abstract":"We report on the design, implementation and performance of a laminate named Thermal Power Plane and solder joints that enable dual-side electrical interconnects (EIC) to a chip stack. This novel packaging topology with a laminate on both sides of the chip stack doubles the number of EIC thus supporting increased communication bandwidth and power density. In addition, in a two-die stack, all power TSVs can be eliminated with the advantage of gained silicon active area. The use of two laminates also enables individual test & burn-in of the dies before stack formation. The TPP needs to provide efficient heat removal and current feed in the out-of-plane and in-plane direction, respectively. An 8+1 coreless build-up laminate with aligned and stacked thermal laminate vias (TLVs) was designed and implemented. Bar-, chevron- and mesh-like copper planes with varying TLV densities were characterized. The mesh design resulted in minimal warpage and voltage drop. The bar and chevron designs result in the lowest thermal resistance. In combination with rail-shaped solder interconnects interfacing between TPP and top chip, the overall thermal resistance of the junction to cold plate of the dual-side EIC approach can outperform that of the standard single-side EIC package. The electrical DC characteristics of the TPP was also evaluated experimentally. The sheet resistance of 0.21 MΩ allows the supply of the required currents within the voltage uniformity requirements. In general, the experimental evaluation supports the feasibility of the proposed dual-side EIC concept supporting further performance and efficiency scaling of high-performance chip stacks.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"468 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123657302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962775
Corné Rentrop, Erik Rubingh, R. Lelieveld, Henrik Sandberg
The ROPAS project (Roll-to-roll paper sensors) combines high end electronics and wireless sensors with low cost paper substrates and processing techniques that can be applied on a large scale. Paper is the next step in the printed electronics roadmap of utilising cheaper substrate materials as a replacement of silicon and PET and is generally referred to as paper electronics. The creation of highly conductive structures applied at high speed on (temperature unstable) paper is extremely important to enable paper electronics. Hereto, recent advantages in nanotechnology such as (encapsulation) printing, surface modification of fiber based products, sensor and battery development, and electronic design (wireless communication) are integrated for large scale roll to roll and sheet to sheet paper applications. The possibilities of paper electronics are demonstrated in high impact (security) and logistics applications, which are demonstrated in security tags and smart labels for anti-counterfeiting purposes by e.g. integration of near field communication (NFC) in paper and finally track-and-trace post pieces such as envelopes. The paper explains the project and its impact, including implications of using a rough, coarse, porous and composite, paper substrate of limited high temperature stability on the design and fabrication of demonstrators and building blocks. Important topics herein are: fast curing of conductive inks on paper using state of the art printing techniques such as inkjet, screen and flexogravure. In the talk, synthesis of printable (humidity) sensor materials, placing of electrical components on paper surfaces including electronic design of the wireless communication and environmental and recycling constraints of the products are discussed as well.
{"title":"Roll-to-roll paper sensors (ROPAS); Wireless communicating sensors on paper in the logistic chain","authors":"Corné Rentrop, Erik Rubingh, R. Lelieveld, Henrik Sandberg","doi":"10.1109/ESTC.2014.6962775","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962775","url":null,"abstract":"The ROPAS project (Roll-to-roll paper sensors) combines high end electronics and wireless sensors with low cost paper substrates and processing techniques that can be applied on a large scale. Paper is the next step in the printed electronics roadmap of utilising cheaper substrate materials as a replacement of silicon and PET and is generally referred to as paper electronics. The creation of highly conductive structures applied at high speed on (temperature unstable) paper is extremely important to enable paper electronics. Hereto, recent advantages in nanotechnology such as (encapsulation) printing, surface modification of fiber based products, sensor and battery development, and electronic design (wireless communication) are integrated for large scale roll to roll and sheet to sheet paper applications. The possibilities of paper electronics are demonstrated in high impact (security) and logistics applications, which are demonstrated in security tags and smart labels for anti-counterfeiting purposes by e.g. integration of near field communication (NFC) in paper and finally track-and-trace post pieces such as envelopes. The paper explains the project and its impact, including implications of using a rough, coarse, porous and composite, paper substrate of limited high temperature stability on the design and fabrication of demonstrators and building blocks. Important topics herein are: fast curing of conductive inks on paper using state of the art printing techniques such as inkjet, screen and flexogravure. In the talk, synthesis of printable (humidity) sensor materials, placing of electrical components on paper surfaces including electronic design of the wireless communication and environmental and recycling constraints of the products are discussed as well.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123060567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962826
T. Matsuo, T. Sugahara, Y. Hirose, J. Jiu, S. Nagao, K. Suganuma, Jianying He, Zhiliang Zhang
We fabricated stack layer transparent conductive IGZO thin films for TFT device applications using a sol-gel method. This research focuses on the properties of the resulting thin films to evaluate the ability of solution methods to replace current ultra-high vacuum techniques to fabricate thin films and its used devices. In this paper, we describe our high quality solution deposited technique: developing a sol-gel process that produced TCO semiconductor layer films with surface roughness in the same order as that of films formed by ultra-high vacuum deposition. As a result, good electrical conductivity and optical transmittance were achieved. The results suggest that solution-based methods show promise as an alternative to ultra-high vacuum methods to produce TCO thin films.
{"title":"Photoelectrical and microphysical properties of Sol-Gel derived IGZO thin films for printed TFTs","authors":"T. Matsuo, T. Sugahara, Y. Hirose, J. Jiu, S. Nagao, K. Suganuma, Jianying He, Zhiliang Zhang","doi":"10.1109/ESTC.2014.6962826","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962826","url":null,"abstract":"We fabricated stack layer transparent conductive IGZO thin films for TFT device applications using a sol-gel method. This research focuses on the properties of the resulting thin films to evaluate the ability of solution methods to replace current ultra-high vacuum techniques to fabricate thin films and its used devices. In this paper, we describe our high quality solution deposited technique: developing a sol-gel process that produced TCO semiconductor layer films with surface roughness in the same order as that of films formed by ultra-high vacuum deposition. As a result, good electrical conductivity and optical transmittance were achieved. The results suggest that solution-based methods show promise as an alternative to ultra-high vacuum methods to produce TCO thin films.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125001971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962743
Tomoko Takahashi, H. Inoue, Takahiro Yada, Naoki Hayashi, Yukari Imaizumi, Y. Ikemoto, Shigenori Sawachi, Atsushi Furuno, K. Yoshimitsu, M. Ooida, Akio Katsumata, Y. Hiruta
A new package structure and technology for the next generation of embedded-die package named as WFOP™ (Wide panel Fan-Out Package) was developed. It's a facedown mounting type, using metal plate as the base plate of its redistributed layer. Manufacturing is done not in wafer scale, but in large scale panel substrate. The structure, process, reliability results, and some performance are introduced. The package assembly technology for WFOP is using die-embedding method. So the technology is also able to apply to 3D packages. Some experience of 3D packages is shown in this paper. This technology will be expected to lead a new packaging technology for the next generation.
{"title":"A new embedded die package — WFOP™","authors":"Tomoko Takahashi, H. Inoue, Takahiro Yada, Naoki Hayashi, Yukari Imaizumi, Y. Ikemoto, Shigenori Sawachi, Atsushi Furuno, K. Yoshimitsu, M. Ooida, Akio Katsumata, Y. Hiruta","doi":"10.1109/ESTC.2014.6962743","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962743","url":null,"abstract":"A new package structure and technology for the next generation of embedded-die package named as WFOP™ (Wide panel Fan-Out Package) was developed. It's a facedown mounting type, using metal plate as the base plate of its redistributed layer. Manufacturing is done not in wafer scale, but in large scale panel substrate. The structure, process, reliability results, and some performance are introduced. The package assembly technology for WFOP is using die-embedding method. So the technology is also able to apply to 3D packages. Some experience of 3D packages is shown in this paper. This technology will be expected to lead a new packaging technology for the next generation.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125073558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962787
A. Novikov, D. Lexow, M. Nowottnick
A novel concept of using phase change materials (PCM) to improve the thermal management of electronic components was investigated. The main idea is the smoothing of temperature peaks produced by the component itself or by high ambient temperature. This was realized by heat absorption during melting process of the PCM. Such materials can be used in powder form as additive to the standard coating material like resin or will be applied directly on the electronic component and encapsulated by a polymer material.
{"title":"Cooling of electronic assemblies through PCM containing coatings","authors":"A. Novikov, D. Lexow, M. Nowottnick","doi":"10.1109/ESTC.2014.6962787","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962787","url":null,"abstract":"A novel concept of using phase change materials (PCM) to improve the thermal management of electronic components was investigated. The main idea is the smoothing of temperature peaks produced by the component itself or by high ambient temperature. This was realized by heat absorption during melting process of the PCM. Such materials can be used in powder form as additive to the standard coating material like resin or will be applied directly on the electronic component and encapsulated by a polymer material.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131548046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962746
Eoin O. Toole, R. Almeida, J. Campos, A. Martins, A. Cardoso, F. Cardoso, S. Kroehnert
The use of embedded Wafer Level Ball grid array(eWLB)[1] technology for the construction of single and multiple side by side die packages has become widespread since the introduction by Infineon technologies more than five years ago. The flexibility of this packaging to include different die material types such as Si and GaAs combined with excellent mechanical, electrical and thermal performance and the advantages of wafer level processing has been employed in a wide range of applications. More recently this flexibility has been extended to included system in package(SiP) applications with a range of embedded passive devices being combined with one or more active dies in a single package. Ideally, for motives of availability and cost, the passive devices utilized in these applications should be standard SMT devices without special requirements in terms of terminal finish. In this paper we will describe the development process involved in enabling the use of standard leadfree tin finished passive devices in embedded eWLB based SiP packages. Development of a variety of potential diffusion barriers based upon both multilayer physical vapor deposition(PVD) and electroplated metallization is explained. Significant insight into the reliability performance of the resulting packages under standard stress conditions is gained for a SiP test vehicle. The first assessment was performed using short build parts to enable a rapid feedback for the experiments. The output for this comparison was Jedec standard High Temperature Storage(HTS175°C 200hrs) stress condition. Scanning electron micrography and microsection analysis of the intermetallic region formed before and after stress with a range of barrier solutions are shown. The solution selection process is described both in terms of reliability and ease of implementation. Further development based on the initial findings suggests a path forward for potential implementation of tinned terminal passives in eWLB.
{"title":"eWLB SiP with Sn finished passives","authors":"Eoin O. Toole, R. Almeida, J. Campos, A. Martins, A. Cardoso, F. Cardoso, S. Kroehnert","doi":"10.1109/ESTC.2014.6962746","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962746","url":null,"abstract":"The use of embedded Wafer Level Ball grid array(eWLB)[1] technology for the construction of single and multiple side by side die packages has become widespread since the introduction by Infineon technologies more than five years ago. The flexibility of this packaging to include different die material types such as Si and GaAs combined with excellent mechanical, electrical and thermal performance and the advantages of wafer level processing has been employed in a wide range of applications. More recently this flexibility has been extended to included system in package(SiP) applications with a range of embedded passive devices being combined with one or more active dies in a single package. Ideally, for motives of availability and cost, the passive devices utilized in these applications should be standard SMT devices without special requirements in terms of terminal finish. In this paper we will describe the development process involved in enabling the use of standard leadfree tin finished passive devices in embedded eWLB based SiP packages. Development of a variety of potential diffusion barriers based upon both multilayer physical vapor deposition(PVD) and electroplated metallization is explained. Significant insight into the reliability performance of the resulting packages under standard stress conditions is gained for a SiP test vehicle. The first assessment was performed using short build parts to enable a rapid feedback for the experiments. The output for this comparison was Jedec standard High Temperature Storage(HTS175°C 200hrs) stress condition. Scanning electron micrography and microsection analysis of the intermetallic region formed before and after stress with a range of barrier solutions are shown. The solution selection process is described both in terms of reliability and ease of implementation. Further development based on the initial findings suggests a path forward for potential implementation of tinned terminal passives in eWLB.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130330901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962812
Steffen Wiese, F. Kraemer
The paper presents an approach to model the mechanical behaviour of copper in 2nd level interconnect structures in electronic assemblies. The discussed mechanical models were analysed in ANSYS and LS-DYNA FEM-Software in order to simulate the performance of typical structural elements in electronic assemblies, such as copper traces or solder pads. Loading conditions span a wide range from low rate deformation of thermal cycles to high rate deformation during drop testing. This study investigated the effect of different mechanical properties of copper, with respect to the stress-strain relationship in 2nd level interconnects. The effect of the anisotropy of Young's modulus, in addition to the effect of isotropic cyclic hardening on the resulting deformation and stresses in the copper structures, were analysed. Furthermore, the resulting contact forces at the copper pad to the solder and to the PCB epoxy material, were investigated. This paper presents specific observations made during the three-dimensional finite element simulations of typical interconnect structures. Microstructural investigations were also carried out, such as to be able to correlate particular mechanical behaviour with established knowledge about copper as an FCC material. Grain sizes and texture of real copper traces are estimated. This study relates these particular features of real structures in electronic assemblies to published properties of copper mono- and polycrystalline materials. The importance of microstructural properties, such as grain size and orientation in terms of their respective influence on the results, are also discussed.
{"title":"Modelling of the mechanical behaviour of copper in 2nd level interconnection structures","authors":"Steffen Wiese, F. Kraemer","doi":"10.1109/ESTC.2014.6962812","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962812","url":null,"abstract":"The paper presents an approach to model the mechanical behaviour of copper in 2nd level interconnect structures in electronic assemblies. The discussed mechanical models were analysed in ANSYS and LS-DYNA FEM-Software in order to simulate the performance of typical structural elements in electronic assemblies, such as copper traces or solder pads. Loading conditions span a wide range from low rate deformation of thermal cycles to high rate deformation during drop testing. This study investigated the effect of different mechanical properties of copper, with respect to the stress-strain relationship in 2nd level interconnects. The effect of the anisotropy of Young's modulus, in addition to the effect of isotropic cyclic hardening on the resulting deformation and stresses in the copper structures, were analysed. Furthermore, the resulting contact forces at the copper pad to the solder and to the PCB epoxy material, were investigated. This paper presents specific observations made during the three-dimensional finite element simulations of typical interconnect structures. Microstructural investigations were also carried out, such as to be able to correlate particular mechanical behaviour with established knowledge about copper as an FCC material. Grain sizes and texture of real copper traces are estimated. This study relates these particular features of real structures in electronic assemblies to published properties of copper mono- and polycrystalline materials. The importance of microstructural properties, such as grain size and orientation in terms of their respective influence on the results, are also discussed.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124692946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962808
H. T. Wang, W. Tan, C. F. Cheong
Solder joint crack in thermal cycling on board (TCoB) for surface mount devices (SMD) is becoming more stringent in semiconductor market. Current TCoB literature mainly focuses on Finite Element Analysis simulation with ANSYS software to identify the most sensitive parameters affecting TCoB performance and estimating the solder fatigue life. By a given Driver Mosfet Power QFN, this paper is focusing on actual TCoB by modifying mold compound's coefficient of thermal expansion (CTE) and storage modulus by altering the filler loading percentage and adding in additive either stress relief additive (SRA) or silicone. These modifications reduce mold compound viscosity, increase CTE1, mold shrinkage potentially increases challenges in wire sweep and map molding panel warpage. Six different mold compounds are assembled and soldered on a PCB board with TCoB condition of -40°C to 125°C. The judging criteria is concentrating on solder joint crack. Package level reliability MSL3@260°C, 500 cycle TC(-65/150°C) and 96h PCT are evaluated. Material analysis of Thermal Mechanical Analysis (TMA) and Dynamic Mechanical Analysis (DMA) are employed to analyze the coefficient of thermal expansion (CTE), glass transition temperature (Tg) and storage modulus of six different mold compounds. Filler loading reduction increase liquid to solid particles ratio, therefore wire sweep and process mapping result for all mold compounds are comparable. Increment of resin induce criticalness of panel warpage as mold shrinkage increases, result shows that filler content ≤87wt% increases panel warpage > 0.7mm which increase the difficulty in package singulation. Experimental TCoB reviews that corner leads are subjected to the highest thermal mechanical stress and becomes the initiation point of solder joint crack. Result further validates storage modulus is primary factor of mold compound instead of CTE1. Higher solder joint thickness ≥34μm is sufficient to prevent solder joint crack and meet TCoB requirement.
{"title":"A novel study of mold compound effect towards TCoB and process integration for power leadless package","authors":"H. T. Wang, W. Tan, C. F. Cheong","doi":"10.1109/ESTC.2014.6962808","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962808","url":null,"abstract":"Solder joint crack in thermal cycling on board (TCoB) for surface mount devices (SMD) is becoming more stringent in semiconductor market. Current TCoB literature mainly focuses on Finite Element Analysis simulation with ANSYS software to identify the most sensitive parameters affecting TCoB performance and estimating the solder fatigue life. By a given Driver Mosfet Power QFN, this paper is focusing on actual TCoB by modifying mold compound's coefficient of thermal expansion (CTE) and storage modulus by altering the filler loading percentage and adding in additive either stress relief additive (SRA) or silicone. These modifications reduce mold compound viscosity, increase CTE1, mold shrinkage potentially increases challenges in wire sweep and map molding panel warpage. Six different mold compounds are assembled and soldered on a PCB board with TCoB condition of -40°C to 125°C. The judging criteria is concentrating on solder joint crack. Package level reliability MSL3@260°C, 500 cycle TC(-65/150°C) and 96h PCT are evaluated. Material analysis of Thermal Mechanical Analysis (TMA) and Dynamic Mechanical Analysis (DMA) are employed to analyze the coefficient of thermal expansion (CTE), glass transition temperature (Tg) and storage modulus of six different mold compounds. Filler loading reduction increase liquid to solid particles ratio, therefore wire sweep and process mapping result for all mold compounds are comparable. Increment of resin induce criticalness of panel warpage as mold shrinkage increases, result shows that filler content ≤87wt% increases panel warpage > 0.7mm which increase the difficulty in package singulation. Experimental TCoB reviews that corner leads are subjected to the highest thermal mechanical stress and becomes the initiation point of solder joint crack. Result further validates storage modulus is primary factor of mold compound instead of CTE1. Higher solder joint thickness ≥34μm is sufficient to prevent solder joint crack and meet TCoB requirement.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"18 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120846444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962791
D. Braden, D. Harvey
There is a continual growth of test and validation in high reliability product applications such as automotive, military and avionics. Principally this is driven by increased use and complexity of electronic systems installed in vehicles in addition to increased end user reliability expectations. Furthermore product development cycles continue to reduce, resulting in less available time to perform accelerated life tests. Moreover, significant increases in test duration are observed as a direct result of raised reliability expectations. The challenge for automotive electronic suppliers in particular is performing life tests in shorter periods of time whilst reducing the overall associated costs of validation testing. The dichotomy is that reliability testing at the component level does not replicate the intended mission environment. Often this can result in disputes between component suppliers and end users. The focus for many component suppliers is on the thermal performance of devices, but real applications require other factors to be considered, such as manufacturing influences during circuit board manufacture and assembly, mechanical stresses and device interactions. Furthermore, previous work by the authors suggests that interconnect and system level reliability is significantly impacted by component layout and constraint points which are application specific [1] [2] [3]. In this paper, a review of suitable prognostic techniques is undertaken and an approach proposed in which reliability testing results at component level matches more closely that undertaken at system level.
{"title":"Aligning component and system qualification testing through prognostics","authors":"D. Braden, D. Harvey","doi":"10.1109/ESTC.2014.6962791","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962791","url":null,"abstract":"There is a continual growth of test and validation in high reliability product applications such as automotive, military and avionics. Principally this is driven by increased use and complexity of electronic systems installed in vehicles in addition to increased end user reliability expectations. Furthermore product development cycles continue to reduce, resulting in less available time to perform accelerated life tests. Moreover, significant increases in test duration are observed as a direct result of raised reliability expectations. The challenge for automotive electronic suppliers in particular is performing life tests in shorter periods of time whilst reducing the overall associated costs of validation testing. The dichotomy is that reliability testing at the component level does not replicate the intended mission environment. Often this can result in disputes between component suppliers and end users. The focus for many component suppliers is on the thermal performance of devices, but real applications require other factors to be considered, such as manufacturing influences during circuit board manufacture and assembly, mechanical stresses and device interactions. Furthermore, previous work by the authors suggests that interconnect and system level reliability is significantly impacted by component layout and constraint points which are application specific [1] [2] [3]. In this paper, a review of suitable prognostic techniques is undertaken and an approach proposed in which reliability testing results at component level matches more closely that undertaken at system level.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132597221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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