Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272583
S. Voldman, S. Luo, C. Nomura, K. Vannorsdel, N. Feilchenfeld
Experimental studies on the ESD protection were completed on advanced magnetic recording giant magneto-resistive heads using a BiCMOS silicon germanium technology for the first time. SiGe-based active and passive elements, such as isolated MOSFETs, varactors and Schottky diodes were used to evaluate the influence of turn-on voltage on the protection levels.
{"title":"Electrostatic discharge (ESD) protection of giant magneto-resistive (GMR) recording heads with a silicon germanium technology","authors":"S. Voldman, S. Luo, C. Nomura, K. Vannorsdel, N. Feilchenfeld","doi":"10.1109/EOSESD.2004.5272583","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272583","url":null,"abstract":"Experimental studies on the ESD protection were completed on advanced magnetic recording giant magneto-resistive heads using a BiCMOS silicon germanium technology for the first time. SiGe-based active and passive elements, such as isolated MOSFETs, varactors and Schottky diodes were used to evaluate the influence of turn-on voltage on the protection levels.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126551695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272597
Junjun Li, R. Gauthier, E. Rosenbaum
We present a novel RC-triggered, MOSFET-based power clamp for on-chip ESD protection. The cascaded PFET feedback technique is introduced. As with other feedback techniques, only a very small time constant is required for the RC trigger circuit which results in reduced capacitor area and reduced leakage at power-up. If mistriggering occurs, it is self-corrected with this dynamic feedback technique.
{"title":"A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection","authors":"Junjun Li, R. Gauthier, E. Rosenbaum","doi":"10.1109/EOSESD.2004.5272597","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272597","url":null,"abstract":"We present a novel RC-triggered, MOSFET-based power clamp for on-chip ESD protection. The cascaded PFET feedback technique is introduced. As with other feedback techniques, only a very small time constant is required for the RC trigger circuit which results in reduced capacitor area and reduced leakage at power-up. If mistriggering occurs, it is self-corrected with this dynamic feedback technique.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124848043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272581
T. Ohtsu, K. Kataoka, S. Natori
ESD robustness was studied for GMR heads with CrMnPt anti ferro material. We also studied the magnetic instability of GMR heads with dual GMR structure. It was found that heads with thick film structure had good ESD robustness and that the heads with dual structure had good stability by ESD.
{"title":"Improvement of ESD robustness and magnetic stability by structure of GMR head","authors":"T. Ohtsu, K. Kataoka, S. Natori","doi":"10.1109/EOSESD.2004.5272581","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272581","url":null,"abstract":"ESD robustness was studied for GMR heads with CrMnPt anti ferro material. We also studied the magnetic instability of GMR heads with dual GMR structure. It was found that heads with thick film structure had good ESD robustness and that the heads with dual structure had good stability by ESD.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123606844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272595
K. Domanski, S. Bargstadt-Franke, W. Stadler, U. Glaser, W. Bala
Detailed transient latch-up (TLU) analyses of external test structures show that a DC trigger does not necessarily reflect worst case conditions. Furthermore, the classical guard ring latch-up protection approach fails for transient trigger. In this contribution, design recommendations for TLU-safe designs are presented. The knowledge about the perturbation environment and an appropriate design are essential for a TLU-robust product.
{"title":"Development strategy for TLU-robust products","authors":"K. Domanski, S. Bargstadt-Franke, W. Stadler, U. Glaser, W. Bala","doi":"10.1109/EOSESD.2004.5272595","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272595","url":null,"abstract":"Detailed transient latch-up (TLU) analyses of external test structures show that a DC trigger does not necessarily reflect worst case conditions. Furthermore, the classical guard ring latch-up protection approach fails for transient trigger. In this contribution, design recommendations for TLU-safe designs are presented. The knowledge about the perturbation environment and an appropriate design are essential for a TLU-robust product.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122110817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272604
D. Bellmore
Characterizing ESD performances of automated handling equipment (AHE) has always been confusing, subjective, sometimes just plain arbitrary, and most of the time wrong. ESD sensitivity of devices is classified by an amplitude and type of discharge mode. For example, a device may be susceptible to a discharge of 200 volts human body model (HBM), charged device model (CDM), or machine model (MM). Each of the models has unique circuitry of capacitance and resistance to provide a specific current and rise time of the discharge at a specific voltage. This is fairly repeatable in most cases. On the other hand, attempts to classify AHEs based on voltage measured at certain points in the product path can be and most often is misleading. This paper deals with the experimental methods of measuring the discharge currents and the results of processing devices through automatic processes and placing them on a special board to promote a discharge.
{"title":"Characterizing automated handling equipment using discharge current measurements","authors":"D. Bellmore","doi":"10.1109/EOSESD.2004.5272604","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272604","url":null,"abstract":"Characterizing ESD performances of automated handling equipment (AHE) has always been confusing, subjective, sometimes just plain arbitrary, and most of the time wrong. ESD sensitivity of devices is classified by an amplitude and type of discharge mode. For example, a device may be susceptible to a discharge of 200 volts human body model (HBM), charged device model (CDM), or machine model (MM). Each of the models has unique circuitry of capacitance and resistance to provide a specific current and rise time of the discharge at a specific voltage. This is fairly repeatable in most cases. On the other hand, attempts to classify AHEs based on voltage measured at certain points in the product path can be and most often is misleading. This paper deals with the experimental methods of measuring the discharge currents and the results of processing devices through automatic processes and placing them on a special board to promote a discharge.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114756355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272616
R. Ashton, B. Weir, G. Weiss, T. Meuse
HBM and TLP measurements on dynamically triggered CMOS power supply clamps were found to be inconsistent for low leakage clamps. The failures at low HBM voltage were found to be due to a voltage ramp leading up to the HBM pulse which prevented the clamps from turning on.
{"title":"Voltages before and after HBM stress and their effect on dynamically triggered power supply clamps","authors":"R. Ashton, B. Weir, G. Weiss, T. Meuse","doi":"10.1109/EOSESD.2004.5272616","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272616","url":null,"abstract":"HBM and TLP measurements on dynamically triggered CMOS power supply clamps were found to be inconsistent for low leakage clamps. The failures at low HBM voltage were found to be due to a voltage ramp leading up to the HBM pulse which prevented the clamps from turning on.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132811906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272811
E. Grund, R. Gauthier
Very fast transmission line pulse (VF-TLP) systems described in the literature are time domain reflection (VF-TDR) configurations. Using other TLP configurations, VF-TLP systems can provide new capabilities. A wafer level Kelvin probe system was derived from VF-time domain transmission (VF-TDT). A test fixture board (TFB) using VF-time domain reflection and transmission (VF-TDRT) enables VF-TLP package level testing.
{"title":"VF-TLP systems using TDT and TDRT for kelvin wafer measurements and package level testing","authors":"E. Grund, R. Gauthier","doi":"10.1109/EOSESD.2004.5272811","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272811","url":null,"abstract":"Very fast transmission line pulse (VF-TLP) systems described in the literature are time domain reflection (VF-TDR) configurations. Using other TLP configurations, VF-TLP systems can provide new capabilities. A wafer level Kelvin probe system was derived from VF-time domain transmission (VF-TDT). A test fixture board (TFB) using VF-time domain reflection and transmission (VF-TDRT) enables VF-TLP package level testing.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"47 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116401623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272612
D. Swenson
Setting up an ESD Control Program is easy with ANSI/ESD S20.20 as the guide. Understanding the requirements of a standardized ESD Control Program is not a difficult task with a bit of study. Verification that the program is continuously in compliance is the major challenge today and requires the most effort. A verification plan is an important administrative component of a certifiable ESD Control Program.
{"title":"Compliance verification: The critical component of a certified ANSI/ESD S20.20 ESD control program plan","authors":"D. Swenson","doi":"10.1109/EOSESD.2004.5272612","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272612","url":null,"abstract":"Setting up an ESD Control Program is easy with ANSI/ESD S20.20 as the guide. Understanding the requirements of a standardized ESD Control Program is not a difficult task with a bit of study. Verification that the program is continuously in compliance is the major challenge today and requires the most effort. A verification plan is an important administrative component of a certifiable ESD Control Program.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130451613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272633
S. Voldman, E. Gebreselasie
As the faster transistors are produced in BiCMOS SiGe technology, low voltage trigger ESD networks will be required to achieve good ESD protection. Diode-configured SiGe HBT trigger elements are used in a SiGe C HBT power clamp network in a 200/285 GHz fT/fMAX silicon germanium heterojunction bipolar transistor (HBT) technology in a 0.13-propm CMOS technology base.
由于更快的晶体管是用BiCMOS SiGe技术生产的，因此需要低压触发ESD网络来实现良好的ESD保护。二极管配置的SiGe HBT触发元件用于SiGe C HBT电源钳位网络，该网络采用0.13 propm CMOS技术基础上的200/285 GHz fT/fMAX硅锗异质结双极晶体管(HBT)技术。
{"title":"Low-voltage diode-configured sige:C HBT triggered ESD power clamps using a raised extrinsic base 200/285 GHz (fT/fMAX) SiGe:C HBT device","authors":"S. Voldman, E. Gebreselasie","doi":"10.1109/EOSESD.2004.5272633","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272633","url":null,"abstract":"As the faster transistors are produced in BiCMOS SiGe technology, low voltage trigger ESD networks will be required to achieve good ESD protection. Diode-configured SiGe HBT trigger elements are used in a SiGe C HBT power clamp network in a 200/285 GHz fT/fMAX silicon germanium heterojunction bipolar transistor (HBT) technology in a 0.13-propm CMOS technology base.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124439461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272640
M. Ker, B. Kuo
Large electrostatic discharge (ESD) protection devices close to the I/O pins, beneficial for ESD protection, have an adverse effect on the performance of broadband RF circuits for impedance mismatch and bandwidth degradation. A new proposed ESD protection structure, pi-model distributed ESD (pi-DESD) protection circuit, composed of one pair of ESD devices near the I/O pin, the other pair close to the core circuit, and a coplanar waveguide with under-grounded shield (CPWG) connecting these two pairs, can successfully achieve both excellent ESD robustness and good broadband RF performance. Cooperating with the active power-rail ESD clamp circuit, the experimental chip in a 0.25-mum CMOS process can sustain the human-body-model (HBM) ESD stress of 8 kV.
靠近I/O引脚的大型静电放电(ESD)保护装置有利于ESD保护，但会导致阻抗失配和带宽退化，对宽带射频电路的性能产生不利影响。提出了一种新的ESD保护结构，即pi型分布式ESD (pi-DESD)保护电路，该电路由一对靠近I/O引脚的ESD器件组成，另一对靠近核心电路，并用带接地屏蔽(CPWG)的共面波导将这两对器件连接起来，可以成功地实现优异的ESD稳健性和良好的宽带射频性能。实验芯片配合有源电源轨ESD箝位电路，在0.25 μ m CMOS工艺下可承受8 kV的人体模型ESD应力。
{"title":"Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme","authors":"M. Ker, B. Kuo","doi":"10.1109/EOSESD.2004.5272640","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272640","url":null,"abstract":"Large electrostatic discharge (ESD) protection devices close to the I/O pins, beneficial for ESD protection, have an adverse effect on the performance of broadband RF circuits for impedance mismatch and bandwidth degradation. A new proposed ESD protection structure, pi-model distributed ESD (pi-DESD) protection circuit, composed of one pair of ESD devices near the I/O pin, the other pair close to the core circuit, and a coplanar waveguide with under-grounded shield (CPWG) connecting these two pairs, can successfully achieve both excellent ESD robustness and good broadband RF performance. Cooperating with the active power-rail ESD clamp circuit, the experimental chip in a 0.25-mum CMOS process can sustain the human-body-model (HBM) ESD stress of 8 kV.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129958066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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