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2004 Electrical Overstress/Electrostatic Discharge Symposium最新文献

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CDM failure modes in a 130nm ASIC technology 130nm ASIC技术中的CDM失效模式
Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272610
C. Brennan, J. Sloan, D. Picozzi
CDM failures in I/O cells in a 130 nm CMOS ASIC technology are studied. Most failures occurred in internal circuits that were not connected to chip pads. The failures correlate to the I/O power supply network resistance at the I/O cells. Failure modes include gate oxide ruptures on internal nodes driven by active circuits.
研究了130nm CMOS ASIC工艺中I/O电池的CDM失效。大多数故障发生在没有连接到芯片衬垫的内部电路中。故障与I/O单元的I/O电源网络电阻有关。失效模式包括由有源电路驱动的内部节点栅氧化物断裂。
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引用次数: 25
ESD design automation for a 90nm ASIC design system 用于90nm ASIC设计系统的ESD设计自动化
Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272614
C. Brennan, J. Kozhaya, R. Proctor, J. Sloan, Shunhua Chang, J. Sundquist, T. Lowe
Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.
描述了用于ESD的设计工具,可确保在大批量、高度自动化的ASIC设计系统中,在单元和芯片级别提供强大的保护。有三个主要组件:ESD的设计规则检查(DRC);提取网表的瞬态CDM模拟;并分析了芯片级电源的网络电阻。
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引用次数: 13
Humidity effects on laminated ESD work surface resistance and charge dissipation properties 湿度对层积静电工作面电阻和电荷耗散性能的影响
Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272606
J. Brodbeck, B. Grunden
Electrostatic discharge (ESD) laminated work surface materials developed during a USAF SBIR project are compared with commercial ESD laminates at five levels of relative humidity. The data shows no correlation between laminate's resistance measurements and their ability to dissipate a charge. Available laminates showed a dependence on higher levels of humidity to function well.
在美国空军SBIR项目期间开发的静电放电(ESD)层压工作表面材料与商业静电放电层压材料在五个相对湿度水平下进行了比较。数据显示层压板的电阻测量值和它们的耗散电荷的能力之间没有相关性。可用的层压板显示出对较高湿度水平的依赖才能发挥良好的作用。
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引用次数: 2
Breakdown behavior of TMR head in ESD transients TMR磁头在ESD瞬态中的击穿行为
Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272588
Zhao-Yu Teng, M. Mo, W. Li, Min-Bing Wong, S. Chou
HBM and D-CDM breakdown testing were preformed on the latest TMR heads of different resistance. Pspice simulations were conducted for individual TMR heads based on their actual failure voltage at HBM and D-CDM, in an attempt to investigate damage current through TMR barrier, as well as voltage across TMR barrier. Results show that in short transient test-HBM and DCDM, damage current threshold (through TMR barrier) is inversely proportional to TMR resistance, while damaging current density threshold sigmah is a constant in each transient model.
在不同电阻的最新TMR磁头上进行HBM和D-CDM击穿试验。基于TMR磁头在HBM和D-CDM下的实际失效电压,对单个TMR磁头进行了Pspice模拟,试图研究通过TMR势垒的损伤电流,以及穿过TMR势垒的电压。结果表明,在短瞬态测试- hbm和DCDM中,损伤电流阈值(通过TMR势垒)与TMR电阻成反比,而损伤电流密度阈值sigmah在各暂态模型中均为常数。
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引用次数: 3
Implementation of 60V tolerant dual direction ESD protection in 5V BiCMOS process for automotive application 在汽车应用的5V BiCMOS工艺中实现60V容限双向ESD保护
Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272623
V. Vashchenko, W. Kindt, M. ter Beek, P. Hopper
A dual-direction ESD protection approach is applied to the problem of 60 V tolerant on-chip protection of the thin film resistors in automotive application circuits realized in 5 V BiCMOS process. A novel method for increasing the breakdown voltage of a blocked N-isolation layer is proposed and validated using process and device numerical simulation followed by experimental measurements.
针对汽车应用电路中薄膜电阻器的60 V容限片上保护问题,提出了一种双向ESD保护方法。提出了一种提高阻塞n隔离层击穿电压的新方法,并通过工艺和器件数值模拟以及实验测量进行了验证。
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引用次数: 14
Transmission line pulse test methods, test techniques and characterization of low capacitance voltage suppression device for system level electrostatic discharge compliance 传输线脉冲试验方法、试验技术及低电容电压抑制装置对系统级静电放电的符合性
Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272624
K. Shrier, T. Truong, J. Felps
Voltage suppression devices are needed in electronic systems to prevent damage to electrical components from electrical overstress (EOS) and electrostatic discharge (ESD) events. A low capacitance, polymer voltage-suppressor (PVS) device is evaluated using various testing techniques that combine transmission line pulse (TLP) test system, direct discharge HBM, and a system-level ESD gun. Additionally, test methods for integrating PVS devices for system-level ESD protection of cell phone GaAs radio frequency (RF) switches and Gigabit Ethernet server semiconductors will be shown. Our work demonstrates the need for integration of device-level and system-level test methodologies for correlation between component ESD survivability and system-level ESD concerns.
在电子系统中需要电压抑制装置,以防止电气过应力(EOS)和静电放电(ESD)事件对电气元件的损坏。采用多种测试技术,结合传输线脉冲(TLP)测试系统、直接放电HBM和系统级ESD枪,对低电容聚合物电压抑制器(PVS)进行了评估。此外,还将展示集成用于手机GaAs射频(RF)开关和千兆以太网服务器半导体的系统级ESD保护的PVS器件的测试方法。我们的工作表明,需要集成器件级和系统级测试方法,以实现组件ESD生存能力和系统级ESD关注点之间的相关性。
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引用次数: 12
The effect of high pin-count ESD tester parasitics on transiently triggered ESD clamps 高引脚数ESD测试仪寄生对瞬态触发ESD钳位的影响
Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272619
H. Kunz, R. Steinhoff, C. Duvvury, G. Boselli, L. Ting
Conflicting HBM ESD results are presented for several ESD testers/test-configurations, all of which pass the present tester specifications. The discrepancy is attributed to parasitic capacitance, which can deactivate the dV/dt-detection of an ESD circuit. An unexpectedly large (>1 nF) effective parallel capacitance is found by summing tester relay capacitances of unstressed pins, connected through on-chip current paths, while considering the Miller effect. An ESD strike between two pins and the symmetric "reverse-pin, reverse-polarity" strike are shown to be nonequivalent due to a different set of on-chip current paths.
冲突的HBM ESD结果出现在几个ESD测试仪/测试配置中,所有这些都通过了当前的测试仪规范。这种差异归因于寄生电容,它可以使ESD电路的dV/dt检测失效。在考虑米勒效应的同时,通过片上电流路径连接的无应力引脚的测试器继电器电容相加,发现了一个意想不到的大(>1 nF)有效并联电容。两个引脚之间的ESD冲击和对称的“反向引脚,反极性”冲击由于片上电流路径的不同而显示为不等效。
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引用次数: 9
Soft ESD phenomena in GMR heads in the HDD manufacturing process 硬盘制造过程中GMR磁头的软静电现象
Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272644
Y. Mizoh, T. Nakano, K. Tagashira, K. Nakamura, T. Suzuki
GMR heads used for hard disk drives (HDD) are very sensitive to ESD. A kind of ESD damage makes a soft magnetic degradation of head performance with time. We report examples of head degradation modes by ESD damage and other damage modes as head Scratch damage, electro migration effects and corrosion of GMR stack, which are usually difficult to be distinguished explicitly by QST and Spinstand measurement test.
用于硬盘驱动器(HDD)的GMR磁头对ESD非常敏感。随着时间的推移,磁头的软磁性能下降是一种ESD损伤。我们报告了静电放电损伤的磁头退化模式以及其他损伤模式,如磁头划伤、电迁移效应和GMR堆腐蚀,这些通常难以通过QST和Spinstand测量测试明确区分。
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引用次数: 11
Electromagnetic field induced degradation of magnetic recording heads in a GTEM cell 电磁场诱导GTEM电池中磁头的退化
Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272647
A. Wallash, L. Baril, V. Kraz, T. Gurga
A gigahertz transverse electromagnetic mode (GTEM) cell was used to apply a controlled RF electric field to magnetic recording assemblies. The resistance and magnetic properties of the giant magnetoresistive (GMR) and tunneling MR (TMR) sensors were measured before and after exposure to the electric field. No degradation in GMR sensor properties was observed for pulsed field strengths up to 40 V/m for the standard assembly configuration. However, severe resistance and magnetic damage was observed when an additional 7 cm long wire was attached to the input of the GMR sensor. It is concluded that it is important to understand and measure the radiated immunity failure level for extremely ESD sensitive devices like magnetic recording assemblies.
采用千兆赫横向电磁模式(GTEM)单元对磁记录组件施加可控射频电场。测量了巨磁阻(GMR)和隧道磁阻(TMR)传感器在电场作用前后的电阻和磁性能。对于标准装配配置,脉冲场强高达40 V/m时,未观察到GMR传感器性能的退化。然而,当在GMR传感器的输入端附加一根7厘米长的电线时,观察到严重的电阻和磁损伤。因此,了解和测量磁记录组件等ESD敏感器件的辐射抗扰度失效水平是非常重要的。
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引用次数: 4
Distributed gate ESD network architecture for inter-power domain signals 功率域间信号的分布式栅极ESD网络架构
Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272602
E. Worley
This paper examines the issue of transmitting signals between circuits of different power domains within an IC and the ESD sensitivity of the receiving logic's oxide in advanced processes. It is also shown that the ESD stress voltage appearing across a receiving gate's oxide can be distributed among several inverters. Also, design of interface attenuation networks that allow large voltage drops between domains for both CDM and HBM tests will be examined.
本文研究了在集成电路内不同功率域的电路之间传输信号的问题,以及高级工艺中接收逻辑氧化物的ESD灵敏度。结果还表明,在接收栅极氧化物上出现的ESD应力电压可以分布在多个逆变器之间。此外,还将研究允许CDM和HBM测试的域之间大电压降的接口衰减网络的设计。
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引用次数: 35
期刊
2004 Electrical Overstress/Electrostatic Discharge Symposium
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