Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272610
C. Brennan, J. Sloan, D. Picozzi
CDM failures in I/O cells in a 130 nm CMOS ASIC technology are studied. Most failures occurred in internal circuits that were not connected to chip pads. The failures correlate to the I/O power supply network resistance at the I/O cells. Failure modes include gate oxide ruptures on internal nodes driven by active circuits.
{"title":"CDM failure modes in a 130nm ASIC technology","authors":"C. Brennan, J. Sloan, D. Picozzi","doi":"10.1109/EOSESD.2004.5272610","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272610","url":null,"abstract":"CDM failures in I/O cells in a 130 nm CMOS ASIC technology are studied. Most failures occurred in internal circuits that were not connected to chip pads. The failures correlate to the I/O power supply network resistance at the I/O cells. Failure modes include gate oxide ruptures on internal nodes driven by active circuits.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116982996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272614
C. Brennan, J. Kozhaya, R. Proctor, J. Sloan, Shunhua Chang, J. Sundquist, T. Lowe
Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.
{"title":"ESD design automation for a 90nm ASIC design system","authors":"C. Brennan, J. Kozhaya, R. Proctor, J. Sloan, Shunhua Chang, J. Sundquist, T. Lowe","doi":"10.1109/EOSESD.2004.5272614","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272614","url":null,"abstract":"Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116569038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272606
J. Brodbeck, B. Grunden
Electrostatic discharge (ESD) laminated work surface materials developed during a USAF SBIR project are compared with commercial ESD laminates at five levels of relative humidity. The data shows no correlation between laminate's resistance measurements and their ability to dissipate a charge. Available laminates showed a dependence on higher levels of humidity to function well.
{"title":"Humidity effects on laminated ESD work surface resistance and charge dissipation properties","authors":"J. Brodbeck, B. Grunden","doi":"10.1109/EOSESD.2004.5272606","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272606","url":null,"abstract":"Electrostatic discharge (ESD) laminated work surface materials developed during a USAF SBIR project are compared with commercial ESD laminates at five levels of relative humidity. The data shows no correlation between laminate's resistance measurements and their ability to dissipate a charge. Available laminates showed a dependence on higher levels of humidity to function well.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134348256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272588
Zhao-Yu Teng, M. Mo, W. Li, Min-Bing Wong, S. Chou
HBM and D-CDM breakdown testing were preformed on the latest TMR heads of different resistance. Pspice simulations were conducted for individual TMR heads based on their actual failure voltage at HBM and D-CDM, in an attempt to investigate damage current through TMR barrier, as well as voltage across TMR barrier. Results show that in short transient test-HBM and DCDM, damage current threshold (through TMR barrier) is inversely proportional to TMR resistance, while damaging current density threshold sigmah is a constant in each transient model.
{"title":"Breakdown behavior of TMR head in ESD transients","authors":"Zhao-Yu Teng, M. Mo, W. Li, Min-Bing Wong, S. Chou","doi":"10.1109/EOSESD.2004.5272588","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272588","url":null,"abstract":"HBM and D-CDM breakdown testing were preformed on the latest TMR heads of different resistance. Pspice simulations were conducted for individual TMR heads based on their actual failure voltage at HBM and D-CDM, in an attempt to investigate damage current through TMR barrier, as well as voltage across TMR barrier. Results show that in short transient test-HBM and DCDM, damage current threshold (through TMR barrier) is inversely proportional to TMR resistance, while damaging current density threshold sigmah is a constant in each transient model.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134464695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272623
V. Vashchenko, W. Kindt, M. ter Beek, P. Hopper
A dual-direction ESD protection approach is applied to the problem of 60 V tolerant on-chip protection of the thin film resistors in automotive application circuits realized in 5 V BiCMOS process. A novel method for increasing the breakdown voltage of a blocked N-isolation layer is proposed and validated using process and device numerical simulation followed by experimental measurements.
{"title":"Implementation of 60V tolerant dual direction ESD protection in 5V BiCMOS process for automotive application","authors":"V. Vashchenko, W. Kindt, M. ter Beek, P. Hopper","doi":"10.1109/EOSESD.2004.5272623","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272623","url":null,"abstract":"A dual-direction ESD protection approach is applied to the problem of 60 V tolerant on-chip protection of the thin film resistors in automotive application circuits realized in 5 V BiCMOS process. A novel method for increasing the breakdown voltage of a blocked N-isolation layer is proposed and validated using process and device numerical simulation followed by experimental measurements.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124002620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272624
K. Shrier, T. Truong, J. Felps
Voltage suppression devices are needed in electronic systems to prevent damage to electrical components from electrical overstress (EOS) and electrostatic discharge (ESD) events. A low capacitance, polymer voltage-suppressor (PVS) device is evaluated using various testing techniques that combine transmission line pulse (TLP) test system, direct discharge HBM, and a system-level ESD gun. Additionally, test methods for integrating PVS devices for system-level ESD protection of cell phone GaAs radio frequency (RF) switches and Gigabit Ethernet server semiconductors will be shown. Our work demonstrates the need for integration of device-level and system-level test methodologies for correlation between component ESD survivability and system-level ESD concerns.
{"title":"Transmission line pulse test methods, test techniques and characterization of low capacitance voltage suppression device for system level electrostatic discharge compliance","authors":"K. Shrier, T. Truong, J. Felps","doi":"10.1109/EOSESD.2004.5272624","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272624","url":null,"abstract":"Voltage suppression devices are needed in electronic systems to prevent damage to electrical components from electrical overstress (EOS) and electrostatic discharge (ESD) events. A low capacitance, polymer voltage-suppressor (PVS) device is evaluated using various testing techniques that combine transmission line pulse (TLP) test system, direct discharge HBM, and a system-level ESD gun. Additionally, test methods for integrating PVS devices for system-level ESD protection of cell phone GaAs radio frequency (RF) switches and Gigabit Ethernet server semiconductors will be shown. Our work demonstrates the need for integration of device-level and system-level test methodologies for correlation between component ESD survivability and system-level ESD concerns.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"326 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120840182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272619
H. Kunz, R. Steinhoff, C. Duvvury, G. Boselli, L. Ting
Conflicting HBM ESD results are presented for several ESD testers/test-configurations, all of which pass the present tester specifications. The discrepancy is attributed to parasitic capacitance, which can deactivate the dV/dt-detection of an ESD circuit. An unexpectedly large (>1 nF) effective parallel capacitance is found by summing tester relay capacitances of unstressed pins, connected through on-chip current paths, while considering the Miller effect. An ESD strike between two pins and the symmetric "reverse-pin, reverse-polarity" strike are shown to be nonequivalent due to a different set of on-chip current paths.
{"title":"The effect of high pin-count ESD tester parasitics on transiently triggered ESD clamps","authors":"H. Kunz, R. Steinhoff, C. Duvvury, G. Boselli, L. Ting","doi":"10.1109/EOSESD.2004.5272619","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272619","url":null,"abstract":"Conflicting HBM ESD results are presented for several ESD testers/test-configurations, all of which pass the present tester specifications. The discrepancy is attributed to parasitic capacitance, which can deactivate the dV/dt-detection of an ESD circuit. An unexpectedly large (>1 nF) effective parallel capacitance is found by summing tester relay capacitances of unstressed pins, connected through on-chip current paths, while considering the Miller effect. An ESD strike between two pins and the symmetric \"reverse-pin, reverse-polarity\" strike are shown to be nonequivalent due to a different set of on-chip current paths.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125517968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272644
Y. Mizoh, T. Nakano, K. Tagashira, K. Nakamura, T. Suzuki
GMR heads used for hard disk drives (HDD) are very sensitive to ESD. A kind of ESD damage makes a soft magnetic degradation of head performance with time. We report examples of head degradation modes by ESD damage and other damage modes as head Scratch damage, electro migration effects and corrosion of GMR stack, which are usually difficult to be distinguished explicitly by QST and Spinstand measurement test.
{"title":"Soft ESD phenomena in GMR heads in the HDD manufacturing process","authors":"Y. Mizoh, T. Nakano, K. Tagashira, K. Nakamura, T. Suzuki","doi":"10.1109/EOSESD.2004.5272644","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272644","url":null,"abstract":"GMR heads used for hard disk drives (HDD) are very sensitive to ESD. A kind of ESD damage makes a soft magnetic degradation of head performance with time. We report examples of head degradation modes by ESD damage and other damage modes as head Scratch damage, electro migration effects and corrosion of GMR stack, which are usually difficult to be distinguished explicitly by QST and Spinstand measurement test.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128008483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272647
A. Wallash, L. Baril, V. Kraz, T. Gurga
A gigahertz transverse electromagnetic mode (GTEM) cell was used to apply a controlled RF electric field to magnetic recording assemblies. The resistance and magnetic properties of the giant magnetoresistive (GMR) and tunneling MR (TMR) sensors were measured before and after exposure to the electric field. No degradation in GMR sensor properties was observed for pulsed field strengths up to 40 V/m for the standard assembly configuration. However, severe resistance and magnetic damage was observed when an additional 7 cm long wire was attached to the input of the GMR sensor. It is concluded that it is important to understand and measure the radiated immunity failure level for extremely ESD sensitive devices like magnetic recording assemblies.
{"title":"Electromagnetic field induced degradation of magnetic recording heads in a GTEM cell","authors":"A. Wallash, L. Baril, V. Kraz, T. Gurga","doi":"10.1109/EOSESD.2004.5272647","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272647","url":null,"abstract":"A gigahertz transverse electromagnetic mode (GTEM) cell was used to apply a controlled RF electric field to magnetic recording assemblies. The resistance and magnetic properties of the giant magnetoresistive (GMR) and tunneling MR (TMR) sensors were measured before and after exposure to the electric field. No degradation in GMR sensor properties was observed for pulsed field strengths up to 40 V/m for the standard assembly configuration. However, severe resistance and magnetic damage was observed when an additional 7 cm long wire was attached to the input of the GMR sensor. It is concluded that it is important to understand and measure the radiated immunity failure level for extremely ESD sensitive devices like magnetic recording assemblies.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123507496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272602
E. Worley
This paper examines the issue of transmitting signals between circuits of different power domains within an IC and the ESD sensitivity of the receiving logic's oxide in advanced processes. It is also shown that the ESD stress voltage appearing across a receiving gate's oxide can be distributed among several inverters. Also, design of interface attenuation networks that allow large voltage drops between domains for both CDM and HBM tests will be examined.
{"title":"Distributed gate ESD network architecture for inter-power domain signals","authors":"E. Worley","doi":"10.1109/EOSESD.2004.5272602","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272602","url":null,"abstract":"This paper examines the issue of transmitting signals between circuits of different power domains within an IC and the ESD sensitivity of the receiving logic's oxide in advanced processes. It is also shown that the ESD stress voltage appearing across a receiving gate's oxide can be distributed among several inverters. Also, design of interface attenuation networks that allow large voltage drops between domains for both CDM and HBM tests will be examined.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116683099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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