Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272632
M. Honda
Induced ESD happened at a small air gap on the floating metal object during electrostatic fields in changing. At the ESD, ultra short impulsive fields are emanated from the metal object. Strength and polarity of the impulsive fields are experimentally analyzed. This radiated impulsive field may strong contribute to GMR head damage.
{"title":"Induced ESD on metal object with a small air gap","authors":"M. Honda","doi":"10.1109/EOSESD.2004.5272632","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272632","url":null,"abstract":"Induced ESD happened at a small air gap on the floating metal object during electrostatic fields in changing. At the ESD, ultra short impulsive fields are emanated from the metal object. Strength and polarity of the impulsive fields are experimentally analyzed. This radiated impulsive field may strong contribute to GMR head damage.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133665050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272591
T. Maloney, S. Poon
A quarter-wave directional coupler plus ordinary transmission line pulsing (TLP) can create short pulses resembling charged device model (CDM) ESD. Pulse rise time often relates to the coupler's center frequency and can thereby be stabilized. It is shown that for a voltage step of a given size, yet with arbitrary waveform, the net amount of coupled charge (the charge packet) is constant and depends only on fixed coupler parameters. This property of Z-matched coupled lines has wider implications. High voltage couplers can be made from coaxial cable or from stripline. Some of these designs are described, tested, and compared to computer simulations of coupled lines.
{"title":"Using coupled transmission lines to generate impedance-matched pulses resembling charged device model ESD","authors":"T. Maloney, S. Poon","doi":"10.1109/EOSESD.2004.5272591","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272591","url":null,"abstract":"A quarter-wave directional coupler plus ordinary transmission line pulsing (TLP) can create short pulses resembling charged device model (CDM) ESD. Pulse rise time often relates to the coupler's center frequency and can thereby be stabilized. It is shown that for a voltage step of a given size, yet with arbitrary waveform, the net amount of coupled charge (the charge packet) is constant and depends only on fixed coupler parameters. This property of Z-matched coupled lines has wider implications. High voltage couplers can be made from coaxial cable or from stripline. Some of these designs are described, tested, and compared to computer simulations of coupled lines.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"704 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122964279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272617
I-Cheng Lin, Chuan-Jane Chao, M. Ker, J. Tseng, Chung-Ti Hsu, L. Leu, Yu-Lin Chen, Chia-Ku Tsai, Ren-Wen Huang
An EOS-like latchup failure occurred in a high-voltage IC product during latchup test and was identified within ESD diodes themselves. A parasitic npn bipolar formed by ESD protection diodes was trigger-activated and produced large current to result in EOS failure. This was verified by electrical measurement from TLP and curve-tracer as well as physical failure analysis. Corresponding layout solutions were proposed and solved this anomalous latchup failure successfully. Therefore ESD protection diode should be laid carefully for true latchup-robust design.
{"title":"Latchup test-induced failure within ESD protection diodes in a high-voltage CMOS IC product","authors":"I-Cheng Lin, Chuan-Jane Chao, M. Ker, J. Tseng, Chung-Ti Hsu, L. Leu, Yu-Lin Chen, Chia-Ku Tsai, Ren-Wen Huang","doi":"10.1109/EOSESD.2004.5272617","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272617","url":null,"abstract":"An EOS-like latchup failure occurred in a high-voltage IC product during latchup test and was identified within ESD diodes themselves. A parasitic npn bipolar formed by ESD protection diodes was trigger-activated and produced large current to result in EOS failure. This was verified by electrical measurement from TLP and curve-tracer as well as physical failure analysis. Corresponding layout solutions were proposed and solved this anomalous latchup failure successfully. Therefore ESD protection diode should be laid carefully for true latchup-robust design.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132949696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272636
Yintat Ma, Guann-Pyng Li
This paper presents design considerations and implementation of InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD protection circuits. The inherit benefits of both bandwidth and ESD robustness of distributed amplifiers are first compared to those of single-ended feedback amplifiers. Next, novel on-chip ESD protection circuits are introduced, featuring low capacitance loading for wide bandwidth, low leakage, and good linearity under high RF power. This paper discusses the principle of operation and performance of the ESD protection circuits, and the RF loading to the distributed amplifier. The RF performance and ESD robustness of the distributed amplifier are also discussed.
介绍了一种具有紧凑型ESD保护电路的InGaP/GaAs HBT dc - 20ghz分布式放大器的设计思路和实现方法。首先比较了分布式放大器与单端反馈放大器在带宽和ESD鲁棒性方面的继承优势。其次，介绍了一种新型片上ESD保护电路，该电路具有低电容负载、宽带宽、低泄漏和高射频功率下良好的线性度。本文讨论了ESD保护电路的工作原理和性能，以及分布式放大器的射频负载。讨论了分布式放大器的射频性能和ESD鲁棒性。
{"title":"InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD protection circuits","authors":"Yintat Ma, Guann-Pyng Li","doi":"10.1109/EOSESD.2004.5272636","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272636","url":null,"abstract":"This paper presents design considerations and implementation of InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD protection circuits. The inherit benefits of both bandwidth and ESD robustness of distributed amplifiers are first compared to those of single-ended feedback amplifiers. Next, novel on-chip ESD protection circuits are introduced, featuring low capacitance loading for wide bandwidth, low leakage, and good linearity under high RF power. This paper discusses the principle of operation and performance of the ESD protection circuits, and the RF loading to the distributed amplifier. The RF performance and ESD robustness of the distributed amplifier are also discussed.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129531015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272607
B. Yap, C. Newberg
DC resistance testing using standard commercial electrodes has been a simple, standard way adopted by many for their evaluation of dissipative materials. However, we have observed that this test is ineffective for the detection of ldquohot spotsrdquo arising from non-homogeneities in the micro-structures of some dissipative materials. We have employed a combination of tests using a direct sharp tip probe for both resistance and charge decay measurements and a small non-contact electrostatic voltmeter for localized surface voltage measurements. These combined tests furnish better information about ldquohot spotrdquo characteristics and their formation in dissipative materials. We wish to share the test techniques, the results and the analysis of our present study.
{"title":"Study of “hot spots” arising from non-homogeneity in the micro-structures of dissipative materials","authors":"B. Yap, C. Newberg","doi":"10.1109/EOSESD.2004.5272607","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272607","url":null,"abstract":"DC resistance testing using standard commercial electrodes has been a simple, standard way adopted by many for their evaluation of dissipative materials. However, we have observed that this test is ineffective for the detection of ldquohot spotsrdquo arising from non-homogeneities in the micro-structures of some dissipative materials. We have employed a combination of tests using a direct sharp tip probe for both resistance and charge decay measurements and a small non-contact electrostatic voltmeter for localized surface voltage measurements. These combined tests furnish better information about ldquohot spotrdquo characteristics and their formation in dissipative materials. We wish to share the test techniques, the results and the analysis of our present study.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115614363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272615
N. Guitard, D. Trémouilles, Stéphane Alves, M. Bafleur, Felix Beaudoin, P. Perdu, A. Wislez
A dedicated test vehicle was designed to study the impact of ESD induced latent defects on digital and analog CMOS circuits. Both CDM and TLP stresses were applied to these circuits through a specific pad which allows stressing the circuit core. Both electrical characterization and non-destructive failure analysis were performed to locate the induced defect. For digital circuits, functionality is not affected although the IDDQ quiescent current increased. However, after burn-in and storage, it was observed that the IDDQ current significantly increased suggesting that the circuit lifetime is degraded. In contrast, even at very low stress level, the analog circuit exhibits a dramatic offset degradation and no recovery is observed after burn-in.
{"title":"ESD induced latent defects in CMOS ICs and reliability impact","authors":"N. Guitard, D. Trémouilles, Stéphane Alves, M. Bafleur, Felix Beaudoin, P. Perdu, A. Wislez","doi":"10.1109/EOSESD.2004.5272615","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272615","url":null,"abstract":"A dedicated test vehicle was designed to study the impact of ESD induced latent defects on digital and analog CMOS circuits. Both CDM and TLP stresses were applied to these circuits through a specific pad which allows stressing the circuit core. Both electrical characterization and non-destructive failure analysis were performed to locate the induced defect. For digital circuits, functionality is not affected although the IDDQ quiescent current increased. However, after burn-in and storage, it was observed that the IDDQ current significantly increased suggesting that the circuit lifetime is degraded. In contrast, even at very low stress level, the analog circuit exhibits a dramatic offset degradation and no recovery is observed after burn-in.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130366644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272813
R. Rodrigo, D. Bellmore, J. Diep, T. Jarrett, N. Jonassen, C. Newberg, D. Parkin, D. Pritchard, J. Salisbury, A. Steinman, J. Turangan
Air ionizers are used during the fabrication and assembly of very small components and sub assemblies that are static sensitive. The plate of a standard charged plate monitor (CPM) is relatively large in comparison. Questions have arisen about the relevancy of CPM test results with respect to very small components. The Ionization Committee of the ESD Association performed tests to investigate this relationship.
{"title":"CPM study: Discharge time and offset voltage, their relationship to plate geometry","authors":"R. Rodrigo, D. Bellmore, J. Diep, T. Jarrett, N. Jonassen, C. Newberg, D. Parkin, D. Pritchard, J. Salisbury, A. Steinman, J. Turangan","doi":"10.1109/EOSESD.2004.5272813","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272813","url":null,"abstract":"Air ionizers are used during the fabrication and assembly of very small components and sub assemblies that are static sensitive. The plate of a standard charged plate monitor (CPM) is relatively large in comparison. Questions have arisen about the relevancy of CPM test results with respect to very small components. The Ionization Committee of the ESD Association performed tests to investigate this relationship.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129895104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272630
N. Shimoyama, M. Tanno, S. Shigematsu, H. Morimura, Y. Okazaki, K. Machida
We evaluated the electrostatic discharge (ESD) hardness for some kinds of capacitive fingerprint sensor LSIs. In contact discharge tests, our sensor with the GND wall structure and another sensor with a GND demonstrated of ESD failure voltage above plusmn8 kV. On the other hand, in air discharge tests, ESD tolerance of our GND wall structure was over plusmn 20 kV, whereas that of the other GND structure was below plusmn 12 kV. It is evident from our findings that ESD immunity in the sensor LSIs obviously depends on the GND structure and our sensor LSI with the GND wall has the highest ESD tolerance.
{"title":"Evaluation of ESD hardness for fingerprint sensor LSIs","authors":"N. Shimoyama, M. Tanno, S. Shigematsu, H. Morimura, Y. Okazaki, K. Machida","doi":"10.1109/EOSESD.2004.5272630","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272630","url":null,"abstract":"We evaluated the electrostatic discharge (ESD) hardness for some kinds of capacitive fingerprint sensor LSIs. In contact discharge tests, our sensor with the GND wall structure and another sensor with a GND demonstrated of ESD failure voltage above plusmn8 kV. On the other hand, in air discharge tests, ESD tolerance of our GND wall structure was over plusmn 20 kV, whereas that of the other GND structure was below plusmn 12 kV. It is evident from our findings that ESD immunity in the sensor LSIs obviously depends on the GND structure and our sensor LSI with the GND wall has the highest ESD tolerance.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123752460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272620
H. Hayashi, T. Kuroda, K. Kato, K. Fukuda, S. Baba, Y. Fukuda
In this paper, we propose a new ESD protection design methodology using a mixed-mode ESD simulation that takes account of a coupling effect for both device and circuit. As a result, we can analysis the each protection unit operation and select the optimized protection circuits in prevention of ESD failure on separated power supply units by prediction of the simulation.
{"title":"ESD protection design using a mixed-mode simulation for advanced devices","authors":"H. Hayashi, T. Kuroda, K. Kato, K. Fukuda, S. Baba, Y. Fukuda","doi":"10.1109/EOSESD.2004.5272620","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272620","url":null,"abstract":"In this paper, we propose a new ESD protection design methodology using a mixed-mode ESD simulation that takes account of a coupling effect for both device and circuit. As a result, we can analysis the each protection unit operation and select the optimized protection circuits in prevention of ESD failure on separated power supply units by prediction of the simulation.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129445052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-01DOI: 10.1109/EOSESD.2004.5272639
K. Suzuki, M. Sato
Conductive and dissipative implements are used to guard extremely sensitive devices against electrostatic discharge. We developed the methods of IV characteristic, nano transient current and transient resistance from basic theory and evaluated the implements. Consequently, almost all the carbon molecules mixed implements are characterized by linearity, resistance, surface potential and breakdown. Also, the suitable resistance of conductive implements can be derived from the excessive mobile charge criteria. At present, almost all the implements cannot guard devices against the charged device model event. However, the theory and methods will derive the suitable and realizable resistance for implement and device makers.
{"title":"Nano-transient current and transient resistance on the conductive or dissipative materials for extremely sensitive devices","authors":"K. Suzuki, M. Sato","doi":"10.1109/EOSESD.2004.5272639","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272639","url":null,"abstract":"Conductive and dissipative implements are used to guard extremely sensitive devices against electrostatic discharge. We developed the methods of IV characteristic, nano transient current and transient resistance from basic theory and evaluated the implements. Consequently, almost all the carbon molecules mixed implements are characterized by linearity, resistance, surface potential and breakdown. Also, the suitable resistance of conductive implements can be derived from the excessive mobile charge criteria. At present, almost all the implements cannot guard devices against the charged device model event. However, the theory and methods will derive the suitable and realizable resistance for implement and device makers.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"270 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126056312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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