Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51088
S. Duey, G. Neudeck
A new, quasi-dielectrically isolated (QDI) bipolar structure using epitaxial lateral overgrowth (ELO) is presented. A main application for QDI is in power integrated circuits, where isolation of high-power devices and low-power logic is necessary. The ELO-QDI structure uses of combination of dielectric isolation and junction isolation providing better isolation properties than junction isolation, while providing better heat dissipation than dielectric isolation. The ELO silicon was grown at a low-temperature, 950 degrees C, low-pressure, 150 torr, in a RF-heated pancake-type reactor. Fabricated transistors have gains, ideality factors, and leakage currents comparable to those of bulk-devices.<>
{"title":"A novel quasi-dielectrically isolated bipolar transistor using epitaxial lateral overgrowth","authors":"S. Duey, G. Neudeck","doi":"10.1109/BIPOL.1988.51088","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51088","url":null,"abstract":"A new, quasi-dielectrically isolated (QDI) bipolar structure using epitaxial lateral overgrowth (ELO) is presented. A main application for QDI is in power integrated circuits, where isolation of high-power devices and low-power logic is necessary. The ELO-QDI structure uses of combination of dielectric isolation and junction isolation providing better isolation properties than junction isolation, while providing better heat dissipation than dielectric isolation. The ELO silicon was grown at a low-temperature, 950 degrees C, low-pressure, 150 torr, in a RF-heated pancake-type reactor. Fabricated transistors have gains, ideality factors, and leakage currents comparable to those of bulk-devices.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128217058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51082
H.J. Chen, S. Nawaz, B.D. Urke, H. Vyas
Measured data are presented on performance of current mode logic (CML) ring oscillators at liquid nitrogen temperature. The devices and circuits were fabricated using double-poly bipolar technology. The experimental data are explained using the hybrid- pi model. CML ring oscillators were fabricated using 1.0 mu m design rules. The measured delay at LN/sub 2/ increased by a factor of 2.3 compared to that at room temperature. The increase in delay is explained by the temperature behavior of the base and load resistors.<>
{"title":"Switching characteristics of poly bipolar circuits at liquid nitrogen temperature","authors":"H.J. Chen, S. Nawaz, B.D. Urke, H. Vyas","doi":"10.1109/BIPOL.1988.51082","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51082","url":null,"abstract":"Measured data are presented on performance of current mode logic (CML) ring oscillators at liquid nitrogen temperature. The devices and circuits were fabricated using double-poly bipolar technology. The experimental data are explained using the hybrid- pi model. CML ring oscillators were fabricated using 1.0 mu m design rules. The measured delay at LN/sub 2/ increased by a factor of 2.3 compared to that at room temperature. The increase in delay is explained by the temperature behavior of the base and load resistors.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128882389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51038
B. Hwang, J. Kirchgessner, T. Bushey, S. Foertsch, J. Stipanuk, L. Marshbanks, J. Hernandez, E. Herald
A 1 K*1 bipolar emitter coupled logic (ECL) static random access memory (RAM) using a polysilicon diode loaded memory cell is realised in a single poly bipolar process technology. The use of the polysilicon diode as the load element for the memory cell is made possible by the fact that its I-V characteristics exhibit an ideality factor of two. The hold voltage for the memory cell is larger than 240 mV over a wide range of cell currents with the lower bound residing in the sub- mu A range. Results show extremely stable operation against row select sensitivity. A 1.5-ns row address access time has been obtained from the test circuit.<>
{"title":"A bipolar ECL static RAM with polysilicon diode loaded memory cell using single poly technology","authors":"B. Hwang, J. Kirchgessner, T. Bushey, S. Foertsch, J. Stipanuk, L. Marshbanks, J. Hernandez, E. Herald","doi":"10.1109/BIPOL.1988.51038","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51038","url":null,"abstract":"A 1 K*1 bipolar emitter coupled logic (ECL) static random access memory (RAM) using a polysilicon diode loaded memory cell is realised in a single poly bipolar process technology. The use of the polysilicon diode as the load element for the memory cell is made possible by the fact that its I-V characteristics exhibit an ideality factor of two. The hold voltage for the memory cell is larger than 240 mV over a wide range of cell currents with the lower bound residing in the sub- mu A range. Results show extremely stable operation against row select sensitivity. A 1.5-ns row address access time has been obtained from the test circuit.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123921190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51042
B. Pejcinovic, T. Tang, D. Navon
Static and small signal performances of Si and Si/sub 1-x/Ge/sub x/ based bipolar junction transistors (BJTs) are compared using numerical simulation. Si/sub 1-x/Ge/sub x/ BJT shows reduced turn-on voltage ( Delta V/sub BE/=0.12 V), much higher current gain h/sub fe/, up to two time higher unity current gain frequency f/sub T/, and somewhat higher maximum frequency of oscillation f/sub max/. By using Si/sub 1-x/Ge/sub x/ it is possible to reduce power dissipation in the circuit environment. Small signal current gain, as obtained by using the quasi-static approximation, is shown for the common emitter configuration.<>
{"title":"A comparison of Si and Si/sub 1-x/Ge/sub x/ based BJTs using numerical simulation","authors":"B. Pejcinovic, T. Tang, D. Navon","doi":"10.1109/BIPOL.1988.51042","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51042","url":null,"abstract":"Static and small signal performances of Si and Si/sub 1-x/Ge/sub x/ based bipolar junction transistors (BJTs) are compared using numerical simulation. Si/sub 1-x/Ge/sub x/ BJT shows reduced turn-on voltage ( Delta V/sub BE/=0.12 V), much higher current gain h/sub fe/, up to two time higher unity current gain frequency f/sub T/, and somewhat higher maximum frequency of oscillation f/sub max/. By using Si/sub 1-x/Ge/sub x/ it is possible to reduce power dissipation in the circuit environment. Small signal current gain, as obtained by using the quasi-static approximation, is shown for the common emitter configuration.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127270165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51053
P. van Wijnen, L. Smith
Small-signal high-frequency measurements of small bipolar transistors, carried out 'on wafer' up to a frequency of 18 GHz, are presented. Current gain, transconductance, and maximum power gain characteristics as a function of frequency and DC bias conditions have been obtained with accurate calibration and correction techniques. The figures of merit, f/sub t/f/sub y/, and f/sub max/, associated with these characteristics have been discussed, and a simplified analysis of the relevant time constants has been given. Simulation results with a modified Gummel/Poon model show that good high-frequency modeling can be achieved by taking into account the current dependence of the base resistance and the base transit time, and the modeling of excess phase shift. Finally the importance of modeling the distributed base-collector capacitance, which is accomplished in the Gummel/Poon model with the parameter x/sub cjc/, has been emphasized. It is very important even for frequencies well below the cutoff frequency.<>
{"title":"High frequency characterization of small geometry bipolar transistors","authors":"P. van Wijnen, L. Smith","doi":"10.1109/BIPOL.1988.51053","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51053","url":null,"abstract":"Small-signal high-frequency measurements of small bipolar transistors, carried out 'on wafer' up to a frequency of 18 GHz, are presented. Current gain, transconductance, and maximum power gain characteristics as a function of frequency and DC bias conditions have been obtained with accurate calibration and correction techniques. The figures of merit, f/sub t/f/sub y/, and f/sub max/, associated with these characteristics have been discussed, and a simplified analysis of the relevant time constants has been given. Simulation results with a modified Gummel/Poon model show that good high-frequency modeling can be achieved by taking into account the current dependence of the base resistance and the base transit time, and the modeling of excess phase shift. Finally the importance of modeling the distributed base-collector capacitance, which is accomplished in the Gummel/Poon model with the parameter x/sub cjc/, has been emphasized. It is very important even for frequencies well below the cutoff frequency.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122704560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51065
V.E. Garuts, E.O. Traa, Y.-C. S. Yu, T. Yamaguchi
A dual 4-bit analog-to-digital converter with Nyquist operation to 1.5 Gs/s and -29 dBc distortion at 1 GHz is presented. An integral digital-to-analog converter was included to observe the performance of the quantizer front end, and also to let the chip be used in a dual-rank digitizer.<>
提出了一种双4位模数转换器，其奈奎斯特工作速率为1.5 g /s，在1ghz时失真为-29 dBc。为了观察量化器前端的性能，并将该芯片应用于双阶数字化仪>中，设计了一个积分数模转换器
{"title":"A dual 4-bit, 1.5 Gs/s analog to digital converter","authors":"V.E. Garuts, E.O. Traa, Y.-C. S. Yu, T. Yamaguchi","doi":"10.1109/BIPOL.1988.51065","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51065","url":null,"abstract":"A dual 4-bit analog-to-digital converter with Nyquist operation to 1.5 Gs/s and -29 dBc distortion at 1 GHz is presented. An integral digital-to-analog converter was included to observe the performance of the quantizer front end, and also to let the chip be used in a dual-rank digitizer.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130079641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51084
C. Wu, T. Wu
Based on current-domain large-signal equivalent circuits, a new physical timing model for bipolar nonthreshold logic (NTL) circuits is developed. Through extensive comparisons with SPICE simulation results, it is found that the maximum error is 25% for the NTL inverters with different operating currents, capacitance loads, device parameters, and input excitation waveforms not deviating much from characteristic waveforms. Moreover, the consumed CPU time and memory in calculations are much less than those in full transient simulations.<>
{"title":"A new physical timing model for bipolar NTL circuits","authors":"C. Wu, T. Wu","doi":"10.1109/BIPOL.1988.51084","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51084","url":null,"abstract":"Based on current-domain large-signal equivalent circuits, a new physical timing model for bipolar nonthreshold logic (NTL) circuits is developed. Through extensive comparisons with SPICE simulation results, it is found that the maximum error is 25% for the NTL inverters with different operating currents, capacitance loads, device parameters, and input excitation waveforms not deviating much from characteristic waveforms. Moreover, the consumed CPU time and memory in calculations are much less than those in full transient simulations.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"55 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133357272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51048
T. R. Anderson
Circuit design and measured performance are described for an operational amplifier with two selectable input stages, fabricated on an analog array chip. Gain bandwidth product is 2.4 GHz, channel switching time is approximately 5 ns. The circuit was developed for specific hybrid applications and then optimized for general-purpose use as a multiplexer, or virtually any other circuit function that might be implemented with an operational amplifier.<>
{"title":"A wideband operational amplifier with two selectable input stages","authors":"T. R. Anderson","doi":"10.1109/BIPOL.1988.51048","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51048","url":null,"abstract":"Circuit design and measured performance are described for an operational amplifier with two selectable input stages, fabricated on an analog array chip. Gain bandwidth product is 2.4 GHz, channel switching time is approximately 5 ns. The circuit was developed for specific hybrid applications and then optimized for general-purpose use as a multiplexer, or virtually any other circuit function that might be implemented with an operational amplifier.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133573093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51041
G. Taylor, M. Lebby, P. Kiely, P. Cooke, A. Isabelle, T. Chang, B. Tell, D. L. Crawford, K. Brown-Goebeler, J. Simmons
The BICFET, a new form of bipolar transistor that offers superior performance for III-V bipolar integrated circuits and several unique advantages over known approaches for optoelectronic integration, is described. The BICFET does not have a base. Instead, the control (or biasing) charge is confined to the inversion channel at a heterojunction interface which is accessed by a source self-aligned to the emitter. The channel is induced by a charge sheet located in the depleted barrier section of the emitter. The mobility of the channel is high (and thus its resistance R/sub IN/ is low) because the narrow-band semiconductor at the interface is undoped. The BICFET does not have charge storage or recombination in a neutral base, and it has the potential for very high speed due its low input capacitance and the enhanced carrier velocity in the collector. The first operation of the N-channel BICFET is reported here. The base-resistance, current-gain, and input-capacitance characteristics of the BICFET are compared to those of the HBT, and BICFET is found to be an attractive structure for circumventing the problems of charge storage and carrier recombination in the HBT.<>
{"title":"Performance and advantages of BICFETs versus HBTs","authors":"G. Taylor, M. Lebby, P. Kiely, P. Cooke, A. Isabelle, T. Chang, B. Tell, D. L. Crawford, K. Brown-Goebeler, J. Simmons","doi":"10.1109/BIPOL.1988.51041","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51041","url":null,"abstract":"The BICFET, a new form of bipolar transistor that offers superior performance for III-V bipolar integrated circuits and several unique advantages over known approaches for optoelectronic integration, is described. The BICFET does not have a base. Instead, the control (or biasing) charge is confined to the inversion channel at a heterojunction interface which is accessed by a source self-aligned to the emitter. The channel is induced by a charge sheet located in the depleted barrier section of the emitter. The mobility of the channel is high (and thus its resistance R/sub IN/ is low) because the narrow-band semiconductor at the interface is undoped. The BICFET does not have charge storage or recombination in a neutral base, and it has the potential for very high speed due its low input capacitance and the enhanced carrier velocity in the collector. The first operation of the N-channel BICFET is reported here. The base-resistance, current-gain, and input-capacitance characteristics of the BICFET are compared to those of the HBT, and BICFET is found to be an attractive structure for circumventing the problems of charge storage and carrier recombination in the HBT.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133843652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51046
R. Bagri, G. Neudeck, W. Klaasen, J. Pak, J. Logsdon
Four methods for fabricating polysilicon-contacted BJTs have been investigated. In the first method polysilicon was deposited using low-pressure chemical vapor deposition (LPCVD) at 620 degrees C. In the remaining three methods a-Si was first deposited and then recrystallized to form polysilicon. In the second method a-Si was deposited using LPCVD at 580 degrees C. The third method used plasma-enhanced chemical vapor deposition (PECVD) to deposit a-Si-H. The fourth method involved a plasma etch with argon or hydrogen prior to deposition of a-Si:H using PECVD. The results indicated that using the PECVD method for depositing a-Si-H without any prior plasma-etch step and recrystallizing it to form polysilicon resulted in the highest current gain ( beta ) enhancement of 3.5 and also allowed the reduction of the polysilicon anneal temperature down to 800 degrees C or 900 degrees C from 1000 degrees C. The compactness in the spread of the peak beta values for the devices fabricated using this technique also reflects its ability to reproducible fabrication of polysilicon contacted shallow emitter BJTs.<>
{"title":"Comparing techniques for fabrication polysilicon contacted emitter bipolar transistors","authors":"R. Bagri, G. Neudeck, W. Klaasen, J. Pak, J. Logsdon","doi":"10.1109/BIPOL.1988.51046","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51046","url":null,"abstract":"Four methods for fabricating polysilicon-contacted BJTs have been investigated. In the first method polysilicon was deposited using low-pressure chemical vapor deposition (LPCVD) at 620 degrees C. In the remaining three methods a-Si was first deposited and then recrystallized to form polysilicon. In the second method a-Si was deposited using LPCVD at 580 degrees C. The third method used plasma-enhanced chemical vapor deposition (PECVD) to deposit a-Si-H. The fourth method involved a plasma etch with argon or hydrogen prior to deposition of a-Si:H using PECVD. The results indicated that using the PECVD method for depositing a-Si-H without any prior plasma-etch step and recrystallizing it to form polysilicon resulted in the highest current gain ( beta ) enhancement of 3.5 and also allowed the reduction of the polysilicon anneal temperature down to 800 degrees C or 900 degrees C from 1000 degrees C. The compactness in the spread of the peak beta values for the devices fabricated using this technique also reflects its ability to reproducible fabrication of polysilicon contacted shallow emitter BJTs.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114586462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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