Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51055
M. Ghannam, R. Mertens, R. van Overstraeten
Detailed two dimensional simulations were carried out on side-wall spacer self-aligned (1) polysilicon emitter bipolar transistor and (2) low-temperature epitaxial emitter bipolar transistor. It is shown that the lateral extrinsic-base-to-intrinsic-base encroachment is improved in the epitaxial emitter transistor resulting in reduced peripheral punchthrough currents. Also, the maximum surface electric field is strongly reduced in the epitaxial emitter structure resulting in smaller tunneling currents. Finally, the calculated transient delays is shorter for the epitaxial transistor than for the polysilicon emitter transistor.<>
{"title":"Two dimensional quantitative study of the performance of low temperature epitaxial silicon emitter bipolar transistors with side-wall spacer","authors":"M. Ghannam, R. Mertens, R. van Overstraeten","doi":"10.1109/BIPOL.1988.51055","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51055","url":null,"abstract":"Detailed two dimensional simulations were carried out on side-wall spacer self-aligned (1) polysilicon emitter bipolar transistor and (2) low-temperature epitaxial emitter bipolar transistor. It is shown that the lateral extrinsic-base-to-intrinsic-base encroachment is improved in the epitaxial emitter transistor resulting in reduced peripheral punchthrough currents. Also, the maximum surface electric field is strongly reduced in the epitaxial emitter structure resulting in smaller tunneling currents. Finally, the calculated transient delays is shorter for the epitaxial transistor than for the polysilicon emitter transistor.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128347289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51040
K. Weiner, T. Sigmon
Gas immersion laser doping (GILD) is presented as a promising new method to fabricate base and emitter regions of precise depth in advanced bipolar transistors. Two additional processes based on GILD technology are introduced: (1) ion implantation with laser redistribution, and (2) laser-induced recrystallization of deposited amorphous Si and Ge films. Transistors with 700-AA base width and maximum current gain of 100 are fabricated. Crystalline Si and Ge/sub 0.18/Si/sub 0.82/ layers are produced on Si<100> substrates using laser recrystallization. These laser-grown layers are suitable for device fabrication.<>
{"title":"Emitter and base fabrication in advanced bipolar transistors using gas immersion laser doping","authors":"K. Weiner, T. Sigmon","doi":"10.1109/BIPOL.1988.51040","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51040","url":null,"abstract":"Gas immersion laser doping (GILD) is presented as a promising new method to fabricate base and emitter regions of precise depth in advanced bipolar transistors. Two additional processes based on GILD technology are introduced: (1) ion implantation with laser redistribution, and (2) laser-induced recrystallization of deposited amorphous Si and Ge films. Transistors with 700-AA base width and maximum current gain of 100 are fabricated. Crystalline Si and Ge/sub 0.18/Si/sub 0.82/ layers are produced on Si<100> substrates using laser recrystallization. These laser-grown layers are suitable for device fabrication.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133270121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51075
J. Lowney
The effects of high-injection levels on the conduction and valence bands of silicon have been determined according to theory based on first principles. The results show important narrowing of the energy gap by the injected electron-hole plasma as well as a reduction in the dopant-carrier interaction because of a reduction in the free-carrier screening radius. Interestingly, these two effects tend to compensate each other somewhat in heavily doped and heavily injected material. Since the gain of a bipolar device is very sensitive to the bandgap, device models need to include these effects in order to model a device correctly throughout its operating regime.<>
{"title":"The effect of high injection on the density of states of silicon","authors":"J. Lowney","doi":"10.1109/BIPOL.1988.51075","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51075","url":null,"abstract":"The effects of high-injection levels on the conduction and valence bands of silicon have been determined according to theory based on first principles. The results show important narrowing of the energy gap by the injected electron-hole plasma as well as a reduction in the dopant-carrier interaction because of a reduction in the free-carrier screening radius. Interestingly, these two effects tend to compensate each other somewhat in heavily doped and heavily injected material. Since the gain of a bipolar device is very sensitive to the bandgap, device models need to include these effects in order to model a device correctly throughout its operating regime.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126591340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51039
M. Klausmeier-Brown, P. Dodd, M. Lundstrom, M. Melloch
A n-p-n bipolar transistor that will be comparable in performance to conventional heterostructure bipolar transistors, but will be far easier to manufacture, is described. The device features an n-GaAs:p/sup +/-GaAs emitter-base junction and makes use of bandgap shrinkage in the p/sup +/-GaAs to maintain high emitter injection efficiency. Measurements of bandgap shrinkage in p/sup +/-GaAs are reviewed. The DC performance of the new device, in terms of the current gain, is expected to be excellent.<>
{"title":"Heteroface bipolar transistor based on bandgap narrowing in p/sup +/-GaAs","authors":"M. Klausmeier-Brown, P. Dodd, M. Lundstrom, M. Melloch","doi":"10.1109/BIPOL.1988.51039","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51039","url":null,"abstract":"A n-p-n bipolar transistor that will be comparable in performance to conventional heterostructure bipolar transistors, but will be far easier to manufacture, is described. The device features an n-GaAs:p/sup +/-GaAs emitter-base junction and makes use of bandgap shrinkage in the p/sup +/-GaAs to maintain high emitter injection efficiency. Measurements of bandgap shrinkage in p/sup +/-GaAs are reviewed. The DC performance of the new device, in terms of the current gain, is expected to be excellent.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126594721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51067
A. Fraser, R. Gleason, E. Strid
Three calibration/correction techniques for on-silicon-wafer S-parameter measurements to 18 GHz were assessed by comparing calibration standards on sapphire and silicon. The effect of these techniques was evaluated by measuring large and small devices, connected to large and small pads. Equivalent circuit models for the calibration standards on silicon are presented. In addition, a new technique for on-wafer S-parameter measurements of backside collector devices is presented.<>
{"title":"GHz on-silicon-wafer probing calibration methods","authors":"A. Fraser, R. Gleason, E. Strid","doi":"10.1109/BIPOL.1988.51067","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51067","url":null,"abstract":"Three calibration/correction techniques for on-silicon-wafer S-parameter measurements to 18 GHz were assessed by comparing calibration standards on sapphire and silicon. The effect of these techniques was evaluated by measuring large and small devices, connected to large and small pads. Equivalent circuit models for the calibration standards on silicon are presented. In addition, a new technique for on-wafer S-parameter measurements of backside collector devices is presented.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133382479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51090
P. Bachert, M. McCombs, P. Sanders
A new RF integrated-circuit technology is described that overcomes the drawbacks of currently available integrated processes. This DIMMIC technology draws its advantage from its dielectric isolation, which minimizes parasitic substrate capacitance, and from its lack of increased collector resistance. Using this technology, a medium-power RF amplifier was built that reduced parts count and size significantly over its discrete counterpart without sacrificing performance.<>
{"title":"A versatile monolithic RF amplifier using a dielectrically isolated monolithic microwave integrated circuit (DIMMIC)","authors":"P. Bachert, M. McCombs, P. Sanders","doi":"10.1109/BIPOL.1988.51090","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51090","url":null,"abstract":"A new RF integrated-circuit technology is described that overcomes the drawbacks of currently available integrated processes. This DIMMIC technology draws its advantage from its dielectric isolation, which minimizes parasitic substrate capacitance, and from its lack of increased collector resistance. Using this technology, a medium-power RF amplifier was built that reduced parts count and size significantly over its discrete counterpart without sacrificing performance.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"50 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133846768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51047
D. Bowers
A high-speed monolithic dual operational amplifier using the 'current feedback' approach is described which enables errors inherent in this type of amplifier to cancel in many applications. The advantages of this approach include a closed-loop bandwidth relatively independent of gain and a very high slew-rate capability. The disadvantages include considerably reduced DC performance compared to a conventional operational amplifier. Techniques for improving the DC performance of the individual amplifiers are described.<>
{"title":"A precision dual 'current feedback' operational amplifier","authors":"D. Bowers","doi":"10.1109/BIPOL.1988.51047","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51047","url":null,"abstract":"A high-speed monolithic dual operational amplifier using the 'current feedback' approach is described which enables errors inherent in this type of amplifier to cancel in many applications. The advantages of this approach include a closed-loop bandwidth relatively independent of gain and a very high slew-rate capability. The disadvantages include considerably reduced DC performance compared to a conventional operational amplifier. Techniques for improving the DC performance of the individual amplifiers are described.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129312132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51045
T. Yamaguchi, Y. Yu, V. Drobny, A. Witkowski
Emitter resistance dependences on emitter arsenic implant dose and diffusion temperature, emitter polysilicon film thickness and its two-dimensional effect, and in situ emitter surface cleaning with HCl gas for submicrometer self-aligned double-polysilicon bipolar transistors are described. Emitter resistance is also characterized as a function of emitter area ranging from 0.6*2.4 mu m/sup 2/ to 3.4*10.4 mu m/sup 2/. Cutoff frequency and ECL-gate delay time are compared between the devices with different emitter areas. Based on the experimental results and circuit simulations, and effects of device geometry scaling on emitter resistance and ECL circuit performance are discussed. It is predicted that an ECL-gate delay time of 35 psec with a cutoff frequency of 33 GHz can be expected at an operational current of 400 mu A by achieving the emitter-base, base-collector, and collector-substrate capacitances of 3 fF, 2 fF, and 4 fF, respectively, with a neutral base width of 40 nm and an emitter resistance of 100 Omega .<>
{"title":"Emitter resistance and performance trade-off of submicrometer self-aligned double-polysilicon bipolar devices","authors":"T. Yamaguchi, Y. Yu, V. Drobny, A. Witkowski","doi":"10.1109/BIPOL.1988.51045","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51045","url":null,"abstract":"Emitter resistance dependences on emitter arsenic implant dose and diffusion temperature, emitter polysilicon film thickness and its two-dimensional effect, and in situ emitter surface cleaning with HCl gas for submicrometer self-aligned double-polysilicon bipolar transistors are described. Emitter resistance is also characterized as a function of emitter area ranging from 0.6*2.4 mu m/sup 2/ to 3.4*10.4 mu m/sup 2/. Cutoff frequency and ECL-gate delay time are compared between the devices with different emitter areas. Based on the experimental results and circuit simulations, and effects of device geometry scaling on emitter resistance and ECL circuit performance are discussed. It is predicted that an ECL-gate delay time of 35 psec with a cutoff frequency of 33 GHz can be expected at an operational current of 400 mu A by achieving the emitter-base, base-collector, and collector-substrate capacitances of 3 fF, 2 fF, and 4 fF, respectively, with a neutral base width of 40 nm and an emitter resistance of 100 Omega .<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123296304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51057
H. Jeong, J. Fossum
Impact ionization in advanced bipolar transistors, which depends on the complex electric-field distribution in the collector, is accounted for in a physical (seminumerical) device model. The collector analysis comprehensively treats quasi-saturation, and thus accounts for the formation of the current-induced space-charge region at high currents as well as the modulation of the junction space-charge region. Simulated (with MMSPICE) and measured characteristics are compared in support of the model.<>
{"title":"Modeling impact ionization in advanced bipolar transistors for device/circuit simulation","authors":"H. Jeong, J. Fossum","doi":"10.1109/BIPOL.1988.51057","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51057","url":null,"abstract":"Impact ionization in advanced bipolar transistors, which depends on the complex electric-field distribution in the collector, is accounted for in a physical (seminumerical) device model. The collector analysis comprehensively treats quasi-saturation, and thus accounts for the formation of the current-induced space-charge region at high currents as well as the modulation of the junction space-charge region. Simulated (with MMSPICE) and measured characteristics are compared in support of the model.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131447114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51074
J. Gannett
Rink, an automatic layout verification system intended for FET technologies, has been enhanced to handle bipolar designs. A straightforward procedure that uses Rink's parasitic capacitance extractor to solve the bipolar device identification problem is described. The bipolar enhancements to Rink have been used successfully on a set of seven high-speed bipolar chips designed for lightwave communication. These chips ranged in complexity from 23 to 67 devices. Full-custom, nonmanhattan layouts for these chips were created on polygon-pusher style layout editors. For each chip, Rink executed an automatic comparison of the netlist extracted from the layout against a SPICE reference netlist. The latter has been coded for SPICE design simulations. Several fatal connectivity errors were uncovered as were a few significant disparities in resistor values and transistor sizes.<>
{"title":"Extending an FET layout verification system to bipolar technology","authors":"J. Gannett","doi":"10.1109/BIPOL.1988.51074","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51074","url":null,"abstract":"Rink, an automatic layout verification system intended for FET technologies, has been enhanced to handle bipolar designs. A straightforward procedure that uses Rink's parasitic capacitance extractor to solve the bipolar device identification problem is described. The bipolar enhancements to Rink have been used successfully on a set of seven high-speed bipolar chips designed for lightwave communication. These chips ranged in complexity from 23 to 67 devices. Full-custom, nonmanhattan layouts for these chips were created on polygon-pusher style layout editors. For each chip, Rink executed an automatic comparison of the netlist extracted from the layout against a SPICE reference netlist. The latter has been coded for SPICE design simulations. Several fatal connectivity errors were uncovered as were a few significant disparities in resistor values and transistor sizes.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130650192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：