Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51085
S.-Y. Yung, D. Burk
The best-case power-delay products for bipolar-transistor gates that have optimally designed transistors with polysilicon-contacted emitters, both with and without interfacial layers between the polysilicon and underlying emitter, are predicted. It is shown that gates that have one or the other of these contacted-resistors have comparable power-delay products. Because this modeling is very general, it is believed the results are applicable for arsenic as well as phosphorous-doped polysilicon-contacted bipolar transistors.<>
{"title":"The best-case power-delay products for polysilicon-contacted bipolar-transistor gates. A theoretical study","authors":"S.-Y. Yung, D. Burk","doi":"10.1109/BIPOL.1988.51085","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51085","url":null,"abstract":"The best-case power-delay products for bipolar-transistor gates that have optimally designed transistors with polysilicon-contacted emitters, both with and without interfacial layers between the polysilicon and underlying emitter, are predicted. It is shown that gates that have one or the other of these contacted-resistors have comparable power-delay products. Because this modeling is very general, it is believed the results are applicable for arsenic as well as phosphorous-doped polysilicon-contacted bipolar transistors.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114213877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51066
G. Flower
A 3 GHz 4:1 multiplexer has been designed in Hewlett Packard's newest bipolar process. The circuit is fully differential and uses ECL-level outputs. Inputs are also ECL levels. The design uses a travelling wave divider approach to generate the timing signals for a 4:1 series gated asynchronous multiplexer. An output flip-flop and an inverting (on-chip) delay line are used in conjunction to retime the output data. The chip operates to 3 GHz from approximately 100 MHz with a power dissipation of 1.8 W. Off-chip drivers are on chip terminated to approximately 100 Omega to present a VSWR of better than 2:1 at the output. Full input registers lock in the data at the inputs.<>
{"title":"A 3 GigaHertz 4:1 time division multiplexer with output retiming","authors":"G. Flower","doi":"10.1109/BIPOL.1988.51066","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51066","url":null,"abstract":"A 3 GHz 4:1 multiplexer has been designed in Hewlett Packard's newest bipolar process. The circuit is fully differential and uses ECL-level outputs. Inputs are also ECL levels. The design uses a travelling wave divider approach to generate the timing signals for a 4:1 series gated asynchronous multiplexer. An output flip-flop and an inverting (on-chip) delay line are used in conjunction to retime the output data. The chip operates to 3 GHz from approximately 100 MHz with a power dissipation of 1.8 W. Off-chip drivers are on chip terminated to approximately 100 Omega to present a VSWR of better than 2:1 at the output. Full input registers lock in the data at the inputs.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"22 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124554423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51069
B. Baccus, D. Collard, E. Dubois, D. Morel
A new 2D multilayer process simulator specially developed for the study of advanced bipolar technologies is described. Numerical problems are presented and an application is introduced to demonstrate the possibilities of the program. The layer management is performed by the topology simulation module, according to the etching or deposition steps. The well-known string model is used and special algorithmic problems have been solved in order to take into account the general multilayer aspect. The compatibility with mesh generation has been also carefully studied: to avoid accuracy loss in the surface shape definition, the string model points are also the surface vertices of the FEM triangulation.<>
{"title":"Two-dimensional process simulation of bipolar devices using a multilayer simulator: IMPACT4","authors":"B. Baccus, D. Collard, E. Dubois, D. Morel","doi":"10.1109/BIPOL.1988.51069","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51069","url":null,"abstract":"A new 2D multilayer process simulator specially developed for the study of advanced bipolar technologies is described. Numerical problems are presented and an application is introduced to demonstrate the possibilities of the program. The layer management is performed by the topology simulation module, according to the etching or deposition steps. The well-known string model is used and special algorithmic problems have been solved in order to take into account the general multilayer aspect. The compatibility with mesh generation has been also carefully studied: to avoid accuracy loss in the surface shape definition, the string model points are also the surface vertices of the FEM triangulation.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124910468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51035
H.J. Greub, J. McDonald, T. Creedon
Advanced bipolar circuits for a RISC operating at a 250 MHz instruction rate are presented. Specifically a 30*8 bit register file macro with 500-ps access time is presented and a clock skew compensation scheme based on digital delay lines is introduced that can significantly reduce clock skew in a wafer scale multichip package. The predicted performance of advanced bipolar memory macros, I/O circuitry, and differential logic circuit are very encouraging. Measurement on a fabricated divide by two circuits shows good agreement with SPICE simulations.<>
{"title":"Key components of the fast reduced instruction set computer (FRISC) employing advanced bipolar differential logic and wafer scale multichip packaging","authors":"H.J. Greub, J. McDonald, T. Creedon","doi":"10.1109/BIPOL.1988.51035","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51035","url":null,"abstract":"Advanced bipolar circuits for a RISC operating at a 250 MHz instruction rate are presented. Specifically a 30*8 bit register file macro with 500-ps access time is presented and a clock skew compensation scheme based on digital delay lines is introduced that can significantly reduce clock skew in a wafer scale multichip package. The predicted performance of advanced bipolar memory macros, I/O circuitry, and differential logic circuit are very encouraging. Measurement on a fabricated divide by two circuits shows good agreement with SPICE simulations.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"278 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116425070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51052
F. Highton, K. Ito
PCM58, a self-contained 18-bit bipolar DAC that responds to serial input data, represents a significant advance in monolithic data conversion. Designed for digital audio applications, it provides 16-bit accuracy at low cost. The converter is built on a 20 V junction isolated bipolar process that offers thin-film NiCr resistors and a buried zener.<>
{"title":"An 18-bit DAC for consumer applications","authors":"F. Highton, K. Ito","doi":"10.1109/BIPOL.1988.51052","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51052","url":null,"abstract":"PCM58, a self-contained 18-bit bipolar DAC that responds to serial input data, represents a significant advance in monolithic data conversion. Designed for digital audio applications, it provides 16-bit accuracy at low cost. The converter is built on a 20 V junction isolated bipolar process that offers thin-film NiCr resistors and a buried zener.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127291951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51080
S. Sawada
Emitter perimeter effects in advanced self-aligned bipolar transistors utilizing a sidewall spacer technology have been studied. Collector-emitter punchthrough, emitter current crowding and base resistance increment due to insufficient extrinsic-intrinsic base overlap in the emitter periphery, and the lowering of cutoff frequency and the tunneling current due to the lateral encroachment of the extrinsic-base into the intrinsic-base area are discussed. Particular emphasis is placed on the dependence of the degree of the extrinsic-intrinsic base overlap on the sidewall spacer length and the extrinsic-base profile. The balance between increasing the base resistance increment and decreasing the cutoff frequency is a device design tradeoff, as is the balance between the perimeter punchthrough current and the perimeter tunneling current.<>
{"title":"Perimeter effect in advanced self-aligned bipolar transistor","authors":"S. Sawada","doi":"10.1109/BIPOL.1988.51080","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51080","url":null,"abstract":"Emitter perimeter effects in advanced self-aligned bipolar transistors utilizing a sidewall spacer technology have been studied. Collector-emitter punchthrough, emitter current crowding and base resistance increment due to insufficient extrinsic-intrinsic base overlap in the emitter periphery, and the lowering of cutoff frequency and the tunneling current due to the lateral encroachment of the extrinsic-base into the intrinsic-base area are discussed. Particular emphasis is placed on the dependence of the degree of the extrinsic-intrinsic base overlap on the sidewall spacer length and the extrinsic-base profile. The balance between increasing the base resistance increment and decreasing the cutoff frequency is a device design tradeoff, as is the balance between the perimeter punchthrough current and the perimeter tunneling current.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126500970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/BIPOL.1988.51051
B. Harvey
An analog comparator that combines the input characteristics of traditional operational amplifiers with the bandwidths and small delays provided by the dielectric isolation process is described. A new comparator configuration involving an integral master/slave flipflop that eliminates oscillations is detailed.<>
{"title":"A 20 nsec high-voltage analog comparator","authors":"B. Harvey","doi":"10.1109/BIPOL.1988.51051","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51051","url":null,"abstract":"An analog comparator that combines the input characteristics of traditional operational amplifiers with the bandwidths and small delays provided by the dielectric isolation process is described. A new comparator configuration involving an integral master/slave flipflop that eliminates oscillations is detailed.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122923132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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