Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51083
G. P. Rosseel, R. Dutton, K. Mayaram, D. Pederson
Simple delay models are derived for the different regions of operation for the bipolar transistors in a BiCMOS driver. The delay equations are approximate but extremely useful in relating the gate delay to the device and circuit parameters. Simulations from a mixed-level circuit and device simulator, CODECS, are used to verify the delay models. SPICE simulations are inadequate since high-level injection effects critical to the performance of the bipolar transistors are not well modeled with present bipolar transistor models in SPICE. The effects of various collector doping concentrations and epi-layer thickness are also investigated.<>
{"title":"Delay analysis for BiCMOS drivers","authors":"G. P. Rosseel, R. Dutton, K. Mayaram, D. Pederson","doi":"10.1109/BIPOL.1988.51083","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51083","url":null,"abstract":"Simple delay models are derived for the different regions of operation for the bipolar transistors in a BiCMOS driver. The delay equations are approximate but extremely useful in relating the gate delay to the device and circuit parameters. Simulations from a mixed-level circuit and device simulator, CODECS, are used to verify the delay models. SPICE simulations are inadequate since high-level injection effects critical to the performance of the bipolar transistors are not well modeled with present bipolar transistor models in SPICE. The effects of various collector doping concentrations and epi-layer thickness are also investigated.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114520498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51091
I. Kipnis, J. F. Kukielka, C. C. Leung, T. Lo, M. Dutta, S. Knorr, C. Snapp
A static divide-by-four frequency prescalar IC operating for input signals from 20 MHz to 5.5 GHz is presented. The circuit was fabricated using Avantek's f/sub T/=12 GHz f/sub max/=20 GHz non-polysilicon-emitter ISOSAT-I silicon bipolar process. The die fits in a standard microwave transistor package due to its small size and single-bias-supply requirement. An integrated input buffer was provided to obtain high sensitivity and to avoid self-oscillation in the absence of an input signal. This work presents an example of a medium-scale-integration silicon bipolar IC operating at GHz frequencies (or Gbit/s rates).<>
{"title":"A wideband, low-power, high-sensitivity and small-size 2.5-GHz static frequency divider IC","authors":"I. Kipnis, J. F. Kukielka, C. C. Leung, T. Lo, M. Dutta, S. Knorr, C. Snapp","doi":"10.1109/BIPOL.1988.51091","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51091","url":null,"abstract":"A static divide-by-four frequency prescalar IC operating for input signals from 20 MHz to 5.5 GHz is presented. The circuit was fabricated using Avantek's f/sub T/=12 GHz f/sub max/=20 GHz non-polysilicon-emitter ISOSAT-I silicon bipolar process. The die fits in a standard microwave transistor package due to its small size and single-bias-supply requirement. An integrated input buffer was provided to obtain high sensitivity and to avoid self-oscillation in the absence of an input signal. This work presents an example of a medium-scale-integration silicon bipolar IC operating at GHz frequencies (or Gbit/s rates).<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129019257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51078
L. Ristić, T. Smy, H. Baltes, I. Filanovsky
A comparative study of a CMOS lateral magnetoresistor structure and a novel structure, with a locally doped base in the proximity of the emitter, is presented. For both structures a differential approach is used. The results indicate that the two locally doped p/sup +/-stripes restrict the injection of electrons from the emitter to the vertical direction, dramatically changing the path of the electrons flowing from the emitter laterally to the collectors. This in turn leads to a more effective deflection, by the magnetic field, of the electrons contributing to the collector current. As a result the magnetic sensitivity of the device is increased by more then three times.<>
{"title":"A CMOS bipolar transistor with a locally doped base in the proximity of the emitter as a magnetic field sensor","authors":"L. Ristić, T. Smy, H. Baltes, I. Filanovsky","doi":"10.1109/BIPOL.1988.51078","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51078","url":null,"abstract":"A comparative study of a CMOS lateral magnetoresistor structure and a novel structure, with a locally doped base in the proximity of the emitter, is presented. For both structures a differential approach is used. The results indicate that the two locally doped p/sup +/-stripes restrict the injection of electrons from the emitter to the vertical direction, dramatically changing the path of the electrons flowing from the emitter laterally to the collectors. This in turn leads to a more effective deflection, by the magnetic field, of the electrons contributing to the collector current. As a result the magnetic sensitivity of the device is increased by more then three times.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125576461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51089
K. O, H. Lee, R. Reif, W. Frank, W. Metz, T. Gillis
A bipolar structure with an estimated f/sub T/ of 5 GHz was fabricated on a selective epitaxial layer. A shallow buried layer (0.25 mu m approximately 0.50 mu m) was formed by diffusing arsenic atoms from an arsenic-implanted polysilicon layer. The polysilicon layer was removed by converting it to oxide and etching the oxide. The defective regions at the edges of the selective epitaxial layer were removed by a plasma etch step to form defect-free base-collector junctions; the junctions can be placed less than 2 mu m from the edges without degrading the device characteristics. Using the selective epitaxial growth, LOCOS isolation and the shallow buried layer, semi-dielectric transistor isolation was achieved.<>
{"title":"A bipolar structure with semi-dielectric device isolation by selective epitaxial growth","authors":"K. O, H. Lee, R. Reif, W. Frank, W. Metz, T. Gillis","doi":"10.1109/BIPOL.1988.51089","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51089","url":null,"abstract":"A bipolar structure with an estimated f/sub T/ of 5 GHz was fabricated on a selective epitaxial layer. A shallow buried layer (0.25 mu m approximately 0.50 mu m) was formed by diffusing arsenic atoms from an arsenic-implanted polysilicon layer. The polysilicon layer was removed by converting it to oxide and etching the oxide. The defective regions at the edges of the selective epitaxial layer were removed by a plasma etch step to form defect-free base-collector junctions; the junctions can be placed less than 2 mu m from the edges without degrading the device characteristics. Using the selective epitaxial growth, LOCOS isolation and the shallow buried layer, semi-dielectric transistor isolation was achieved.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"346 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122561015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51056
W. Kloosterman, H. de Graaff
Weak avalanche in bipolar transistors can be accurately modeled by using the collector depletion capacitance. This model has the advantages of a relatively fast numerical evaluation and an easily extracted avalanche parameter. The model incorporates internal voltage drop and temperature dependence and can be implemented in any compact bipolar transistor model.<>
{"title":"Avalanche multiplication in a compact bipolar transistor model for circuit simulation","authors":"W. Kloosterman, H. de Graaff","doi":"10.1109/BIPOL.1988.51056","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51056","url":null,"abstract":"Weak avalanche in bipolar transistors can be accurately modeled by using the collector depletion capacitance. This model has the advantages of a relatively fast numerical evaluation and an easily extracted avalanche parameter. The model incorporates internal voltage drop and temperature dependence and can be implemented in any compact bipolar transistor model.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126467513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51059
V.F. Drobny, C. Hacherl, S. Dotarrar, T. Yamaguchi, A. Tang, Y. Yu
The combination of self-aligned double-polysilicon bipolar technology with the trench isolation technique and planarized field oxide and polysilicon regions results in a high-performance bipolar VLSI process, planarized at all mask levels. The planarization approach simplifies photolithography. It also eliminates deformation and discontinuities of polysilicon lines over severe topography and problems with polysilicon residue after RIE steps. A SWAMI process is used to define and isolate both polysilicon layers.<>
{"title":"Planarized self-aligned double-polysilicon bipolar technology","authors":"V.F. Drobny, C. Hacherl, S. Dotarrar, T. Yamaguchi, A. Tang, Y. Yu","doi":"10.1109/BIPOL.1988.51059","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51059","url":null,"abstract":"The combination of self-aligned double-polysilicon bipolar technology with the trench isolation technique and planarized field oxide and polysilicon regions results in a high-performance bipolar VLSI process, planarized at all mask levels. The planarization approach simplifies photolithography. It also eliminates deformation and discontinuities of polysilicon lines over severe topography and problems with polysilicon residue after RIE steps. A SWAMI process is used to define and isolate both polysilicon layers.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116858833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51071
A. Alvarez, J. Arreola, S. Pai, K.N. Ratnakumar
A corners methodology for BiCMOS is derived using CMOS corners as the basis. Five corners for CMOS are proposed. Coupled to the four axis corners are two bipolar corners per CMOS corner. This implies that for BiCMOS there are a total of nine possible transistor corners that are superimposed on temperature, voltage, and resistor variation. Physical correlation between MOS and bipolar parameters is taken into account by using numerical and analytical techniques. Both lithographic and diffusion/film variations are accounted for in the methodology. Using the described approach, nonphysical corners are eliminated and the total number of possibilities is restricted to those of practical interest. Resulting corners circuit simulations clearly show the advantage of using physically based worst-case process files. Also demonstrated is the robustness of the basic BiCMOS gate with respect to worst-case process files and temperature.<>
{"title":"A methodology for worst-case design of BiCMOS integrated circuits","authors":"A. Alvarez, J. Arreola, S. Pai, K.N. Ratnakumar","doi":"10.1109/BIPOL.1988.51071","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51071","url":null,"abstract":"A corners methodology for BiCMOS is derived using CMOS corners as the basis. Five corners for CMOS are proposed. Coupled to the four axis corners are two bipolar corners per CMOS corner. This implies that for BiCMOS there are a total of nine possible transistor corners that are superimposed on temperature, voltage, and resistor variation. Physical correlation between MOS and bipolar parameters is taken into account by using numerical and analytical techniques. Both lithographic and diffusion/film variations are accounted for in the methodology. Using the described approach, nonphysical corners are eliminated and the total number of possibilities is restricted to those of practical interest. Resulting corners circuit simulations clearly show the advantage of using physically based worst-case process files. Also demonstrated is the robustness of the basic BiCMOS gate with respect to worst-case process files and temperature.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128911396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51086
J. Dunkley, R. Metzler
A rigorous statistical technique is presented for properly modeling the design rules for the maximum current density permitted to pass through the interconnecting metal of an integrated circuit. The electromigration model includes consideration of the circuit's overall manufacturing and systems environment. Process variables, assembly variables, and variations in the system's electrical and thermal environment are statistically accounted for when determining current density limits in the metallization. This assures that the reliability requirements of the circuit are met.<>
{"title":"A systems approach to electromigration prevention in bipolar integrated circuits","authors":"J. Dunkley, R. Metzler","doi":"10.1109/BIPOL.1988.51086","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51086","url":null,"abstract":"A rigorous statistical technique is presented for properly modeling the design rules for the maximum current density permitted to pass through the interconnecting metal of an integrated circuit. The electromigration model includes consideration of the circuit's overall manufacturing and systems environment. Process variables, assembly variables, and variations in the system's electrical and thermal environment are statistically accounted for when determining current density limits in the metallization. This assures that the reliability requirements of the circuit are met.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133508935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51037
K. Yamaguchi, H. Nanbu, K. Kanetani, N. Homma, T. Nakamura, K. Ohhata, A. Uchida, K. Ogiue
An experimental soft-error immune 64-kb 3-ns emitter couple logic (ECL) random access memory (RAM) has been developed. Its key factors are: a soft-error immune memory cell, an upward transistor decoder, a Darlington word driver with advanced discharge circuits, and 0.8 mu m SICOS technology. To reduce the memory cell size, double-layer polysilicon is used for high and low load-resistor. These double layers of polysilicon are essential in realizing the memory cell size of 498 mu m/sup 2/.<>
研制了一种实验性的64 kb 3-ns射极耦合逻辑随机存取存储器(RAM)。其关键因素是:软错误免疫存储单元，向上晶体管解码器，先进放电电路的达灵顿字驱动，0.8 μ m SICOS技术。为了减小存储单元的尺寸，高、低负载电阻器采用双层多晶硅。这些双层多晶硅对于实现498 μ m/sup /的存储单元尺寸至关重要。
{"title":"An experimental soft-error immune 64-Kb 3 ns ECL bipolar RAM","authors":"K. Yamaguchi, H. Nanbu, K. Kanetani, N. Homma, T. Nakamura, K. Ohhata, A. Uchida, K. Ogiue","doi":"10.1109/BIPOL.1988.51037","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51037","url":null,"abstract":"An experimental soft-error immune 64-kb 3-ns emitter couple logic (ECL) random access memory (RAM) has been developed. Its key factors are: a soft-error immune memory cell, an upward transistor decoder, a Darlington word driver with advanced discharge circuits, and 0.8 mu m SICOS technology. To reduce the memory cell size, double-layer polysilicon is used for high and low load-resistor. These double layers of polysilicon are essential in realizing the memory cell size of 498 mu m/sup 2/.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134193217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51036
H. Itoh, T. Saitoh, T. Yamada, M. Yamamoto, A. Masaki
Approaches to high-speed and high-load driving capability of bipolar logic gates are discussed. Several circuits are investigated. It is shown that the Emitter Coupled Logic (ECL) with FET pull-down emitter-followers has a 3-5 times greater capability of driving capacitive loads than the conventional one. The performance improvement is drastically enhanced when applied to GaAs LSIs.<>
{"title":"Advanced ECL with new active pull-down emitter-followers","authors":"H. Itoh, T. Saitoh, T. Yamada, M. Yamamoto, A. Masaki","doi":"10.1109/BIPOL.1988.51036","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51036","url":null,"abstract":"Approaches to high-speed and high-load driving capability of bipolar logic gates are discussed. Several circuits are investigated. It is shown that the Emitter Coupled Logic (ECL) with FET pull-down emitter-followers has a 3-5 times greater capability of driving capacitive loads than the conventional one. The performance improvement is drastically enhanced when applied to GaAs LSIs.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126893890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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