Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978524
W. Chong, W. Cho, Z. Liu, Chu Hong Wang, K. Lau
We report the first 1700 pixels per inch (PPI) passive-matrix blue light-emitting diodes on silicon (LEDoS) micro-displays. By flip-chip bonding a micro-LED array onto an ASIC display driver, we successfully fabricated a 0.19-inch display with a resolution of 256 x 192, the highest ever reported in LED-based micro-display. In addition, the LEDoS micro-display can deliver brightness as high as 1300 mcd/m2 and render images in 6-bit grayscale. The remarkable performance suggests the tremendous potential of LEDoS micro-displays for portable display applications which require high performance, small size and low power consumption.
我们报告了第一个1700像素每英寸(PPI)的无源矩阵蓝色发光二极管硅(LEDoS)微显示器。通过将微型led阵列倒装到ASIC显示驱动器上，我们成功地制作了分辨率为256 x 192的0.19英寸显示屏，这是基于led的微显示器中最高的。此外，LEDoS微型显示器可以提供高达1300 mcd/m2的亮度，并以6位灰度呈现图像。卓越的性能表明LEDoS微型显示器在高性能、小尺寸和低功耗的便携式显示应用中具有巨大的潜力。
{"title":"1700 Pixels Per Inch (PPI) Passive-Matrix Micro-LED Display Powered by ASIC","authors":"W. Chong, W. Cho, Z. Liu, Chu Hong Wang, K. Lau","doi":"10.1109/CSICS.2014.6978524","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978524","url":null,"abstract":"We report the first 1700 pixels per inch (PPI) passive-matrix blue light-emitting diodes on silicon (LEDoS) micro-displays. By flip-chip bonding a micro-LED array onto an ASIC display driver, we successfully fabricated a 0.19-inch display with a resolution of 256 x 192, the highest ever reported in LED-based micro-display. In addition, the LEDoS micro-display can deliver brightness as high as 1300 mcd/m2 and render images in 6-bit grayscale. The remarkable performance suggests the tremendous potential of LEDoS micro-displays for portable display applications which require high performance, small size and low power consumption.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125427134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978556
H. Blanck, J. Splettstober, D. Floriot
In the last years GaN has remained a key technology in Europe in particular, but not only, for RF Applications. After an intensive period of research and development the scope has shifted towards industrialization and product development. This is especially true for the applications up to around 20GHz where systems are now being built using European GaN-based components. At the same time, an increasing part of the research activity has moved toward higher frequencies beyond 20GHz.
{"title":"Future of GaN RF Technology in Europe","authors":"H. Blanck, J. Splettstober, D. Floriot","doi":"10.1109/CSICS.2014.6978556","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978556","url":null,"abstract":"In the last years GaN has remained a key technology in Europe in particular, but not only, for RF Applications. After an intensive period of research and development the scope has shifted towards industrialization and product development. This is especially true for the applications up to around 20GHz where systems are now being built using European GaN-based components. At the same time, an increasing part of the research activity has moved toward higher frequencies beyond 20GHz.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130253957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978544
T. Merkle, A. Leuther, S. Koch, I. Kallfass, A. Tessmann, S. Wagner, H. Massler, M. Schlechtweg, O. Ambacher
High gain amplifier MMICs (monolithic microwave integrated circuits) addressing broadband radar and communication applications at the waveguide bands WR-6 (110 - 170 GHz) and WR-3 (220 - 325 GHz) are presented. All circuits are manufactured in the next generation metamorphic high electron mobility transistor (mHEMT) technology featuring 20 nm gate length and a strained 100% InAs channel. The transistors are encapsulated by 0.3 μm and 1.4 μm thick layers of benzocyclobutene (BCB). The 1.4 μm thick BCB layer is used to form shielded thin-film microstrip (TFMS) lines confined at the front-side of the wafer for implementing matching networks. Substrate thinning and backside processing is not required for the function of the amplifiers. The amplifier for WR-6 operates over the whole waveguide band with an average gain of 28 dB. A gain of more than 24 dB was measured for the MMIC from 215 - 290 GHz. All presented MMICs exceed 30% of gain defined bandwidth.
{"title":"Backside Process Free Broadband Amplifier MMICs at D-Band and H-Band in 20 nm mHEMT Technology","authors":"T. Merkle, A. Leuther, S. Koch, I. Kallfass, A. Tessmann, S. Wagner, H. Massler, M. Schlechtweg, O. Ambacher","doi":"10.1109/CSICS.2014.6978544","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978544","url":null,"abstract":"High gain amplifier MMICs (monolithic microwave integrated circuits) addressing broadband radar and communication applications at the waveguide bands WR-6 (110 - 170 GHz) and WR-3 (220 - 325 GHz) are presented. All circuits are manufactured in the next generation metamorphic high electron mobility transistor (mHEMT) technology featuring 20 nm gate length and a strained 100% InAs channel. The transistors are encapsulated by 0.3 μm and 1.4 μm thick layers of benzocyclobutene (BCB). The 1.4 μm thick BCB layer is used to form shielded thin-film microstrip (TFMS) lines confined at the front-side of the wafer for implementing matching networks. Substrate thinning and backside processing is not required for the function of the amplifiers. The amplifier for WR-6 operates over the whole waveguide band with an average gain of 28 dB. A gain of more than 24 dB was measured for the MMIC from 215 - 290 GHz. All presented MMICs exceed 30% of gain defined bandwidth.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133906787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978584
Gabriel M. Rebeiz, W. Shin, F. Golcuk, O. Inac, S. Zihir, O. Gurbuz, J. Edwards, T. Kanar
Presents a summary of the millimeter-wave wafer-scale phased array work at UCSD. This concept can drastically reduce the cost of millimeter-wave phased arrays by combining the RFIC blocks, antennas, power distribution and summing, digital control and up and down converters all on the same wafer (or large piece of silicon), and eliminates all RF transitions in and out of the chip, therefore resulting in more efficient systems and lower cost systems. Examples at 90-100 GHz, 108-114 GHz and 400 GHz will be presented in this paper, together with their measured antenna patterns.
{"title":"Wafer-Scale Millimeter-Wave Phased-Array RFICs","authors":"Gabriel M. Rebeiz, W. Shin, F. Golcuk, O. Inac, S. Zihir, O. Gurbuz, J. Edwards, T. Kanar","doi":"10.1109/CSICS.2014.6978584","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978584","url":null,"abstract":"Presents a summary of the millimeter-wave wafer-scale phased array work at UCSD. This concept can drastically reduce the cost of millimeter-wave phased arrays by combining the RFIC blocks, antennas, power distribution and summing, digital control and up and down converters all on the same wafer (or large piece of silicon), and eliminates all RF transitions in and out of the chip, therefore resulting in more efficient systems and lower cost systems. Examples at 90-100 GHz, 108-114 GHz and 400 GHz will be presented in this paper, together with their measured antenna patterns.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128557126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978546
S. Shopov, S. Voinigescu
This paper describes for the first time the high frequency performance characterization of a production 28-nm ultra-thin-body-and-BOX (UTBB) fully-depleted (FD) SOI CMOS technology. The measured gm, fT, and maximum available gain (MAG) of fully-wired n-channel and p-channel MOSFETs are reported as a function of gate-source, drainsource, back-gate voltages and drain current density. It is shown that the back-gate bias can reduce the VGS at which the peak gm, peak fT and peak MAG occur by up to 400 mV and can flatten the fT-VGS characteristics, as needed in highly linear amplifiers. The peak gm/fT values of 1.5mS/μm/298GHz and 0.93mS/μm/194GHz, for n-MOSFETs and p-MOSFETs respectively, match or exceed those of 28-nm LP bulk and 45-nm SOI MOSFETs with identical layout geometry and metal stack wiring.
本文首次描述了量产28纳米超薄体盒(UTBB)全耗尽(FD) SOI CMOS技术的高频性能表征。报告了全有线n沟道和p沟道mosfet的测量gm、fT和最大可用增益(MAG)是栅极源、漏极源、后门电压和漏极电流密度的函数。结果表明，在高线性放大器中，后门偏置可以将峰值gm、峰值fT和峰值MAG产生的VGS降低高达400 mV，并可以使fT-VGS特性变平。n- mosfet和p- mosfet的峰值gm/fT值分别为1.5mS/μm/298GHz和0.93mS/μm/194GHz，匹配或超过具有相同布局几何形状和金属堆叠布线的28 nm LP bulk和45 nm SOI mosfet。
{"title":"Characterization of the High Frequency Performance of 28-nm UTBB FDSOI MOSFETs as a Function of Backgate Bias","authors":"S. Shopov, S. Voinigescu","doi":"10.1109/CSICS.2014.6978546","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978546","url":null,"abstract":"This paper describes for the first time the high frequency performance characterization of a production 28-nm ultra-thin-body-and-BOX (UTBB) fully-depleted (FD) SOI CMOS technology. The measured g<sub>m</sub>, f<sub>T</sub>, and maximum available gain (MAG) of fully-wired n-channel and p-channel MOSFETs are reported as a function of gate-source, drainsource, back-gate voltages and drain current density. It is shown that the back-gate bias can reduce the V<sub>GS</sub> at which the peak g<sub>m</sub>, peak f<sub>T</sub> and peak MAG occur by up to 400 mV and can flatten the f<sub>T</sub>-V<sub>GS</sub> characteristics, as needed in highly linear amplifiers. The peak g<sub>m</sub>/f<sub>T</sub> values of 1.5mS/μm/298GHz and 0.93mS/μm/194GHz, for n-MOSFETs and p-MOSFETs respectively, match or exceed those of 28-nm LP bulk and 45-nm SOI MOSFETs with identical layout geometry and metal stack wiring.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129179821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978585
A. Margomenos, A. Kurdoghlian, M. Micovic, K. Shinohara, H. Moyer, D. Regan, R. Grabar, C. Mcguire, M. Wetzel, D. Chow
We report the first W-band GaN receiver components using a next generation, highly scaled GaN device technology. This technology (40nm, fT= 220 GHz, fmax= 400 GHz, Vbrk > 40V) enables receiver components that meet or exceed performance reported by competing device technologies while maintaining > 5x higher breakdown voltage, higher linearity, dynamic range and RF survivability. This paper includes results for a 4 and a 5 stage low noise amplifier (LNA) (gain over 5 dB/stage at 110 GHz), a single-pole single-throw (SPST) and a single-pole double-throw (SPDT) switch with loss of 0.9 dB and 1.3 dB respectively and a reflective type phase shifter
{"title":"W-Band GaN Receiver Components Utilizing Highly Scaled, Next Generation GaN Device Technology","authors":"A. Margomenos, A. Kurdoghlian, M. Micovic, K. Shinohara, H. Moyer, D. Regan, R. Grabar, C. Mcguire, M. Wetzel, D. Chow","doi":"10.1109/CSICS.2014.6978585","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978585","url":null,"abstract":"We report the first W-band GaN receiver components using a next generation, highly scaled GaN device technology. This technology (40nm, fT= 220 GHz, fmax= 400 GHz, Vbrk > 40V) enables receiver components that meet or exceed performance reported by competing device technologies while maintaining > 5x higher breakdown voltage, higher linearity, dynamic range and RF survivability. This paper includes results for a 4 and a 5 stage low noise amplifier (LNA) (gain over 5 dB/stage at 110 GHz), a single-pole single-throw (SPST) and a single-pole double-throw (SPDT) switch with loss of 0.9 dB and 1.3 dB respectively and a reflective type phase shifter","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133941793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978566
R. Howell, E. Stewart, R. Freitag, J. Parke, B. Nechay, H. Cramer, M. King, Shalini Gupta, J. Hartman, P. Borodulin, M. Snook, I. Wathuthanthri, Parrish Ralston, K. Renaldo, H. G. Henry
A low loss, high isolation, broadband RF switch has been developed using a novel type of field effect transistor structure that exploits the use of a super-lattice structure in combination with a three dimensional, castellated gate to achieve excellent RF switch performance. Using an AlGaN/GaN super-lattice epitaxial layer, this Super-Lattice Castellated Field Effect Transistor (SLCFET) was used to build 1-18 GHz SPDT RF switches. Measured insertion loss of the SPDT at 10 GHz was -0.4 dB, with -35 dB of isolation and -23 dB of return loss, along with a measured linearity OIP3 value 62 dBm and a P0.1dB of 34 dBm.
{"title":"Low Loss, High Performance 1-18 GHz SPDT Based on the Novel Super-Lattice Castellated Field Effect Transistor (SLCFET)","authors":"R. Howell, E. Stewart, R. Freitag, J. Parke, B. Nechay, H. Cramer, M. King, Shalini Gupta, J. Hartman, P. Borodulin, M. Snook, I. Wathuthanthri, Parrish Ralston, K. Renaldo, H. G. Henry","doi":"10.1109/CSICS.2014.6978566","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978566","url":null,"abstract":"A low loss, high isolation, broadband RF switch has been developed using a novel type of field effect transistor structure that exploits the use of a super-lattice structure in combination with a three dimensional, castellated gate to achieve excellent RF switch performance. Using an AlGaN/GaN super-lattice epitaxial layer, this Super-Lattice Castellated Field Effect Transistor (SLCFET) was used to build 1-18 GHz SPDT RF switches. Measured insertion loss of the SPDT at 10 GHz was -0.4 dB, with -35 dB of isolation and -23 dB of return loss, along with a measured linearity OIP3 value 62 dBm and a P0.1dB of 34 dBm.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131833749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978555
S. Halder, J. McMacken, J. Gering
A generic modeling topology is proposed for high power packaged GaN HFET devices leading to first pass design/modeling success. In addition to the EM environment of the package parasitics, the model considers thermal cross coupling and electrode cross coupling effects at the multi-cell device array to arrive at sufficiently accurate model. The model derived by studying a 5-cell GaN part is played back against 1,3,7 cell packaged devices from different types of GaN process to show model agreements at 0.9,2.14 and 3.5 GHz demonstrating acceptable first pass design success.
{"title":"First Pass Multi Cell Modeling Strategy for GaN Package Devices","authors":"S. Halder, J. McMacken, J. Gering","doi":"10.1109/CSICS.2014.6978555","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978555","url":null,"abstract":"A generic modeling topology is proposed for high power packaged GaN HFET devices leading to first pass design/modeling success. In addition to the EM environment of the package parasitics, the model considers thermal cross coupling and electrode cross coupling effects at the multi-cell device array to arrive at sufficiently accurate model. The model derived by studying a 5-cell GaN part is played back against 1,3,7 cell packaged devices from different types of GaN process to show model agreements at 0.9,2.14 and 3.5 GHz demonstrating acceptable first pass design success.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115475181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978570
Jun Ren, B. Song, H. Xing, Shuoqi Chen, A. Ketterson, E. Beam, T. Chou, M. Pilla, H. Tserng, Xiang Gao, P. Saunier, P. Fay
Device models to support circuit design efforts using monolithically-integrated enhancement- and depletion-mode high-speed InAlN/AlN/GaN HEMTs are reported. Physically- motivated modifications to the conventional empirical compact models have been included to enhance model accuracy over bias and temperature. The models have been extracted from DC through 110 GHz at baseplate temperatures from 25 °C through 100 °C; good agreement is obtained between measurement results and the extracted model.
{"title":"Model Development for Monolithically-Integrated E/D-Mode Millimeter-Wave InAlN/AlN/GaN HEMTs","authors":"Jun Ren, B. Song, H. Xing, Shuoqi Chen, A. Ketterson, E. Beam, T. Chou, M. Pilla, H. Tserng, Xiang Gao, P. Saunier, P. Fay","doi":"10.1109/CSICS.2014.6978570","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978570","url":null,"abstract":"Device models to support circuit design efforts using monolithically-integrated enhancement- and depletion-mode high-speed InAlN/AlN/GaN HEMTs are reported. Physically- motivated modifications to the conventional empirical compact models have been included to enhance model accuracy over bias and temperature. The models have been extracted from DC through 110 GHz at baseplate temperatures from 25 °C through 100 °C; good agreement is obtained between measurement results and the extracted model.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129336133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978540
J. Mccue, M. Casto, J. Li, P. Watson, W. Khalil
In this paper, a double-balanced Gilbert cell down-conversion mixer is demonstrated from 70-110 GHz. The wide bandwidth and high frequency are enabled by the HRL InP/Si BiCMOS process. With an fT of 300 GHz, the available 0.25 μm InP HBTs are used in the signal path while the 90 nm CMOS devices are used for biasing and gain adjustment. The fully differential circuit is implemented using two on-chip Marchand baluns feeding both the LO and RF ports. An IF buffer follows the mixer to improve matching and signal quality for testing. After de-embedding the balun and IF buffer, the mixer core achieves a peak conversion gain of 13 dB, a minimum DSB NF of 10 dB, and an OP1dB of -2 dBm while consuming 5 mA from a 3.3 V supply.
{"title":"An Active Double-Balanced Down-Conversion Mixer in InP/Si BICMOS Operating from 70-110 GHz","authors":"J. Mccue, M. Casto, J. Li, P. Watson, W. Khalil","doi":"10.1109/CSICS.2014.6978540","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978540","url":null,"abstract":"In this paper, a double-balanced Gilbert cell down-conversion mixer is demonstrated from 70-110 GHz. The wide bandwidth and high frequency are enabled by the HRL InP/Si BiCMOS process. With an fT of 300 GHz, the available 0.25 μm InP HBTs are used in the signal path while the 90 nm CMOS devices are used for biasing and gain adjustment. The fully differential circuit is implemented using two on-chip Marchand baluns feeding both the LO and RF ports. An IF buffer follows the mixer to improve matching and signal quality for testing. After de-embedding the balun and IF buffer, the mixer core achieves a peak conversion gain of 13 dB, a minimum DSB NF of 10 dB, and an OP1dB of -2 dBm while consuming 5 mA from a 3.3 V supply.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130993289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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