Pub Date : 2014-10-01DOI: 10.1109/CSICS.2014.6978553
I. Fujimori
Since the first OC-192 transceiver in CMOS was introduced in 2000, architecture and technology advancements have pushed wireline transceivers in CMOS to mainstream, even for OC-768 data rates. A diverse portfolio of multi-gigabit SerDes I/Os is now essential for large scale SOCs, not only for Networking but also Consumer applications. DSP-based transceivers with ADC frontends have forced a paradigm shift in how wireline transceivers are architected. This paper covers the evolution of CMOS wireline transceivers at Broadcom.
{"title":"Evolution of Multi-Gigabit Wireline Transceivers in CMOS","authors":"I. Fujimori","doi":"10.1109/CSICS.2014.6978553","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978553","url":null,"abstract":"Since the first OC-192 transceiver in CMOS was introduced in 2000, architecture and technology advancements have pushed wireline transceivers in CMOS to mainstream, even for OC-768 data rates. A diverse portfolio of multi-gigabit SerDes I/Os is now essential for large scale SOCs, not only for Networking but also Consumer applications. DSP-based transceivers with ADC frontends have forced a paradigm shift in how wireline transceivers are architected. This paper covers the evolution of CMOS wireline transceivers at Broadcom.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114961324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/CSICS.2014.6978537
Huiming Xu, Barry Wu, Ardy Winoto, M. Feng
An AlInP emitter ledge (EL) has been developed for a Type-II GaAsSb/InP DHBT with doping-graded base. The AlInP emitter ledge has effectively reduced emitter peripheral surface recombination current, thus improving current gain. A 0.25 x 5 μm2 device has demonstrated maximum current gain β = 24, BVCEO = 6.3 V and fT/fMAX = 480/620 GHz. RF performances of 600+ GHz Type II DHBTs with and without emitter ledge have also been compared.
{"title":"Advanced Process and Modeling on 600+ GHz Emitter Ledge Type-II GaAsSb/InP DHBT","authors":"Huiming Xu, Barry Wu, Ardy Winoto, M. Feng","doi":"10.1109/CSICS.2014.6978537","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978537","url":null,"abstract":"An AlInP emitter ledge (EL) has been developed for a Type-II GaAsSb/InP DHBT with doping-graded base. The AlInP emitter ledge has effectively reduced emitter peripheral surface recombination current, thus improving current gain. A 0.25 x 5 μm2 device has demonstrated maximum current gain β = 24, BVCEO = 6.3 V and fT/fMAX = 480/620 GHz. RF performances of 600+ GHz Type II DHBTs with and without emitter ledge have also been compared.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122898521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/CSICS.2014.6978574
Naim Ben-Hamida, C. Kurowski, R. Gibbins, J. Weng, Ted Wong, John Lindsay, H. Mah, S. Aouini, Andrew McCarthy
This paper describes an active clock distribution network for a 100G/200G coherent optical receiver. The chip has more than 1 billion transistors implemented in 32nm CMOS bulk technology with 11 metal layers. The active clock spines enabled a low-skew, low jitter, and low power clock distribution solution. In addition, a debug-friendly clocking environment provides easy observability, testing, and reconfiguration features; hence, enabling rapid time to market.
{"title":"Programmable Active Clock Spine for 100Gb/200Gb Coherent Optical Receiver Chip in 32nm CMOS","authors":"Naim Ben-Hamida, C. Kurowski, R. Gibbins, J. Weng, Ted Wong, John Lindsay, H. Mah, S. Aouini, Andrew McCarthy","doi":"10.1109/CSICS.2014.6978574","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978574","url":null,"abstract":"This paper describes an active clock distribution network for a 100G/200G coherent optical receiver. The chip has more than 1 billion transistors implemented in 32nm CMOS bulk technology with 11 metal layers. The active clock spines enabled a low-skew, low jitter, and low power clock distribution solution. In addition, a debug-friendly clocking environment provides easy observability, testing, and reconfiguration features; hence, enabling rapid time to market.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121668980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/CSICS.2014.6978550
A. Gutierrez-Aitken, K. Hennig, D. Scott, Kenneth F. Sato, Wes Chan, B. Poust, Xiang Zeng, K. Thai, Eric B. Nakamura, E. Kaneshiro, Nancy Lin, C. Monier, I. Smorchkova, B. Oyama, A. Oki, R. Kagiwada, G. Chao
Northrop Grumman Aerospace Systems (NGAS) under the Diverse Accessible Heterojunction Integration (DAHI) DARPA program is developing heterogeneous integration processes, process design kit (PDK) and thermal analysis tools to integrate deep submicron CMOS, Indium Phosphide (InP) heterojunction bipolar transistors (HBTs), Gallium Nitride (GaN) high electron mobility transistors (HEMTs) and high-Q passive technologies for advanced DoD and other government systems.
{"title":"Diverse Accessible Heterogeneous Integration (DAHI) at Northrop Grumman Aerospace Systems (NGAS)","authors":"A. Gutierrez-Aitken, K. Hennig, D. Scott, Kenneth F. Sato, Wes Chan, B. Poust, Xiang Zeng, K. Thai, Eric B. Nakamura, E. Kaneshiro, Nancy Lin, C. Monier, I. Smorchkova, B. Oyama, A. Oki, R. Kagiwada, G. Chao","doi":"10.1109/CSICS.2014.6978550","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978550","url":null,"abstract":"Northrop Grumman Aerospace Systems (NGAS) under the Diverse Accessible Heterojunction Integration (DAHI) DARPA program is developing heterogeneous integration processes, process design kit (PDK) and thermal analysis tools to integrate deep submicron CMOS, Indium Phosphide (InP) heterojunction bipolar transistors (HBTs), Gallium Nitride (GaN) high electron mobility transistors (HEMTs) and high-Q passive technologies for advanced DoD and other government systems.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134640603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/CSICS.2014.6978541
T. Nardmann, J. Krause, M. Schroter
The emitter series resistance is a very important parameter for bipolar transistors since it can have a significant impact on both the DC and high-frequency characteristics of transistors. Its accurate determination is quite difficult due to the complicated emitter material stack and the lack of suitable test structures. Thus, extraction methods that rely on transistor terminal characteristics must be used instead. In this paper, the accuracy of several widely used extraction methods for the emitter resistance has been investigated for three different type I InP DHBT technologies by applying the methods to both measured and simulated data. Since for the latter the emitter resistance is exactly known, it allows a reliable evaluation of the accuracy and the applicability of a method.
{"title":"An Evaluation of Extraction Methods for the Emitter Resistance for InP DHBTs","authors":"T. Nardmann, J. Krause, M. Schroter","doi":"10.1109/CSICS.2014.6978541","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978541","url":null,"abstract":"The emitter series resistance is a very important parameter for bipolar transistors since it can have a significant impact on both the DC and high-frequency characteristics of transistors. Its accurate determination is quite difficult due to the complicated emitter material stack and the lack of suitable test structures. Thus, extraction methods that rely on transistor terminal characteristics must be used instead. In this paper, the accuracy of several widely used extraction methods for the emitter resistance has been investigated for three different type I InP DHBT technologies by applying the methods to both measured and simulated data. Since for the latter the emitter resistance is exactly known, it allows a reliable evaluation of the accuracy and the applicability of a method.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125328767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/CSICS.2014.6978558
P. Saunier
We report the development of a new generation of GaN devices and their performance. This new E/D technology based on "Si-like" processes will offer the possibility of competing with Si-Ge and C-MOS devices for mixed-mode circuits and mm-Wave array applications. The advantage comes from their superior breakdown voltages and ft/fmax while using processes and geometries only known so far by the Si industry. We are reviewing the performances of these devices developed under the DARPA NEXT program at TriQuint and other companies (HRL). At TriQuint, 30nm self-aligned gate InAlN/AlN/GaN devices achieved simultaneous fT/fmax of 359/347GHz. Thanks to their reduced geometry, these devices make excellent low-voltage RF devices. We published excellent performances at 10GHz with up to 67-69% PAE at 6V bias and 30GHz with up to 14.4dB associated gain and 2.6W/mm, 39.6% PAE at 8V bias. The Noise Figure of these devices at 10GHz was ~0.25dB with 3V drain bias. HRL has demonstrated fT/fmax as high as 454/444GHz at Vd=3V with a 20nm gate self-aligned device. It is tempting to envision a GaN-on-Si technology based on such devices where a fabrication process fully compatible with a Si foundry would allow the use of 8" wafers but more importantly the use of a large number of interconnect layers with micron and sub-micron geometries, both unknown to the III-V world. Preliminary work has been reported by Raytheon with GaN transistors on a 200 mm GaN-on-Si wafer (grown by MBE) fabricated with Au free metallurgy.
{"title":"GaN for Next Generation Electronics","authors":"P. Saunier","doi":"10.1109/CSICS.2014.6978558","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978558","url":null,"abstract":"We report the development of a new generation of GaN devices and their performance. This new E/D technology based on \"Si-like\" processes will offer the possibility of competing with Si-Ge and C-MOS devices for mixed-mode circuits and mm-Wave array applications. The advantage comes from their superior breakdown voltages and ft/fmax while using processes and geometries only known so far by the Si industry. We are reviewing the performances of these devices developed under the DARPA NEXT program at TriQuint and other companies (HRL). At TriQuint, 30nm self-aligned gate InAlN/AlN/GaN devices achieved simultaneous fT/fmax of 359/347GHz. Thanks to their reduced geometry, these devices make excellent low-voltage RF devices. We published excellent performances at 10GHz with up to 67-69% PAE at 6V bias and 30GHz with up to 14.4dB associated gain and 2.6W/mm, 39.6% PAE at 8V bias. The Noise Figure of these devices at 10GHz was ~0.25dB with 3V drain bias. HRL has demonstrated fT/fmax as high as 454/444GHz at Vd=3V with a 20nm gate self-aligned device. It is tempting to envision a GaN-on-Si technology based on such devices where a fabrication process fully compatible with a Si foundry would allow the use of 8\" wafers but more importantly the use of a large number of interconnect layers with micron and sub-micron geometries, both unknown to the III-V world. Preliminary work has been reported by Raytheon with GaN transistors on a 200 mm GaN-on-Si wafer (grown by MBE) fabricated with Au free metallurgy.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133187054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/CSICS.2014.6978565
H. Yamazaki
This paper reviews our recent study on a linear optical modulator (LOM). The LOM has a highly linear field response, which is suitable for digital coherent optical communications systems where advanced multilevel transmission signals are generated in the electrical domain using high-speed digital-to-analog converters (DACs). A twostage lattice optical configuration enables us to compensate for the nonlinearity (sinusoidal nature) of the response of a conventional Mach-Zehnder modulator (MZM), which is an obstacle to achieving low-loss and low-distortion electro-optic conversion of the multilevel signals. We experimentally proved that the LOM has an advantage over the MZM in terms of the trade-off between the linearity and intrinsic optical-power loss.
{"title":"Linear Optical Modulator for DAC-Based Coherent Fiber Communications Systems","authors":"H. Yamazaki","doi":"10.1109/CSICS.2014.6978565","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978565","url":null,"abstract":"This paper reviews our recent study on a linear optical modulator (LOM). The LOM has a highly linear field response, which is suitable for digital coherent optical communications systems where advanced multilevel transmission signals are generated in the electrical domain using high-speed digital-to-analog converters (DACs). A twostage lattice optical configuration enables us to compensate for the nonlinearity (sinusoidal nature) of the response of a conventional Mach-Zehnder modulator (MZM), which is an obstacle to achieving low-loss and low-distortion electro-optic conversion of the multilevel signals. We experimentally proved that the LOM has an advantage over the MZM in terms of the trade-off between the linearity and intrinsic optical-power loss.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122638421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/CSICS.2014.6978560
E. Higham
GaN technology for RF applications has been widely adopted in defense applications, but commercial acceptance has been much slower. Wireless base stations seemed like the most likely commercial early adopter of GaN, but this market has been slow to take off. This paper will review the material properties of GaN material and how these translate to device parameters. Developments with incumbent LDMOS technology, along with new linearization schemes will illustrate future direction for the wireless base station market. The paper will close with forecasts for the overall power market and how quickly GaN revenue will grow.
{"title":"GaN Technology in Base Stations - Why and When?","authors":"E. Higham","doi":"10.1109/CSICS.2014.6978560","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978560","url":null,"abstract":"GaN technology for RF applications has been widely adopted in defense applications, but commercial acceptance has been much slower. Wireless base stations seemed like the most likely commercial early adopter of GaN, but this market has been slow to take off. This paper will review the material properties of GaN material and how these translate to device parameters. Developments with incumbent LDMOS technology, along with new linearization schemes will illustrate future direction for the wireless base station market. The paper will close with forecasts for the overall power market and how quickly GaN revenue will grow.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127579796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/CSICS.2014.6978545
Jeffrey K. Jones, B. Noori, J. Frei, Enver Krvavac
Doherty Amplifiers have become the standard architecture for high-efficiency cellular infrastructure applications, but most designs in production and in the field are limited in RF bandwidth (RFBW). Though it would be desirable to have Doherty amplifiers that operate over several adjacent bands, the importance of system efficiency under corrected linearity conditions has limited the deployment of wider-bandwidth Doherty amplifiers. This is particularly true where amplifiers require peak power capability of 500W or greater. This paper discusses filter design techniques related to RF power semiconductors targeted for wideband Doherty operations, as well as an amplifier technique that we call Frequency Selective Broadband (FSBB) Doherty design-this technique allows an alternative amplifier design covering multiple operating bands, without trade-offs in efficiency performance.
{"title":"Broadband Doherty Alternative with Filter Design Considerations","authors":"Jeffrey K. Jones, B. Noori, J. Frei, Enver Krvavac","doi":"10.1109/CSICS.2014.6978545","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978545","url":null,"abstract":"Doherty Amplifiers have become the standard architecture for high-efficiency cellular infrastructure applications, but most designs in production and in the field are limited in RF bandwidth (RFBW). Though it would be desirable to have Doherty amplifiers that operate over several adjacent bands, the importance of system efficiency under corrected linearity conditions has limited the deployment of wider-bandwidth Doherty amplifiers. This is particularly true where amplifiers require peak power capability of 500W or greater. This paper discusses filter design techniques related to RF power semiconductors targeted for wideband Doherty operations, as well as an amplifier technique that we call Frequency Selective Broadband (FSBB) Doherty design-this technique allows an alternative amplifier design covering multiple operating bands, without trade-offs in efficiency performance.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124944736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/CSICS.2014.6978543
A. Magnani, V. d’Alessandro, L. Codecasa, P. Zampardi, B. Moser, N. Rinaldi
This work is focused on the analysis of the dynamic thermal behavior of advanced GaAs HBTs, with particular emphasis on BiFET technologies, where pHEMTs are integrated below the conventional bipolar device. A novel highly-efficient tool is employed to determine the influence on the thermal impedance of the key layout and technology features, namely, size of the emitter and base-collector mesa, pHEMT layers, and metallization architecture. The tool relies on the multi-point moment matching algorithm, and allows CPU time and memory storage much lower than those required by commercially-available numerical software packages.
{"title":"Analysis of the Influence of Layout and Technology Parameters on the Thermal Impedance of GaAs HBT/BiFET Using a Highly-Efficient Tool","authors":"A. Magnani, V. d’Alessandro, L. Codecasa, P. Zampardi, B. Moser, N. Rinaldi","doi":"10.1109/CSICS.2014.6978543","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978543","url":null,"abstract":"This work is focused on the analysis of the dynamic thermal behavior of advanced GaAs HBTs, with particular emphasis on BiFET technologies, where pHEMTs are integrated below the conventional bipolar device. A novel highly-efficient tool is employed to determine the influence on the thermal impedance of the key layout and technology features, namely, size of the emitter and base-collector mesa, pHEMT layers, and metallization architecture. The tool relies on the multi-point moment matching algorithm, and allows CPU time and memory storage much lower than those required by commercially-available numerical software packages.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117259086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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