Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978530
M. Roberg, Bumjin Kim
This paper presents a fully integrated 6-12 GHz GaN MMIC push-pull amplifier for low harmonic drive applications. A folded Marchand balun is used to perform the unbalanced-balanced and balanced-unbalanced transformations. The three-stage push-pull amplifier provides in excess of 28 dB of small signal gain at a quiescent bias point of 25V, 200mA. The minimum saturated output power across the 6-12 GHz bandwidth is 32.3 dBm. The worst case second harmonic level under a saturated operating condition is -40 dBc, demonstrating the capability of the push-pull amplifier to suppress the even order harmonics, especially when the second harmonic is within the amplifier bandwidth.
本文提出了一种用于低谐波驱动应用的全集成6-12 GHz GaN MMIC推挽放大器。使用折叠的马尔尚平衡来执行不平衡-平衡和平衡-不平衡转换。三级推挽放大器在25V, 200mA的静态偏置点提供超过28db的小信号增益。6- 12ghz带宽的最小饱和输出功率为32.3 dBm。在饱和工作条件下，最坏情况下的二次谐波电平为-40 dBc，证明了推挽放大器抑制偶数次谐波的能力，特别是当二次谐波在放大器带宽内时。
{"title":"A 6-12 GHz Push-Pull GaN Amplifier for Low Harmonic Drive Applications","authors":"M. Roberg, Bumjin Kim","doi":"10.1109/CSICS.2014.6978530","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978530","url":null,"abstract":"This paper presents a fully integrated 6-12 GHz GaN MMIC push-pull amplifier for low harmonic drive applications. A folded Marchand balun is used to perform the unbalanced-balanced and balanced-unbalanced transformations. The three-stage push-pull amplifier provides in excess of 28 dB of small signal gain at a quiescent bias point of 25V, 200mA. The minimum saturated output power across the 6-12 GHz bandwidth is 32.3 dBm. The worst case second harmonic level under a saturated operating condition is -40 dBc, demonstrating the capability of the push-pull amplifier to suppress the even order harmonics, especially when the second harmonic is within the amplifier bandwidth.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128539949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978578
A. Tomkins, Alan Poon, E. Juntunen, A. El-Gabaly, Grigori Temkine, Yat-Loong To, C. Farnsworth, Arash Tabibiazar, M. Fakharzadeh, S. Jafarlou, Hatem Tawfik, Brad Lynch, M. Tazlauanu, Ronald Glibbery
A silicon-based 60-GHz chipset is described that addresses both the consumer and infrastructure backhaul requirements. An antenna-integrated packaged solution includes a WiGig compliant transceiver and > 8dBi gain antennas. Low-loss wave-guide modules are also shown that integrate the same transceiver with a <; 1dB loss WR-15 wave-guide transition. A fully WiGig compliant baseband IC is described integrating a USB 3.0 interface and a full analog front-end interface to a radio transceiver. Finally, the next-generation transceiver IC is described that features enhanced output power, > +16 dBm, and newly optimized fast-locking AGC operation.
{"title":"Silicon Wireless Systems for 60-GHz Consumer and Infrastructure Applications","authors":"A. Tomkins, Alan Poon, E. Juntunen, A. El-Gabaly, Grigori Temkine, Yat-Loong To, C. Farnsworth, Arash Tabibiazar, M. Fakharzadeh, S. Jafarlou, Hatem Tawfik, Brad Lynch, M. Tazlauanu, Ronald Glibbery","doi":"10.1109/CSICS.2014.6978578","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978578","url":null,"abstract":"A silicon-based 60-GHz chipset is described that addresses both the consumer and infrastructure backhaul requirements. An antenna-integrated packaged solution includes a WiGig compliant transceiver and > 8dBi gain antennas. Low-loss wave-guide modules are also shown that integrate the same transceiver with a <; 1dB loss WR-15 wave-guide transition. A fully WiGig compliant baseband IC is described integrating a USB 3.0 interface and a full analog front-end interface to a radio transceiver. Finally, the next-generation transceiver IC is described that features enhanced output power, > +16 dBm, and newly optimized fast-locking AGC operation.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124864498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978538
S. Menezo, H. Duprez, A. Descos, D. Bordel, L. Sanchez, P. Brianceau, L. Fulbert, V. Carron, B. Ben Bakir
In the absence of practically efficient lasers achievable directly in Silicon or other group IV materials, Si-photonic transmitter sources must be made by "Hybrid integration" of III-V chips or "Heterogeneous integration" with III-V gain materials. "Hybrid integration" technologies consist in integrating processed (and finished) chips in a photonic microsystem. One commercial solution (from LUXTERA) makes use of a InP-bulk- processed laser-chip [3]. The laser chip is attached to the PIC, and its light is coupled into the PIC- waveguide by means of a lens, followed by an optical isolator, and a mirror for directing the light to a surface grating coupler in the Si-PIC. Other approaches (from KOTURA/ORACLE) consist in but-coupling a III-V- semiconductor reflective-SOA to the PIC-3μm- thick-Si-waveguide that comprises a Bragg-mirror for defining the laser cavity [4]. This forms an external-cavity DBR laser, with reported Waveguide-Coupled Wall-Plug-Efficiencies (WC-WPE) for the uncooled lasers of up to 9.5% at powers of 6 mW. In spite of the good demonstrated performances, this solution requires an accurate alignment between the R-SOA and the Si-PIC, limiting the capability for a low cost fabrication. As a more economical route that we opted for, "Heterogeneous integration" technologies were proposed [5], [6] together with new laser architectures. An InP-wafer having the III-V-gain- layers grown on top is bonded with loose alignment requirements (~50μm), the III-V gain-layers facing down to the bottom Silicon-On- Insulator (SOI) wafer on which silicon waveguides are pre- processed. In a more economical route, the InP-substrate having the laser III-V-gain- layers on top is first diced, and the dies are bonded where needed. Then the InP-substrate is removed, and the laser process is continued on the remaining III-V gain epi-layers, in a regular wafer level process flow. Putting the expensive III-V-gain material only where needed saves on cost. In addition to lower cost, photonic integration promises improved reliability and performances and reduced footprints over discrete components systems. This paper will report on our recent advances on both, 1) the developed III-V on Silicon lasers (DBR and DFB types) built up from heterogeneous integration, and, 2) the development of the integration technology for processing the lasers on 200mm-wafers, with industrial CMOS tools at very low cost.
{"title":"Advances on III-V on Silicon DBR and DFB Lasers for WDM Optical Interconnects and Associated Heterogeneous Integration 200mm-Wafer-Scale Technology","authors":"S. Menezo, H. Duprez, A. Descos, D. Bordel, L. Sanchez, P. Brianceau, L. Fulbert, V. Carron, B. Ben Bakir","doi":"10.1109/CSICS.2014.6978538","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978538","url":null,"abstract":"In the absence of practically efficient lasers achievable directly in Silicon or other group IV materials, Si-photonic transmitter sources must be made by \"Hybrid integration\" of III-V chips or \"Heterogeneous integration\" with III-V gain materials. \"Hybrid integration\" technologies consist in integrating processed (and finished) chips in a photonic microsystem. One commercial solution (from LUXTERA) makes use of a InP-bulk- processed laser-chip [3]. The laser chip is attached to the PIC, and its light is coupled into the PIC- waveguide by means of a lens, followed by an optical isolator, and a mirror for directing the light to a surface grating coupler in the Si-PIC. Other approaches (from KOTURA/ORACLE) consist in but-coupling a III-V- semiconductor reflective-SOA to the PIC-3μm- thick-Si-waveguide that comprises a Bragg-mirror for defining the laser cavity [4]. This forms an external-cavity DBR laser, with reported Waveguide-Coupled Wall-Plug-Efficiencies (WC-WPE) for the uncooled lasers of up to 9.5% at powers of 6 mW. In spite of the good demonstrated performances, this solution requires an accurate alignment between the R-SOA and the Si-PIC, limiting the capability for a low cost fabrication. As a more economical route that we opted for, \"Heterogeneous integration\" technologies were proposed [5], [6] together with new laser architectures. An InP-wafer having the III-V-gain- layers grown on top is bonded with loose alignment requirements (~50μm), the III-V gain-layers facing down to the bottom Silicon-On- Insulator (SOI) wafer on which silicon waveguides are pre- processed. In a more economical route, the InP-substrate having the laser III-V-gain- layers on top is first diced, and the dies are bonded where needed. Then the InP-substrate is removed, and the laser process is continued on the remaining III-V gain epi-layers, in a regular wafer level process flow. Putting the expensive III-V-gain material only where needed saves on cost. In addition to lower cost, photonic integration promises improved reliability and performances and reduced footprints over discrete components systems. This paper will report on our recent advances on both, 1) the developed III-V on Silicon lasers (DBR and DFB types) built up from heterogeneous integration, and, 2) the development of the integration technology for processing the lasers on 200mm-wafers, with industrial CMOS tools at very low cost.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122521936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978586
Y. Niida, Y. Kamada, T. Ohki, S. Ozaki, K. Makiyama, N. Okamoto, Masaru Sato, S. Masuda, Keiji Watanabe
A new design methodology was proposed to obtain wide-bandwidth and flat-group-delay reactive-matching GaN HEMT MMIC amplifiers. Frequency dependence of the optimal source and load impedance of a GaN HEMT are derived as polynomial equations and matching circuits are designed by small signal simulation without the use of large-signal transistor model and large-signal simulation. Fabricated GaN HEMT MMIC amplifiers, which show a small deviation of Pout and PAE in the range of 8-18 GHz, prove that our methodology is suitable for the design of a wide-bandwidth MMIC amplifier.
{"title":"X-Ku Wide-Bandwidth GaN HEMT MMIC Amplifier with Small Deviation of Output Power and PAE","authors":"Y. Niida, Y. Kamada, T. Ohki, S. Ozaki, K. Makiyama, N. Okamoto, Masaru Sato, S. Masuda, Keiji Watanabe","doi":"10.1109/CSICS.2014.6978586","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978586","url":null,"abstract":"A new design methodology was proposed to obtain wide-bandwidth and flat-group-delay reactive-matching GaN HEMT MMIC amplifiers. Frequency dependence of the optimal source and load impedance of a GaN HEMT are derived as polynomial equations and matching circuits are designed by small signal simulation without the use of large-signal transistor model and large-signal simulation. Fabricated GaN HEMT MMIC amplifiers, which show a small deviation of Pout and PAE in the range of 8-18 GHz, prove that our methodology is suitable for the design of a wide-bandwidth MMIC amplifier.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124808036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978549
Ryan M. Clement, Leigh E. Milner, E. Convert, L. Hall, M. Parker, M. G. McCulloch, A. Dadello, Benny Wu, J. Harvey, A. Parker, S. Mahon
Direct down-conversion receivers at Ka band in GaAs and SiGe are measured and analysed with particular attention to linearity. The GaAs receiver is observed to have the superior overall linearity although SiGe has the better second-order behaviour. The linearity is discussed with respect to the requirements of point-to-point radio and for the first time, to the authors' knowledge, an explanation is established for the effect of third-order distortion in the LNA on the second-order distortion from the complete receiver.
{"title":"Direct Down-Conversion 38 GHz GaAs and SiGe Receivers","authors":"Ryan M. Clement, Leigh E. Milner, E. Convert, L. Hall, M. Parker, M. G. McCulloch, A. Dadello, Benny Wu, J. Harvey, A. Parker, S. Mahon","doi":"10.1109/CSICS.2014.6978549","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978549","url":null,"abstract":"Direct down-conversion receivers at Ka band in GaAs and SiGe are measured and analysed with particular attention to linearity. The GaAs receiver is observed to have the superior overall linearity although SiGe has the better second-order behaviour. The linearity is discussed with respect to the requirements of point-to-point radio and for the first time, to the authors' knowledge, an explanation is established for the effect of third-order distortion in the LNA on the second-order distortion from the complete receiver.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130594290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978582
M. Ozalas
Thermal issues pose significant challenges for today's RF power amplifier designs. Recently, layout-based electro-thermal simulation tools have become widely available across the industry. While these tools are most commonly used for device-level reliability and lifetime verification, electro-thermal simulation can also enable engineers to gain new insight into the performance effects that are brought on by cross-circuit thermal coupling in RF power amplifiers. This paper describes the use of electro-thermal simulation to understand, predict, and account for cross-circuit thermal coupling in a commercial HBT power amplifier. Specifically, electro-thermal analysis is used to analyze how thermal coupling impacts gain compression and low frequency memory effects.
{"title":"The Impact of Electro-Thermal Coupling on HBT Power Amplifiers","authors":"M. Ozalas","doi":"10.1109/CSICS.2014.6978582","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978582","url":null,"abstract":"Thermal issues pose significant challenges for today's RF power amplifier designs. Recently, layout-based electro-thermal simulation tools have become widely available across the industry. While these tools are most commonly used for device-level reliability and lifetime verification, electro-thermal simulation can also enable engineers to gain new insight into the performance effects that are brought on by cross-circuit thermal coupling in RF power amplifiers. This paper describes the use of electro-thermal simulation to understand, predict, and account for cross-circuit thermal coupling in a commercial HBT power amplifier. Specifically, electro-thermal analysis is used to analyze how thermal coupling impacts gain compression and low frequency memory effects.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132686860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978552
G. Sasso, C. Maneux, J. Boeck, V. d’Alessandro, K. Aufinger, T. Zimmer, N. Rinaldi
Hot-carrier degradation analysis and modeling of 240/380 GHz fT/fMAX SiGe HBTs are addressed. A proper stress bias setup is proposed, suitable for the evaluation of RF performance during stress interruption. The impact of stress conditions, lateral scaling and device layout is discussed. An analytical model is proposed, which predicts base current degradation, including its dependence upon stress voltage, stress duration, and emitter geometry, and contributes to understand the physical background of the phenomena.
{"title":"Evaluation and Modeling of Voltage Stress-Induced Hot Carrier Effects in High-Speed SiGe HBTs","authors":"G. Sasso, C. Maneux, J. Boeck, V. d’Alessandro, K. Aufinger, T. Zimmer, N. Rinaldi","doi":"10.1109/CSICS.2014.6978552","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978552","url":null,"abstract":"Hot-carrier degradation analysis and modeling of 240/380 GHz fT/fMAX SiGe HBTs are addressed. A proper stress bias setup is proposed, suitable for the evaluation of RF performance during stress interruption. The impact of stress conditions, lateral scaling and device layout is discussed. An analytical model is proposed, which predicts base current degradation, including its dependence upon stress voltage, stress duration, and emitter geometry, and contributes to understand the physical background of the phenomena.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123314318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978522
N. El-Hinnawy, P. Borodulin, E. B. Jones, B. Wagner, M. King, J. Mason, J. Bain, J. Paramesh, T. E. Schlesinger, R. Howell, Michael J. Lee, R. Young
Improvements to the GeTe inline phase-change switch (IPCS) technology have resulted in a record-performing radio-frequency (RF) switch. An ON-state resistance of 0.9 Ω (0.027 Ω·mm) with an OFF-state capacitance and resistance of 14.1 fF and 30 kΩ, respectively, were measured, resulting in a calculated switch cutoff frequency (Fco) of 12.5 THz. This represents the highest reported Fco achieved with chalcogenide switches to date. The threshold voltage (Vth) for these devices was measured at 3V and the measured third-order intercept point (TOI) was 72 dBm. Single-pole, single-throw (SPST) switches were fabricated, with a measured insertion loss less than 0.15 dB in the ON-state, and 15dB isolation in the OFF-state at 18 GHz. Single-pole, double-throw (SPDT) switches were fabricated using a complete backside process with through-substrate vias, with a measured insertion loss 0.25 dB, and 35dB isolation.
{"title":"12.5 THz Fco GeTe Inline Phase-Change Switch Technology for Reconfigurable RF and Switching Applications","authors":"N. El-Hinnawy, P. Borodulin, E. B. Jones, B. Wagner, M. King, J. Mason, J. Bain, J. Paramesh, T. E. Schlesinger, R. Howell, Michael J. Lee, R. Young","doi":"10.1109/CSICS.2014.6978522","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978522","url":null,"abstract":"Improvements to the GeTe inline phase-change switch (IPCS) technology have resulted in a record-performing radio-frequency (RF) switch. An ON-state resistance of 0.9 Ω (0.027 Ω·mm) with an OFF-state capacitance and resistance of 14.1 fF and 30 kΩ, respectively, were measured, resulting in a calculated switch cutoff frequency (Fco) of 12.5 THz. This represents the highest reported Fco achieved with chalcogenide switches to date. The threshold voltage (Vth) for these devices was measured at 3V and the measured third-order intercept point (TOI) was 72 dBm. Single-pole, single-throw (SPST) switches were fabricated, with a measured insertion loss less than 0.15 dB in the ON-state, and 15dB isolation in the OFF-state at 18 GHz. Single-pole, double-throw (SPDT) switches were fabricated using a complete backside process with through-substrate vias, with a measured insertion loss 0.25 dB, and 35dB isolation.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117016797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978577
M. Webster, C. Appel, Prakash Gothoskar, S. Sunder, B. Dama, K. Shastri
We describe a silicon photonic optical modulator based on a MOS-capacitor and a low power 1V CMOS inverter-based driver IC. In an MZI configuration, this efficient modulator and driver IC combination can produce a 9dB extinction ratio at 28 Gbps, at a wavelength of 1310nm.
{"title":"Silicon Photonic Modulator Based on a MOS-Capacitor and a CMOS Driver","authors":"M. Webster, C. Appel, Prakash Gothoskar, S. Sunder, B. Dama, K. Shastri","doi":"10.1109/CSICS.2014.6978577","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978577","url":null,"abstract":"We describe a silicon photonic optical modulator based on a MOS-capacitor and a low power 1V CMOS inverter-based driver IC. In an MZI configuration, this efficient modulator and driver IC combination can produce a 9dB extinction ratio at 28 Gbps, at a wavelength of 1310nm.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128919325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978568
Y. Won, Farzad Houshmand, D. Agonafer, M. Asheghi, K. Goodson
The high power densities targeted for GaN HEMT on SiC technology can dramatically increase the performance of radar systems. The increasing power will require improved heat removal technologies associated with conduction and convection. Here we explore combined cooling technologies based on SiC substrate and SiC or Cu microstructures, which improve the thermal performance of high power devices.
{"title":"Microfluidic Heat Exchangers for High Power Density GaN on SiC","authors":"Y. Won, Farzad Houshmand, D. Agonafer, M. Asheghi, K. Goodson","doi":"10.1109/CSICS.2014.6978568","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978568","url":null,"abstract":"The high power densities targeted for GaN HEMT on SiC technology can dramatically increase the performance of radar systems. The increasing power will require improved heat removal technologies associated with conduction and convection. Here we explore combined cooling technologies based on SiC substrate and SiC or Cu microstructures, which improve the thermal performance of high power devices.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125319996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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