Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978567
D. Green, C. L. Dohrman, A. Kane, Tsu-Hsi Chang
The DARPA Microsystems Technology Office is developing revolutionary materials, devices, and integration techniques for meeting the RF integrated circuit performance requirements for advanced modern RF systems. DARPA is enabling these systems through systematic development of materials and devices, circuits, and integration technologies for compound semiconductors. The DARPA Nitride Electronic Next-Generation Technology (NEXT) program is developing high performance nitride transistors for high-speed RF, analog and mixed signal electronics, thus overcoming the Johnson figure of merit limits to achieving simultaneous high-speed operation and high breakdown voltage. The DARPA Microscale Power Conversion (MPC) program is developing nitride-based technology to enable dynamic envelope-tracking power conversion embedded in RF radiating elements. The DARPA Diverse Accessible Heterogeneous Integration (DAHI) program is developing transistor-scale heterogeneous integration processes to intimately combine advanced compound semiconductor (CS) devices, as well as other emerging materials and devices, with high-density silicon CMOS technology. Taken together, these programs are addressing many of the critical challenges for next-generation RF modules and seek to revolutionize DoD capabilities in this area.
{"title":"Materials and Integration Strategies for Modern RF Integrated Circuits","authors":"D. Green, C. L. Dohrman, A. Kane, Tsu-Hsi Chang","doi":"10.1109/CSICS.2014.6978567","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978567","url":null,"abstract":"The DARPA Microsystems Technology Office is developing revolutionary materials, devices, and integration techniques for meeting the RF integrated circuit performance requirements for advanced modern RF systems. DARPA is enabling these systems through systematic development of materials and devices, circuits, and integration technologies for compound semiconductors. The DARPA Nitride Electronic Next-Generation Technology (NEXT) program is developing high performance nitride transistors for high-speed RF, analog and mixed signal electronics, thus overcoming the Johnson figure of merit limits to achieving simultaneous high-speed operation and high breakdown voltage. The DARPA Microscale Power Conversion (MPC) program is developing nitride-based technology to enable dynamic envelope-tracking power conversion embedded in RF radiating elements. The DARPA Diverse Accessible Heterogeneous Integration (DAHI) program is developing transistor-scale heterogeneous integration processes to intimately combine advanced compound semiconductor (CS) devices, as well as other emerging materials and devices, with high-density silicon CMOS technology. Taken together, these programs are addressing many of the critical challenges for next-generation RF modules and seek to revolutionize DoD capabilities in this area.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123975053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978554
J. Hartmann
Electronics is more and more pervasive in everyday life: smartphones, connected cars, Internet of Things... All this is not only about mobile energy efficient technologies: it is wireless and wireline connectivity, sensors. UTBB FD-SOI (Ultra Thin Body and Buried-oxide Fully Depleted Silicon On Insulator) is a planar semiconductor technology that introduced the advantages of fully depleted transistors from the 28nm technology node, which is cost optimal, allowing joining the advantages of a general purpose high speed technology with the ones of a low power one. The paper describes the development of the FD-SOI technology, the choice of devices centering, and their main characteristics, especially suited for high speed energy efficient operation, even in low voltage conditions, thanks to the their intrinsic characteristics offered by being fully depleted. Those, are not limited to digital logic devices, but extend to memory bit-cells (fast, low leakage, and operating at low voltage) and the exceptional analog characteristics of devices.
电子产品在日常生活中越来越普遍:智能手机、联网汽车、物联网……所有这一切不仅仅是关于移动节能技术:它是无线和有线连接，传感器。UTBB FD-SOI (Ultra Thin Body and buredoxide Fully贫化硅绝缘体)是一种平面半导体技术，它从28nm技术节点引入了完全耗尽晶体管的优势，这是成本最优的，允许将通用高速技术的优势与低功耗技术的优势结合起来。本文介绍了FD-SOI技术的发展，器件定心的选择，以及它们的主要特性，特别是适用于高速节能运行，即使在低电压条件下，由于它们的内在特性提供了完全耗尽。这些并不局限于数字逻辑器件，而是扩展到存储位单元(快速、低漏和在低电压下工作)和器件的特殊模拟特性。
{"title":"FD-SOI Technology Development and Key Devices Characteristics for Fast, Power Efficient, Low Voltage SoCs","authors":"J. Hartmann","doi":"10.1109/CSICS.2014.6978554","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978554","url":null,"abstract":"Electronics is more and more pervasive in everyday life: smartphones, connected cars, Internet of Things... All this is not only about mobile energy efficient technologies: it is wireless and wireline connectivity, sensors. UTBB FD-SOI (Ultra Thin Body and Buried-oxide Fully Depleted Silicon On Insulator) is a planar semiconductor technology that introduced the advantages of fully depleted transistors from the 28nm technology node, which is cost optimal, allowing joining the advantages of a general purpose high speed technology with the ones of a low power one. The paper describes the development of the FD-SOI technology, the choice of devices centering, and their main characteristics, especially suited for high speed energy efficient operation, even in low voltage conditions, thanks to the their intrinsic characteristics offered by being fully depleted. Those, are not limited to digital logic devices, but extend to memory bit-cells (fast, low leakage, and operating at low voltage) and the exceptional analog characteristics of devices.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121507272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978548
P. Ye
The rise of two-dimensional (2D) crystals has given new challenges and opportunities to the device research. The semiconducting MoS2 as n-channel and few-layer phosphorene as p-channel have been considered as promising ultra-thin body channels for future microelectronic and optoelectronic devices. In this paper, we focus on the fundamental device properties of these 2D transistors. In the first part of the paper, we demonstrate high-performance MoS2 FETs with record drain current of 460 mA/mm and record low contact resistance of 0.5 Ω·mm enabled by molecular chemical doping of 1,2 dichloroethane (DCE). In the second part of the paper, we introduce a new p-type 2D material called phosphorene which is one monolayer of layered black phosphorus (BP). At room temperature, the few-layer phosphorene field-effect transistors with 1.0 μm channel length display a high on-current of 194 mA/mm, a high hole field-effect mobility of 286 cm2/V·s, and an on/off ratio up to 104. We demonstrate the possibility of phosphorene integration by constructing the first 2D CMOS inverter of phosphorene PMOS and MoS2 NMOS transistors and the first BP/MoS2 PN diode for photonic applications.
{"title":"Device Perspective on 2D Materials","authors":"P. Ye","doi":"10.1109/CSICS.2014.6978548","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978548","url":null,"abstract":"The rise of two-dimensional (2D) crystals has given new challenges and opportunities to the device research. The semiconducting MoS2 as n-channel and few-layer phosphorene as p-channel have been considered as promising ultra-thin body channels for future microelectronic and optoelectronic devices. In this paper, we focus on the fundamental device properties of these 2D transistors. In the first part of the paper, we demonstrate high-performance MoS2 FETs with record drain current of 460 mA/mm and record low contact resistance of 0.5 Ω·mm enabled by molecular chemical doping of 1,2 dichloroethane (DCE). In the second part of the paper, we introduce a new p-type 2D material called phosphorene which is one monolayer of layered black phosphorus (BP). At room temperature, the few-layer phosphorene field-effect transistors with 1.0 μm channel length display a high on-current of 194 mA/mm, a high hole field-effect mobility of 286 cm2/V·s, and an on/off ratio up to 104. We demonstrate the possibility of phosphorene integration by constructing the first 2D CMOS inverter of phosphorene PMOS and MoS2 NMOS transistors and the first BP/MoS2 PN diode for photonic applications.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129011992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978569
K.K.-S. Kong, M. Kao, S. Nayak
We demonstrate a compact and efficient Ka-band high power amplifier with output power of 34.5dBm at 30 GHz by using 0.15 μm GaN technology. This paper reports record compact area of 2.38 mm^2 in a Ka-band high power amplifier (HPA) class. We employed 0.15 μm GaN process on 50 μm thick SiC substrate technology to achieve high output power with high efficiency and compact design. The advantage of a GaN PA in commercial millimeter-wave market is illustrated by comparing it to similar GaAs power amplifiers.
{"title":"Miniaturization of Ka-Band High Power Amplifier by 0.15 µm GaN MMIC Technology","authors":"K.K.-S. Kong, M. Kao, S. Nayak","doi":"10.1109/CSICS.2014.6978569","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978569","url":null,"abstract":"We demonstrate a compact and efficient Ka-band high power amplifier with output power of 34.5dBm at 30 GHz by using 0.15 μm GaN technology. This paper reports record compact area of 2.38 mm^2 in a Ka-band high power amplifier (HPA) class. We employed 0.15 μm GaN process on 50 μm thick SiC substrate technology to achieve high output power with high efficiency and compact design. The advantage of a GaN PA in commercial millimeter-wave market is illustrated by comparing it to similar GaAs power amplifiers.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131410367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978579
Bin Hou, Yibing Zhao, Eric Newman, Shuyun Zhang
A monolithic integrated single chip RF variable gain low noise amplifier (VGLNA) based on GaAs BiFET technology is demonstrated in this work. The LNA could be operated from 700MHz to 3GHz. The measured NF is 1dB at both 975MHz and 1.75GHz. The gain of the VGLNA can be varied from a maximum of 36dB down to -13dB at 1.75GHz. Measured Output IP3 is 38.4dBm and measured Output 1dB compression is greater than 27dBm at 1.75GHz at maximum gain. The measured input return loss is better than 14dB across the full gain range. The single die VGLNA is implemented in a 5×5mm LFCSP package. It draws 265mA on a 5V supply.
{"title":"Single Chip RF Variable Gain Low Noise Amplifier","authors":"Bin Hou, Yibing Zhao, Eric Newman, Shuyun Zhang","doi":"10.1109/CSICS.2014.6978579","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978579","url":null,"abstract":"A monolithic integrated single chip RF variable gain low noise amplifier (VGLNA) based on GaAs BiFET technology is demonstrated in this work. The LNA could be operated from 700MHz to 3GHz. The measured NF is 1dB at both 975MHz and 1.75GHz. The gain of the VGLNA can be varied from a maximum of 36dB down to -13dB at 1.75GHz. Measured Output IP3 is 38.4dBm and measured Output 1dB compression is greater than 27dBm at 1.75GHz at maximum gain. The measured input return loss is better than 14dB across the full gain range. The single die VGLNA is implemented in a 5×5mm LFCSP package. It draws 265mA on a 5V supply.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125002897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978526
Z. Griffith, M. Urteaga, P. Rowell, R. Pierson
A 69.5-94.0GHz solid-state power amplifier MMIC is presented in 250nm InP HBT, where from 76-94GHz it demonstrates >200mW Pout with simultaneous >23.5% PAE, 11dB compressed gain and 694mW PDC. At 86GHz operation, 232mW Pout with peak 28.9% PAE is observed - this corresponds to 1.21W/mm linear power density. This 2-stage amplifier has a flat S21 mid-band gain of 14-15dB, and the 1dB small-signal gain roll-off is between 66-96GHz. The large-signal Psat bandwidth is between 69.5-94GHz. This SSPA utilizes a novel, compact power cell topology developed for multi-finger HBTs, which overcomes the inability of the RF output interconnects and combiners to carry the high DC bias currents required by the HBT PA cells in the thin-film microstrip interconnect. Across the 76-94GHz bandwidth, P1dB gain compression Pout is >118mW which corresponds to ≥ 14.5% PAE; this is a relevant RF operating point where higher linearity operation may be required. This work improves upon the state-of-the-art for E-, and W-Band SSPAs by demonstrating 6x higher bandwidth (24.5GHz largesignal bandwidth) while having high PAE > 23.5%. This compact approach can permit an additional 4× or 8× power combining and in-turn a monolithic 1-1.5W Pout SSPA in this 250nm InP HBT technology at Eand W-band.
{"title":"A >0mW SSPA from 76-94GHz, with Peak 28.9% PAE at 86GHz","authors":"Z. Griffith, M. Urteaga, P. Rowell, R. Pierson","doi":"10.1109/CSICS.2014.6978526","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978526","url":null,"abstract":"A 69.5-94.0GHz solid-state power amplifier MMIC is presented in 250nm InP HBT, where from 76-94GHz it demonstrates >200mW Pout with simultaneous >23.5% PAE, 11dB compressed gain and 694mW PDC. At 86GHz operation, 232mW Pout with peak 28.9% PAE is observed - this corresponds to 1.21W/mm linear power density. This 2-stage amplifier has a flat S21 mid-band gain of 14-15dB, and the 1dB small-signal gain roll-off is between 66-96GHz. The large-signal Psat bandwidth is between 69.5-94GHz. This SSPA utilizes a novel, compact power cell topology developed for multi-finger HBTs, which overcomes the inability of the RF output interconnects and combiners to carry the high DC bias currents required by the HBT PA cells in the thin-film microstrip interconnect. Across the 76-94GHz bandwidth, P1dB gain compression Pout is >118mW which corresponds to ≥ 14.5% PAE; this is a relevant RF operating point where higher linearity operation may be required. This work improves upon the state-of-the-art for E-, and W-Band SSPAs by demonstrating 6x higher bandwidth (24.5GHz largesignal bandwidth) while having high PAE > 23.5%. This compact approach can permit an additional 4× or 8× power combining and in-turn a monolithic 1-1.5W Pout SSPA in this 250nm InP HBT technology at Eand W-band.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129731516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978528
Z. Griffith, M. Urteaga, P. Rowell, R. Pierson
A 3-stage, 16-way PA-cell combined InP HBT solidstate power amplifier MMIC is presented demonstrating 23.2dBm (208.7mW) Pout at 210GHz to 21.0dBm (126.0mW) at 235GHz for 10dBm Pin - this represents 13.2-11.0dB large-signal gain. The total high-power bandwidth of this SSPA is between 190.8-237GHz. The amplifier has 24.3-26.7dB S21 gain from 206243GHz. The total PDC is 5.81W. A power-cascode cell topology is used for the PA unit cell, which is used to generate a 3-Stage, 4Cell output combined SSPA - then four of these 4-Cell SSPAs are combined using low insertion loss Wilkinson dividers and combiners to realize the overall 16-way PA cell combined MMIC. This is the first reported SSPA MMIC demonstrating > 200mW Pout above 200GHz operation. The output powers from this work across 190.8-237GHz are the highest values reported from an SSPA MMIC and improves upon state-of-the-art by 1.16-1.6× from 190.8-225GHz and by 1.6× from 230-235GHz. This result closely meets or exceeds across the same frequency operation the highest Pout reported from a solid-state based PA, a four-chip waveguide-block combined module.
{"title":"A 23.2dBm at 210GHz to 21.0dBm at 235GHz 16-Way PA-Cell Combined InP HBT SSPA MMIC","authors":"Z. Griffith, M. Urteaga, P. Rowell, R. Pierson","doi":"10.1109/CSICS.2014.6978528","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978528","url":null,"abstract":"A 3-stage, 16-way PA-cell combined InP HBT solidstate power amplifier MMIC is presented demonstrating 23.2dBm (208.7mW) Pout at 210GHz to 21.0dBm (126.0mW) at 235GHz for 10dBm Pin - this represents 13.2-11.0dB large-signal gain. The total high-power bandwidth of this SSPA is between 190.8-237GHz. The amplifier has 24.3-26.7dB S21 gain from 206243GHz. The total PDC is 5.81W. A power-cascode cell topology is used for the PA unit cell, which is used to generate a 3-Stage, 4Cell output combined SSPA - then four of these 4-Cell SSPAs are combined using low insertion loss Wilkinson dividers and combiners to realize the overall 16-way PA cell combined MMIC. This is the first reported SSPA MMIC demonstrating > 200mW Pout above 200GHz operation. The output powers from this work across 190.8-237GHz are the highest values reported from an SSPA MMIC and improves upon state-of-the-art by 1.16-1.6× from 190.8-225GHz and by 1.6× from 230-235GHz. This result closely meets or exceeds across the same frequency operation the highest Pout reported from a solid-state based PA, a four-chip waveguide-block combined module.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126737577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978559
A. Margomenos, A. Kurdoghlian, M. Micovic, K. Shinohara, D. Brown, A. Corrion, H. Moyer, S. Burnham, D. Regan, R. Grabar, C. Mcguire, M. Wetzel, R. Bowen, P. Chen, H. Tai, A. Schmitz, H. Fung, A. Fung, D. Chow
Highly scaled GaN T-gate technology offers devices with high ft/fMAX, and low minimum noise figure while still maintaining high breakdown voltage and high linearity typical for GaN technology. In this paper we report an E-band GaN power amplifier (PA) with output power (Pout) of 1.3 W at power added efficiency (PAE) of 27% and a 65-110 GHz ultra-wideband low noise amplifier (LNA). We also report the first G-band GaN amplifier capable of producing output power density of 296mW/mm at 180 GHz. All these components were realized with a 40 nm T-gate process (ft= 200 GHz, fMAX= 400 GHz, Vbrk > 40V) which can enable the next generation of transmitter and receiver components that meet or exceed performance reported by competing device technologies while maintaining > 5x higher breakdown voltage, higher linearity, dynamic range and RF survivability.
{"title":"GaN Technology for E, W and G-Band Applications","authors":"A. Margomenos, A. Kurdoghlian, M. Micovic, K. Shinohara, D. Brown, A. Corrion, H. Moyer, S. Burnham, D. Regan, R. Grabar, C. Mcguire, M. Wetzel, R. Bowen, P. Chen, H. Tai, A. Schmitz, H. Fung, A. Fung, D. Chow","doi":"10.1109/CSICS.2014.6978559","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978559","url":null,"abstract":"Highly scaled GaN T-gate technology offers devices with high ft/fMAX, and low minimum noise figure while still maintaining high breakdown voltage and high linearity typical for GaN technology. In this paper we report an E-band GaN power amplifier (PA) with output power (Pout) of 1.3 W at power added efficiency (PAE) of 27% and a 65-110 GHz ultra-wideband low noise amplifier (LNA). We also report the first G-band GaN amplifier capable of producing output power density of 296mW/mm at 180 GHz. All these components were realized with a 40 nm T-gate process (ft= 200 GHz, fMAX= 400 GHz, Vbrk > 40V) which can enable the next generation of transmitter and receiver components that meet or exceed performance reported by competing device technologies while maintaining > 5x higher breakdown voltage, higher linearity, dynamic range and RF survivability.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129215781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978562
J. Godin, J. Dupuy, F. Jorge, F. Blache, M. Riet, V. Nodjiadjim, P. Berdaguer, B. Duval, A. Konczykowska
This paper reports on very high speed large swing drivers suitable for the generation of high symbol rate spectrally efficient optical transmission signals. To accommodate available data rate, these circuits integrate multiplexing stages. Fabricated using our InP DHBT technology (FT and FMAX >300 GHz, BVCE0 ~5 V), these circuits include NRZ and Multi-Level drivers; they have been used to generate OOK, QPSK and QAM signals in optical transmission experiments at bitrates beyond 100 Gbps.
{"title":"InP DHBT Mux-Drivers for Very High Symbol Rate Optical Communications","authors":"J. Godin, J. Dupuy, F. Jorge, F. Blache, M. Riet, V. Nodjiadjim, P. Berdaguer, B. Duval, A. Konczykowska","doi":"10.1109/CSICS.2014.6978562","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978562","url":null,"abstract":"This paper reports on very high speed large swing drivers suitable for the generation of high symbol rate spectrally efficient optical transmission signals. To accommodate available data rate, these circuits integrate multiplexing stages. Fabricated using our InP DHBT technology (FT and FMAX >300 GHz, BVCE0 ~5 V), these circuits include NRZ and Multi-Level drivers; they have been used to generate OOK, QPSK and QAM signals in optical transmission experiments at bitrates beyond 100 Gbps.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130195747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-18DOI: 10.1109/CSICS.2014.6978575
D. Agonafer, J. Palko, Y. Won, K. Lopez, Thomas J. Dusseault, Julie Gires, M. Asheghi, J. Santiago, K. Goodson
High power density GaN HEMT technology can increase the capability of defense electronics systems with the reduction of CSWaP. However, thermal limitations have currently limited the inherent capabilities of this technology where transistor-level power densities that exceed 10 kW/cm2 are electrically feasible. This paper introduces the concept of an evaporative microcooling device utilizing some of the current two-phase vapor separation technologies currently being developed for water and dielectric liquids.
{"title":"Progress on Phase Separation Microfluidics","authors":"D. Agonafer, J. Palko, Y. Won, K. Lopez, Thomas J. Dusseault, Julie Gires, M. Asheghi, J. Santiago, K. Goodson","doi":"10.1109/CSICS.2014.6978575","DOIUrl":"https://doi.org/10.1109/CSICS.2014.6978575","url":null,"abstract":"High power density GaN HEMT technology can increase the capability of defense electronics systems with the reduction of CSWaP. However, thermal limitations have currently limited the inherent capabilities of this technology where transistor-level power densities that exceed 10 kW/cm2 are electrically feasible. This paper introduces the concept of an evaporative microcooling device utilizing some of the current two-phase vapor separation technologies currently being developed for water and dielectric liquids.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128942151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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