Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100234
Qiansu Wan, Geng Yang, Qiang Chen, Lirong Zheng
This paper presents electrical performance of paper based inkjet printed flexible cable for wearable electrocardiogram (ECG) monitoring. The cable is fabricated by inkjet printing of nano-silver wires on paper which connect bio-electric electrodes with wireless transmission of ECG signals to the central medical device. The cable consists of printed metal traces and a shielding line in the middle. The experiment results show that a reliable performance with high quality ECG data can be transmitted on the inkjet printed flexible cable.
{"title":"Electrical performance of inkjet printed flexible cable for ECG monitoring","authors":"Qiansu Wan, Geng Yang, Qiang Chen, Lirong Zheng","doi":"10.1109/EPEPS.2011.6100234","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100234","url":null,"abstract":"This paper presents electrical performance of paper based inkjet printed flexible cable for wearable electrocardiogram (ECG) monitoring. The cable is fabricated by inkjet printing of nano-silver wires on paper which connect bio-electric electrodes with wireless transmission of ECG signals to the central medical device. The cable consists of printed metal traces and a shielding line in the middle. The experiment results show that a reliable performance with high quality ECG data can be transmitted on the inkjet printed flexible cable.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128543782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100238
Manho Lee, Jonghyun Cho, Joohee Kim, J. Pak, Joungho Kim, Hyungdong Lee, Junho Lee, Kunwoo Park
The effect of temperature variation on through silicon via (TSV) noise coupling is measured in this paper. The measurement result is analyzed using the temperature-dependent TSV lumped model and shows good correlation. Under the hundreds-of-MHz frequency range, increasing temperature reduces the noise suppression because the dielectric constant increases. However, over that frequency range, increasing temperature increases the noise suppression because the silicon substrate's resistivity increases.
{"title":"Temperature-dependent through-silicon via (TSV) model and noise coupling","authors":"Manho Lee, Jonghyun Cho, Joohee Kim, J. Pak, Joungho Kim, Hyungdong Lee, Junho Lee, Kunwoo Park","doi":"10.1109/EPEPS.2011.6100238","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100238","url":null,"abstract":"The effect of temperature variation on through silicon via (TSV) noise coupling is measured in this paper. The measurement result is analyzed using the temperature-dependent TSV lumped model and shows good correlation. Under the hundreds-of-MHz frequency range, increasing temperature reduces the noise suppression because the dielectric constant increases. However, over that frequency range, increasing temperature increases the noise suppression because the silicon substrate's resistivity increases.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127997232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100245
Xiaolei Li, Jianming Jin, Jilin Tan
As the operating frequency and integration level of integrated circuits (IC) increase, full-wave analysis algorithms are needed to accurately simulate the arising electromagnetic phenomena. The finite-element time-domain (FETD) method has become an attractive candidate for this simulation due to its advantages in modeling complex geometries and materials, conducting transient analyses, and performing broadband characterizations. Three FETD-based numerical algorithms, including the original FETD method, the dual-field domain-decomposition (DFDD) method, and the discontinuous Galerkin time-domain (DGTD) method, are investigated and applied to the simulation of printed circuit board (PCB) structures to demonstrate their accuracies and capabilities.
{"title":"Three finite-element time-domain-based numerical algorithms for high-frequency broadband PCB simulations","authors":"Xiaolei Li, Jianming Jin, Jilin Tan","doi":"10.1109/EPEPS.2011.6100245","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100245","url":null,"abstract":"As the operating frequency and integration level of integrated circuits (IC) increase, full-wave analysis algorithms are needed to accurately simulate the arising electromagnetic phenomena. The finite-element time-domain (FETD) method has become an attractive candidate for this simulation due to its advantages in modeling complex geometries and materials, conducting transient analyses, and performing broadband characterizations. Three FETD-based numerical algorithms, including the original FETD method, the dual-field domain-decomposition (DFDD) method, and the discontinuous Galerkin time-domain (DGTD) method, are investigated and applied to the simulation of printed circuit board (PCB) structures to demonstrate their accuracies and capabilities.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127511574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100190
D. Kostka, A. Scogna, Frank Paglia, B. Mutnury
The electrical performance of high speed signaling in coupled differential microstrip lines is analyzed. Based on the modal decomposition analysis, the cancellation frequency in the single-ended insertion loss response is explained and a closed formula is presented for the prediction of such resonant frequencies. Sensitivity analyses are also performed in order to investigate the impact of the solder mask layer and the differential microstrip geometry on the cancellation frequency.
{"title":"Electrical performance of high speed signaling in coupled microstrip lines","authors":"D. Kostka, A. Scogna, Frank Paglia, B. Mutnury","doi":"10.1109/EPEPS.2011.6100190","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100190","url":null,"abstract":"The electrical performance of high speed signaling in coupled differential microstrip lines is analyzed. Based on the modal decomposition analysis, the cancellation frequency in the single-ended insertion loss response is explained and a closed formula is presented for the prediction of such resonant frequencies. Sensitivity analyses are also performed in order to investigate the impact of the solder mask layer and the differential microstrip geometry on the cancellation frequency.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126852594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100246
J. Hillebrand, S. Kieß, Y. Wang, M. Wróblewski, S. Simon
In this paper three different methods for reconstructing CAD models of solder balls based on 3D computed tomography (CT) data are discussed. The resulting CAD model contains accurate geometrical data of the device which can be used for an electromagnetic field simulation using the finite difference time domain (FDTD) method. This allows a non-instrusive evaluation of the electrical parameters of passive circuits, in this case for solder balls or bumps. All three reconstruction methods presented here will result in simulation meshes with a significantly reduced number of mesh cells compared to a simulation directly based on the original CT data. This leads to a significant reduction of both memory usage and simulation time which is important for complex packages.
{"title":"CAD model reconstruction of solder balls for the computationally efficient electromagnetic field simulation","authors":"J. Hillebrand, S. Kieß, Y. Wang, M. Wróblewski, S. Simon","doi":"10.1109/EPEPS.2011.6100246","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100246","url":null,"abstract":"In this paper three different methods for reconstructing CAD models of solder balls based on 3D computed tomography (CT) data are discussed. The resulting CAD model contains accurate geometrical data of the device which can be used for an electromagnetic field simulation using the finite difference time domain (FDTD) method. This allows a non-instrusive evaluation of the electrical parameters of passive circuits, in this case for solder balls or bumps. All three reconstruction methods presented here will result in simulation meshes with a significantly reduced number of mesh cells compared to a simulation directly based on the original CT data. This leads to a significant reduction of both memory usage and simulation time which is important for complex packages.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126686043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100201
M. Farhan, N. Nakhla, M. Nakhla, R. Achar, Albert Ruehliy
The large number of interconnects in high-speed circuits is a major bottleneck for fast simulation of such circuits. Recently, waveform relaxation methods based on transverse partitioning (WR-TP) were proposed to address this issue. It was shown that the complexity of WR-TP grows only linearly with the number of lines. However, as the coupling between the lines becomes stronger, the WR-TP algorithm either fails to converge or the number of iterations required for convergence increases. In this paper, an overlapping partitioning method for WR-TP is presented, which minimizes the number of iterations in the presence of strong coupling between the lines.
{"title":"Waveform relaxation and overlapping partitioning techniques for tightly coupled interconnects","authors":"M. Farhan, N. Nakhla, M. Nakhla, R. Achar, Albert Ruehliy","doi":"10.1109/EPEPS.2011.6100201","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100201","url":null,"abstract":"The large number of interconnects in high-speed circuits is a major bottleneck for fast simulation of such circuits. Recently, waveform relaxation methods based on transverse partitioning (WR-TP) were proposed to address this issue. It was shown that the complexity of WR-TP grows only linearly with the number of lines. However, as the coupling between the lines becomes stronger, the WR-TP algorithm either fails to converge or the number of iterations required for convergence increases. In this paper, an overlapping partitioning method for WR-TP is presented, which minimizes the number of iterations in the presence of strong coupling between the lines.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126077996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100233
Yu Chang, C. Madden, R. Schmitt
Analysis of high-speed links requires modeling of timing noise in devices and clock architecture as well as passive inter-connections. With the increased demand on data rate and low power in mobile devices such as 3D PoP, it is more challenging to predict bit error rate (BER) due to their tighten timing and voltage constraints. Phase relationship among different jitter sources becomes a key player deciding how well links perform. A new method based on the subspace concept is proposed to estimate the phases in multi-tone jitter sequences. Its accuracy is much less sensitive to the size of data than FFT based method. For the first time, the phase of one on-chip jitter sensitivity function is characterized out using limited data from measurement.
{"title":"A new method to estimate phases of sinusoidal jitter to evaluate high-speed links","authors":"Yu Chang, C. Madden, R. Schmitt","doi":"10.1109/EPEPS.2011.6100233","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100233","url":null,"abstract":"Analysis of high-speed links requires modeling of timing noise in devices and clock architecture as well as passive inter-connections. With the increased demand on data rate and low power in mobile devices such as 3D PoP, it is more challenging to predict bit error rate (BER) due to their tighten timing and voltage constraints. Phase relationship among different jitter sources becomes a key player deciding how well links perform. A new method based on the subspace concept is proposed to estimate the phases in multi-tone jitter sequences. Its accuracy is much less sensitive to the size of data than FFT based method. For the first time, the phase of one on-chip jitter sensitivity function is characterized out using limited data from measurement.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121896755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100231
Yin-Cheng Chang, S. Hsu, D. Chang, Jeng-Hung Lee, Shuw-Guann Lin, Y. Juang
An extracting methodology is proposed to characterize the performance of interconnect. This work successfully extracts the interconnect by using transmission matrix (T-matrix) for calculation. This method exhibits its validity without frequency limitation mathematically. It can deal with most kinds of vertical interconnects including bond-wires, micro-bumps and through-silicon-vias (TSVs). Details of equations and measurement procedure are reported in this work. The bump in flip-chip process is taken as an example. The analysis is depicted and the measured results are performed for verification up to 20 GHz.
{"title":"A de-embedding method for extracting S-parameters of vertical interconnect in advanced packaging","authors":"Yin-Cheng Chang, S. Hsu, D. Chang, Jeng-Hung Lee, Shuw-Guann Lin, Y. Juang","doi":"10.1109/EPEPS.2011.6100231","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100231","url":null,"abstract":"An extracting methodology is proposed to characterize the performance of interconnect. This work successfully extracts the interconnect by using transmission matrix (T-matrix) for calculation. This method exhibits its validity without frequency limitation mathematically. It can deal with most kinds of vertical interconnects including bond-wires, micro-bumps and through-silicon-vias (TSVs). Details of equations and measurement procedure are reported in this work. The bump in flip-chip process is taken as an example. The analysis is depicted and the measured results are performed for verification up to 20 GHz.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"489 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133118344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100209
Ayman Shafik, Keytaek Lee, E. Z. Tabasy, S. Palermo
In this paper, the performance impact of embedding partial equalization in ADC-based receivers is analyzed. A hybrid ADC receiver architecture which includes embedded equalization and selective digital equalization power-down based on threshold detection is proposed.
{"title":"Embedded equalization for ADC-based serial I/O receivers","authors":"Ayman Shafik, Keytaek Lee, E. Z. Tabasy, S. Palermo","doi":"10.1109/EPEPS.2011.6100209","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100209","url":null,"abstract":"In this paper, the performance impact of embedding partial equalization in ADC-based receivers is analyzed. A hybrid ADC receiver architecture which includes embedded equalization and selective digital equalization power-down based on threshold detection is proposed.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131464025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100222
Qing He, Duo Chen, D. Jiao
An explicit and unconditionally stable time-domain finite-element method of linear complexity is developed for the simulation of 3-D global interconnect network. Numerical experiments have demonstrated that the proposed unconditionally stable explicit method outperforms both the conditionally stable explicit method and the unconditionally stable implicit method in computational efficiency.
{"title":"An explicit and unconditionally stable time-domain finite-element method of linear complexity for electromagnetics-based simulation of 3-D global interconnect network","authors":"Qing He, Duo Chen, D. Jiao","doi":"10.1109/EPEPS.2011.6100222","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100222","url":null,"abstract":"An explicit and unconditionally stable time-domain finite-element method of linear complexity is developed for the simulation of 3-D global interconnect network. Numerical experiments have demonstrated that the proposed unconditionally stable explicit method outperforms both the conditionally stable explicit method and the unconditionally stable implicit method in computational efficiency.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134645377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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