Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100223
Tai-Yu Cheng, Chuen-De Wang, Y. Chiou, Tzong-Lin Wu
In this paper, the effects of slow wave and dielectric quasi-TEM modes in through-silicon via (TSV) are analyzed by using the currently used TSV model. By the E-field plot, if pitch-to-diameter ratio is small in TSV structure, it is found out that some electrical behaviour of the TSVs is not well characterized by conventional model. This paper proposes a general and analytic model for the electrical modeling of through-silicon via (TSV) based on the conformal mapping method to modify the conventional model in admittance (CG) parts. With the improved model, the electrical performance of the modified model agrees very well with full-wave simulation up to 40GHz for small normalized pitch TSV.
{"title":"Accuracy-improved through-silicon-via model using conformal mapping technique","authors":"Tai-Yu Cheng, Chuen-De Wang, Y. Chiou, Tzong-Lin Wu","doi":"10.1109/EPEPS.2011.6100223","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100223","url":null,"abstract":"In this paper, the effects of slow wave and dielectric quasi-TEM modes in through-silicon via (TSV) are analyzed by using the currently used TSV model. By the E-field plot, if pitch-to-diameter ratio is small in TSV structure, it is found out that some electrical behaviour of the TSVs is not well characterized by conventional model. This paper proposes a general and analytic model for the electrical modeling of through-silicon via (TSV) based on the conformal mapping method to modify the conventional model in admittance (CG) parts. With the improved model, the electrical performance of the modified model agrees very well with full-wave simulation up to 40GHz for small normalized pitch TSV.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130735006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100170
D. Oh
Single-ended signaling is a popular choice for memory interface designs, due to its low pin-count requirement and slow DRAM process technology. Single-ended signaling requires a good current return path, in order to maintain high signal quality. Commonly used single-ended signaling schemes require both power and ground current return paths. In high-density memory interface systems, not all of the signals can be routed using a stripline with both power and ground planes. Using other non-stripline routing configurations can lead to voltage noise at some of the reference planes; referred to as plane bounce. This paper demonstrates that, while plane bounce may be significant in amplitude, its impact on the data signal is not as critical as previously thought. Various channel topologies are used to support this assertion.
{"title":"Plane bounce in high-speed single-ended signaling I/O interfaces","authors":"D. Oh","doi":"10.1109/EPEPS.2011.6100170","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100170","url":null,"abstract":"Single-ended signaling is a popular choice for memory interface designs, due to its low pin-count requirement and slow DRAM process technology. Single-ended signaling requires a good current return path, in order to maintain high signal quality. Commonly used single-ended signaling schemes require both power and ground current return paths. In high-density memory interface systems, not all of the signals can be routed using a stripline with both power and ground planes. Using other non-stripline routing configurations can lead to voltage noise at some of the reference planes; referred to as plane bounce. This paper demonstrates that, while plane bounce may be significant in amplitude, its impact on the data signal is not as critical as previously thought. Various channel topologies are used to support this assertion.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132619645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100253
Sidharath Jain, Jiming Song, T. Kamgaing, Y. Mekonnen
An efficient approach to speed up the spectral domain analysis for the general case of shielded microstrip has been presented. It uses asymptotic expansion for the Bessel's function and the Green's function which are involved in the computation of the elements of the Galerkin matrix. The coefficients in the asymptotic expansion of the Green's functions are obtained by a combination of analytical and numerical approaches. Efficient computation of the infinite summation obtained after leading term extraction is done using two different super convergent sine cosine series. Very accurate results for the propagation constants in the general case of a multilayered shielded microstrip line can be obtained using a few basis functions.
{"title":"Efficient spectral domain analysis of multilayered shielded microstrip using two super convergent series","authors":"Sidharath Jain, Jiming Song, T. Kamgaing, Y. Mekonnen","doi":"10.1109/EPEPS.2011.6100253","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100253","url":null,"abstract":"An efficient approach to speed up the spectral domain analysis for the general case of shielded microstrip has been presented. It uses asymptotic expansion for the Bessel's function and the Green's function which are involved in the computation of the elements of the Galerkin matrix. The coefficients in the asymptotic expansion of the Green's functions are obtained by a combination of analytical and numerical approaches. Efficient computation of the infinite summation obtained after leading term extraction is done using two different super convergent sine cosine series. Very accurate results for the propagation constants in the general case of a multilayered shielded microstrip line can be obtained using a few basis functions.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132249742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100240
Sourajeet Roy, A. Dounavis
In this paper, a waveform relaxation algorithm is presented to efficiently model power distribution networks. The proposed algorithm is based on physically partitioning the large circuit into smaller disjoint subcircuits. A key feature of the partitioning scheme is that it ensures that the noise injected by each transient source is localized within the subcircuit where the source resides thereby leading to efficient convergence of the algorithm. The iterative solution of the subcircuits is parallelizable and scales efficiently with the number of processors. A numerical example has been provided to illustrate the validity of the proposed algorithm over full SPICE simulations.
{"title":"Waveform relaxation based analysis of noise propagation in power distribution networks","authors":"Sourajeet Roy, A. Dounavis","doi":"10.1109/EPEPS.2011.6100240","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100240","url":null,"abstract":"In this paper, a waveform relaxation algorithm is presented to efficiently model power distribution networks. The proposed algorithm is based on physically partitioning the large circuit into smaller disjoint subcircuits. A key feature of the partitioning scheme is that it ensures that the noise injected by each transient source is localized within the subcircuit where the source resides thereby leading to efficient convergence of the algorithm. The iterative solution of the subcircuits is parallelizable and scales efficiently with the number of processors. A numerical example has been provided to illustrate the validity of the proposed algorithm over full SPICE simulations.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115345023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100228
Qian Li, K. Melde, G. Yeh, Hui Wu, Yaochao Yang
This paper presents a method to simplify the 3D full-wave simulation of via structures on the multilayer mid-planes. The method splits the full-length via model into small via sections, simulates these sections separately. The final simulation results are obtained by cascading the scattering parameters for the small via sections. The simulation accuracy of the cascaded structure for FEXT is comparable to the accuracy obtained with simulations of the 3D via using full-wave simulations in HFSS for frequencies up to 20GHz for both uniform structures and the structures with discontinuity. The results show a dramatic reduction in simulation time and complexity.
{"title":"3D via modeling simplification on multilayer mid-planes","authors":"Qian Li, K. Melde, G. Yeh, Hui Wu, Yaochao Yang","doi":"10.1109/EPEPS.2011.6100228","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100228","url":null,"abstract":"This paper presents a method to simplify the 3D full-wave simulation of via structures on the multilayer mid-planes. The method splits the full-length via model into small via sections, simulates these sections separately. The final simulation results are obtained by cascading the scattering parameters for the small via sections. The simulation accuracy of the cascaded structure for FEXT is comparable to the accuracy obtained with simulations of the 3D via using full-wave simulations in HFSS for frequencies up to 20GHz for both uniform structures and the structures with discontinuity. The results show a dramatic reduction in simulation time and complexity.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115628078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100208
W. Beyene, A. Amirkhany, C. Madden, H. Lan, L. Yang, K. Kaviani, S. Mukherjee, D. Secker, R. Schmitt
The design of a high-speed single-ended parallel interface using conventional package and board technologies is presented. The system uses asymmetrical architecture where the equalization and timing adjustment circuits for both memory WRITE and READ transactions are on the controller to reduce the memory cost. The analysis and optimization steps employed to mitigate the effect of inter-symbol interference, crosstalk, and supply noise are discussed. The impact of data encoding techniques on system timing margin is also investigated. The designed single-ended signaling was able to achieve a reliable communication at a data rate of 12.8 Gbps over a graphics channel. Several of the noise reduction techniques were also verified with measurement made on a prototype system.
{"title":"Design and analysis of 12.8 Gb/s single-ended signaling for memory interface","authors":"W. Beyene, A. Amirkhany, C. Madden, H. Lan, L. Yang, K. Kaviani, S. Mukherjee, D. Secker, R. Schmitt","doi":"10.1109/EPEPS.2011.6100208","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100208","url":null,"abstract":"The design of a high-speed single-ended parallel interface using conventional package and board technologies is presented. The system uses asymmetrical architecture where the equalization and timing adjustment circuits for both memory WRITE and READ transactions are on the controller to reduce the memory cost. The analysis and optimization steps employed to mitigate the effect of inter-symbol interference, crosstalk, and supply noise are discussed. The impact of data encoding techniques on system timing margin is also investigated. The designed single-ended signaling was able to achieve a reliable communication at a data rate of 12.8 Gbps over a graphics channel. Several of the noise reduction techniques were also verified with measurement made on a prototype system.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122111067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100199
A. Trivedi, W. Yueh, S. Mukhopadhyay
We analyze the bias and frequency dependent capacitance of the Power/Ground (P/G) Through-Silicon-Via (TSVs) and its impact on the high-frequency noise in the power delivery network (PDN) of a 3D stack. We show that the P/G TSVs in a 3D PDN act as on-chip distributed decoupling capacitances and hence, help reduce the high-frequency impedance. We present that for the same cross-sectional area, P/G TSVs created using a cluster of small diameter TSVs has higher capacitance than a single large diameter TSV and hence, can further reduce the high-frequency PDN impedance.
{"title":"Impact of Through-Silicon-Via capacitance on high frequency supply noise in 3D-stacks","authors":"A. Trivedi, W. Yueh, S. Mukhopadhyay","doi":"10.1109/EPEPS.2011.6100199","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100199","url":null,"abstract":"We analyze the bias and frequency dependent capacitance of the Power/Ground (P/G) Through-Silicon-Via (TSVs) and its impact on the high-frequency noise in the power delivery network (PDN) of a 3D stack. We show that the P/G TSVs in a 3D PDN act as on-chip distributed decoupling capacitances and hence, help reduce the high-frequency impedance. We present that for the same cross-sectional area, P/G TSVs created using a cluster of small diameter TSVs has higher capacitance than a single large diameter TSV and hence, can further reduce the high-frequency PDN impedance.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125592861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100179
E. Liu, E. Li
Radio frequency system-on-chips (RF SoC) require high quality passive devices such as capacitors. We comprehensively studied the vertical natural capacitors (VNCAP) made of CMOS back-end-of-lines (BEOL) in 32-nm technology. We used electromagnetic simulation and a Pi-type equivalent circuit model for the study of the VNCAP, and reported its electrical characteristics including the scattering parameter, effective capacitance, self-resonant frequency and quality factor up to 20 GHz. We also briefly discussed the performance scaling trend of VNCAPs from 65-nm to 32-nm technology.
{"title":"Electrical performance of vertical natural capacitor for RF system-on-chip in 32-nm technology","authors":"E. Liu, E. Li","doi":"10.1109/EPEPS.2011.6100179","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100179","url":null,"abstract":"Radio frequency system-on-chips (RF SoC) require high quality passive devices such as capacitors. We comprehensively studied the vertical natural capacitors (VNCAP) made of CMOS back-end-of-lines (BEOL) in 32-nm technology. We used electromagnetic simulation and a Pi-type equivalent circuit model for the study of the VNCAP, and reported its electrical characteristics including the scattering parameter, effective capacitance, self-resonant frequency and quality factor up to 20 GHz. We also briefly discussed the performance scaling trend of VNCAPs from 65-nm to 32-nm technology.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128907718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100171
J. Choi, M. Swaminathan
When the return path of a signal is not continuous, unwanted noise will couple to the return current, leading to worsening of the signal waveform. To prevent such a signal integrity issue, a thorough understanding of the physics of the return path discontinuity (RPD) is critical. This paper presents analysis and quantification of the impact of RPDs in the presence of a power delivery network. The study of the different types of RPDs, such as a gap between reference planes and an aperture, provides designing and modeling guidelines. The guidelines are applied to an efficient PDN analysis method to further improve computational efficiency.
{"title":"Practical aspects of modeling apertures for signal and power integrity co-simulation","authors":"J. Choi, M. Swaminathan","doi":"10.1109/EPEPS.2011.6100171","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100171","url":null,"abstract":"When the return path of a signal is not continuous, unwanted noise will couple to the return current, leading to worsening of the signal waveform. To prevent such a signal integrity issue, a thorough understanding of the physics of the return path discontinuity (RPD) is critical. This paper presents analysis and quantification of the impact of RPDs in the presence of a power delivery network. The study of the different types of RPDs, such as a gap between reference planes and an aperture, provides designing and modeling guidelines. The guidelines are applied to an efficient PDN analysis method to further improve computational efficiency.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122418140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100221
T. Sekine, H. Asai
This paper describes a full-wave transient simulation technique based on the partial element equivalent circuit (PEEC) method and a leapfrog scheme. Usually, the quasi-static PEEC method, which does not include retardation of coupling effects, constructs a dense circuit matrix due to instantaneous interaction of the mutual couplings. On the other hand, it is known that sparsity can be exploited if the retardation is taken into account so that the mutual elements affect with delay. The network realized by the PEEC method is often solved by a modified nodal analysis-based direct solver. In this work, we apply the leapfrog scheme to the time domain formulation of the retarded PEEC networks instead of the conventional direct solver. The leapfrog scheme is one of the explicit finite difference methods in the time domain and has an advantage of few computational complexities. Example simulations of asymmetric interconnects show that the leapfrog-based solver is suitable for the full-wave PEEC simulations in the time domain.
{"title":"Full-wave PEEC time domain solver based on leapfrog scheme","authors":"T. Sekine, H. Asai","doi":"10.1109/EPEPS.2011.6100221","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100221","url":null,"abstract":"This paper describes a full-wave transient simulation technique based on the partial element equivalent circuit (PEEC) method and a leapfrog scheme. Usually, the quasi-static PEEC method, which does not include retardation of coupling effects, constructs a dense circuit matrix due to instantaneous interaction of the mutual couplings. On the other hand, it is known that sparsity can be exploited if the retardation is taken into account so that the mutual elements affect with delay. The network realized by the PEEC method is often solved by a modified nodal analysis-based direct solver. In this work, we apply the leapfrog scheme to the time domain formulation of the retarded PEEC networks instead of the conventional direct solver. The leapfrog scheme is one of the explicit finite difference methods in the time domain and has an advantage of few computational complexities. Example simulations of asymmetric interconnects show that the leapfrog-based solver is suitable for the full-wave PEEC simulations in the time domain.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114811766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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