Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100198
Jonghyun Cho, Myunghoi Kim, Joohee Kim, J. Pak, Joungho Kim, Hyungdong Lee, Junho Lee, Kunwoo Park
The effects of through-silicon via (TSV) depletion are analyzed based on the frequency- and time-domain measurements in this paper. As TSV dc bias voltage increases, a TSV depletion region is generated; this region decreases TSV noise coupling at frequencies below 1 GHz. It also creates duty-cycle distortion of the coupled signal, which results from the nonlinearity of the TSV.
{"title":"Through-silicon via (TSV) depletion effect","authors":"Jonghyun Cho, Myunghoi Kim, Joohee Kim, J. Pak, Joungho Kim, Hyungdong Lee, Junho Lee, Kunwoo Park","doi":"10.1109/EPEPS.2011.6100198","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100198","url":null,"abstract":"The effects of through-silicon via (TSV) depletion are analyzed based on the frequency- and time-domain measurements in this paper. As TSV dc bias voltage increases, a TSV depletion region is generated; this region decreases TSV noise coupling at frequencies below 1 GHz. It also creates duty-cycle distortion of the coupled signal, which results from the nonlinearity of the TSV.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122664396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100183
Joon Hyung Chung, A. Cangellaris
A methodology is presented for the computationally-efficient and accurate rational approximation of broadband electromagnetic responses of passive multi-ports. The proposed method relies on the repeated rational interpolation of subsets of the frequency data with the number of samples in each set being a fraction of that in the original set. The generated poles from the subsets are appropriately combined to serve as the poles of the multi-port system and to solve for the residues of its rational function fit. The expediency of this methodology is demonstrated through its application to the fitting of several multi-port broadband data.
{"title":"Fast rational function fitting of broadband multi-port responses via repeated random sampling","authors":"Joon Hyung Chung, A. Cangellaris","doi":"10.1109/EPEPS.2011.6100183","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100183","url":null,"abstract":"A methodology is presented for the computationally-efficient and accurate rational approximation of broadband electromagnetic responses of passive multi-ports. The proposed method relies on the repeated rational interpolation of subsets of the frequency data with the number of samples in each set being a fraction of that in the original set. The generated poles from the subsets are appropriately combined to serve as the poles of the multi-port system and to solve for the residues of its rational function fit. The expediency of this methodology is demonstrated through its application to the fitting of several multi-port broadband data.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123308818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100186
O. Vikinski
High frequency supply noise affects chip performance in mechanisms that go beyond logic path failures due to voltage drops. One of the dominant chip performance degradation mechanisms due to high frequency noise is the direct introduction of clock jitter. Basic modeling studies powered by Fourier analysis help establish a clear and fundamental understanding of how noise is translated into jitter in the clock distribution path. In this context oscillator feed forward mechanism is also explored and analysis of its spectral response reveals how, once tuned properly, it benefits frequency boost.
{"title":"Spectral relations of supply noise and jitter with regular and feed forward clocking schemes","authors":"O. Vikinski","doi":"10.1109/EPEPS.2011.6100186","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100186","url":null,"abstract":"High frequency supply noise affects chip performance in mechanisms that go beyond logic path failures due to voltage drops. One of the dominant chip performance degradation mechanisms due to high frequency noise is the direct introduction of clock jitter. Basic modeling studies powered by Fourier analysis help establish a clear and fundamental understanding of how noise is translated into jitter in the clock distribution path. In this context oscillator feed forward mechanism is also explored and analysis of its spectral response reveals how, once tuned properly, it benefits frequency boost.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131164058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100229
G. Shiue, Y. Tsai, Che-Ming Hsu, Jia-Hung Shiu
This work proposes two noise reduction schemes that use strongly coupled vertical-turn traces as substitute for weakly coupled vertical-turn traces and added guard traces to reduce the common-mode noise in a weakly differential serpentine delay microstrip line. The peak-to-peak amplitude of common-mode noise in the time-domain is reduced by bout 65% using the two methods, according to simulation results. The simulation results demonstrate that the frequency range over which the magnitude of differential-to-common mode conversion is reduced for a differential serpentine delay line with is wide band in the range 0.1∼2.7GHz and 3.2∼10GHz. Furthermore, the differential reflection loss for additional guard traces is only slightly reduced at the frequency of interest, but when strongly coupled vertical-turn traces are used. However, the differential insertion loss achieved using the two improved schemes is almost the same as that of the traditional pattern.
{"title":"Common-mode noise reduction schemes for differential serpentine delay microstrip line in high-speed digital circuits","authors":"G. Shiue, Y. Tsai, Che-Ming Hsu, Jia-Hung Shiu","doi":"10.1109/EPEPS.2011.6100229","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100229","url":null,"abstract":"This work proposes two noise reduction schemes that use strongly coupled vertical-turn traces as substitute for weakly coupled vertical-turn traces and added guard traces to reduce the common-mode noise in a weakly differential serpentine delay microstrip line. The peak-to-peak amplitude of common-mode noise in the time-domain is reduced by bout 65% using the two methods, according to simulation results. The simulation results demonstrate that the frequency range over which the magnitude of differential-to-common mode conversion is reduced for a differential serpentine delay line with is wide band in the range 0.1∼2.7GHz and 3.2∼10GHz. Furthermore, the differential reflection loss for additional guard traces is only slightly reduced at the frequency of interest, but when strongly coupled vertical-turn traces are used. However, the differential insertion loss achieved using the two improved schemes is almost the same as that of the traditional pattern.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123257969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100218
A. Chiariello, A. Maffucci, F. Villone, M. Nicolazzo
A parallel computation approach based on the properties of the Graphics Processor Units (GPU) is here presented to speed-up the broadband modeling of passive 3D structures. The full-wave electromagnetic model is based on a surface integral formulation, numerically implemented by using a null-pinv decomposition of the unknowns. The numerical model has been proven to be accurate and well-posed for a frequency range from DC to hundreds of GHz. A bottleneck of the model is the assembly of fully populated matrices and the final matrix inversion. This paper presents A GPU parallelization of the matrix assembly phase, and analyzes two case-studies which refer to full-wave analysis of interconnects. The achieved speedup with respect to a conventional serial approach is around 50x.
{"title":"Fast full-wave modeling of passive structures with graphic processors","authors":"A. Chiariello, A. Maffucci, F. Villone, M. Nicolazzo","doi":"10.1109/EPEPS.2011.6100218","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100218","url":null,"abstract":"A parallel computation approach based on the properties of the Graphics Processor Units (GPU) is here presented to speed-up the broadband modeling of passive 3D structures. The full-wave electromagnetic model is based on a surface integral formulation, numerically implemented by using a null-pinv decomposition of the unknowns. The numerical model has been proven to be accurate and well-posed for a frequency range from DC to hundreds of GHz. A bottleneck of the model is the assembly of fully populated matrices and the final matrix inversion. This paper presents A GPU parallelization of the matrix assembly phase, and analyzes two case-studies which refer to full-wave analysis of interconnects. The achieved speedup with respect to a conventional serial approach is around 50x.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129943454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100194
Dayoung Kim, Joohee Kim, Jonghyun Cho, J. Pak, Joungho Kim, Hyungdong Lee, Junho Lee, Kunwoo Park
As TSV-based three-dimensional integrated circuit (3D IC) technology advances rapidly, research on a new scheme for a three-dimensional clock distribution network (3D CDN) in TSV-based 3D IC with low skew, low jitter, low power consumption and small area consumption is needed. In this paper, we propose a new 3D CDN structure with distributed multi-TSV 3D CDN (DMT 3D CDN), and analyze the skew, jitter, power and area consumption. The proposed DMT 3D CDN improves the performance of the skew, jitter and area consumption, although the power consumption is degraded.
随着基于tsv的三维集成电路(3D IC)技术的迅速发展，需要研究一种基于tsv的三维时钟分配网络(3D CDN)的低倾斜、低抖动、低功耗和小面积消耗的新方案。本文提出了一种分布式多tsv 3D CDN (DMT 3D CDN)结构，并对其倾斜、抖动、功耗和面积消耗进行了分析。提出的DMT 3D CDN在降低功耗的同时，改善了歪斜、抖动和面积消耗的性能。
{"title":"Distributed multi TSV 3D clock distribution network in TSV-based 3D IC","authors":"Dayoung Kim, Joohee Kim, Jonghyun Cho, J. Pak, Joungho Kim, Hyungdong Lee, Junho Lee, Kunwoo Park","doi":"10.1109/EPEPS.2011.6100194","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100194","url":null,"abstract":"As TSV-based three-dimensional integrated circuit (3D IC) technology advances rapidly, research on a new scheme for a three-dimensional clock distribution network (3D CDN) in TSV-based 3D IC with low skew, low jitter, low power consumption and small area consumption is needed. In this paper, we propose a new 3D CDN structure with distributed multi-TSV 3D CDN (DMT 3D CDN), and analyze the skew, jitter, power and area consumption. The proposed DMT 3D CDN improves the performance of the skew, jitter and area consumption, although the power consumption is degraded.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122039852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100235
Eunseok Song, Kyoungchoul Koo, Myunghoi Kim, J. Pak, Joungho Kim
In this paper, we introduce a new decoupling capacitor stacked chip (DCSC) with discrete capacitors and through-silicon-vias (TSVs) that can overcome the limitations of the conventional decoupling capacitor solutions such as expensive on-chip NMOS capacitor and package-level discrete decoupling capacitor with narrow-band. The key idea of the proposed TSV-based DCSC is mounting the decoupling capacitors such as silicon-based NMOS capacitor and discrete capacitor on the backside of a chip and connecting the capacitors to the on-chip PDN through TSVs. Therefore, the TSV-based DCSC provides the lowest parasitic inductance (ESL: under several tens pH) through a short interconnections between the on-chip PDN and decoupling capacitors as well as the largest capacitance (up to several uF) by stacking the additional decoupling capacitors to 3D-IC systems.
{"title":"Decoupling capacitor stacked chip (DCSC) in TSV-based 3D-ICs","authors":"Eunseok Song, Kyoungchoul Koo, Myunghoi Kim, J. Pak, Joungho Kim","doi":"10.1109/EPEPS.2011.6100235","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100235","url":null,"abstract":"In this paper, we introduce a new decoupling capacitor stacked chip (DCSC) with discrete capacitors and through-silicon-vias (TSVs) that can overcome the limitations of the conventional decoupling capacitor solutions such as expensive on-chip NMOS capacitor and package-level discrete decoupling capacitor with narrow-band. The key idea of the proposed TSV-based DCSC is mounting the decoupling capacitors such as silicon-based NMOS capacitor and discrete capacitor on the backside of a chip and connecting the capacitors to the on-chip PDN through TSVs. Therefore, the TSV-based DCSC provides the lowest parasitic inductance (ESL: under several tens pH) through a short interconnections between the on-chip PDN and decoupling capacitors as well as the largest capacitance (up to several uF) by stacking the additional decoupling capacitors to 3D-IC systems.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132064546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100202
Haisheng Hu, A. Chinea, Stefano Grivet-Talocia, M. Miscuglio
This paper presents an optimized Waveform Relaxation solver for electrically-long high-speed channels terminated by nonlinear networks. The time-domain scattering operators of channel and terminations are cast as recursive convolutions and nonlinear discrete-time filters, respectively. A transverse and longitudinal decoupling is then applied to the channel operator, with the introduction of suitable relaxation sources, and solved iteratively until convergence. A frequency-dependent over-relaxation parameter is introduced in order to optimize the convergence rate. Numerical results show significantly reduced runtime and iteration count for critical benchmarks with respect to previous Waveform Relaxation formulations.
{"title":"Fast iterative simulation of high-speed channels via frequency-dependent over-relaxation","authors":"Haisheng Hu, A. Chinea, Stefano Grivet-Talocia, M. Miscuglio","doi":"10.1109/EPEPS.2011.6100202","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100202","url":null,"abstract":"This paper presents an optimized Waveform Relaxation solver for electrically-long high-speed channels terminated by nonlinear networks. The time-domain scattering operators of channel and terminations are cast as recursive convolutions and nonlinear discrete-time filters, respectively. A transverse and longitudinal decoupling is then applied to the channel operator, with the introduction of suitable relaxation sources, and solved iteratively until convergence. A frequency-dependent over-relaxation parameter is introduced in order to optimize the convergence rate. Numerical results show significantly reduced runtime and iteration count for critical benchmarks with respect to previous Waveform Relaxation formulations.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132587125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100217
D. Gope, V. Jandhyala, Xiren Wang, D. MacMillen, R. Camposano, Swagato Chakraborty, J. Pingenot, Devan Williams
Cloud computing is a potential paradigm-shifter for system-level electronic design automation tools for chip-package-board design. However, exploiting the true power of on-demand scalable computing is as yet an unmet challenge. We examine electromagnetic (EM) field simulation on cloud platforms.
{"title":"Towards system-level electromagnetic field simulation on computing clouds","authors":"D. Gope, V. Jandhyala, Xiren Wang, D. MacMillen, R. Camposano, Swagato Chakraborty, J. Pingenot, Devan Williams","doi":"10.1109/EPEPS.2011.6100217","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100217","url":null,"abstract":"Cloud computing is a potential paradigm-shifter for system-level electronic design automation tools for chip-package-board design. However, exploiting the true power of on-demand scalable computing is as yet an unmet challenge. We examine electromagnetic (EM) field simulation on cloud platforms.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131650685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100182
D. Deschrijver, K. Crombecq, Huu Minh Nguyen, T. Dhaene
Accurate modeling of parameterized microwave and RF components often requires a large number of full-wave electromagnetic simulations. In order to reduce the overall simulation cost, a sequential sampling algorithm is proposed that selects a sparse set of data samples which characterize the overall response of the system. The resulting data samples can be fed into existing modeling techniques. The effectiveness of the approach is illustrated by a parameterized H-shaped microwave antenna.
{"title":"Sequential sampling strategy for the modeling of parameterized microwave and RF components","authors":"D. Deschrijver, K. Crombecq, Huu Minh Nguyen, T. Dhaene","doi":"10.1109/EPEPS.2011.6100182","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100182","url":null,"abstract":"Accurate modeling of parameterized microwave and RF components often requires a large number of full-wave electromagnetic simulations. In order to reduce the overall simulation cost, a sequential sampling algorithm is proposed that selects a sparse set of data samples which characterize the overall response of the system. The resulting data samples can be fed into existing modeling techniques. The effectiveness of the approach is illustrated by a parameterized H-shaped microwave antenna.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122205343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：