Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100251
F. Broydé, E. Clavelier
By combining 4 pseudo-differential architectures with compatible types of termination circuit, we identify 12 multichannel pseudo-differential transmission schemes. Each provides a reduced external crosstalk compared to multiple single-ended links, using fewer conductors than multiple differential links.
{"title":"Twelve pseudo-differential transmission schemes","authors":"F. Broydé, E. Clavelier","doi":"10.1109/EPEPS.2011.6100251","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100251","url":null,"abstract":"By combining 4 pseudo-differential architectures with compatible types of termination circuit, we identify 12 multichannel pseudo-differential transmission schemes. Each provides a reduced external crosstalk compared to multiple single-ended links, using fewer conductors than multiple differential links.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127631412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100227
Daniel Rodriguez, S. Chun, R. Mandrekar, D. Dreps
Modern PCBs are increasingly subjected to real estate constraints. Often tradeoffs are made between ideal signaling conditions and placement feasibility. Traditional analysis of high speed signals has focused on the effects of through-channel characteristics such as insertion loss, return loss, transmitter/receiver equalization, and crosstalk due to adjacent signals of the same bus. This paper presents an issue in preproduction hardware in which a switching regulator's placement directly led to degraded margin in nearby high speed serial links via noise coupling. The phenomenon was characterized in a lab setting and subsequent hardware revisions implemented an isolation technique that proved highly effective.
{"title":"Switching regulator noise coupled onto high speed differential links","authors":"Daniel Rodriguez, S. Chun, R. Mandrekar, D. Dreps","doi":"10.1109/EPEPS.2011.6100227","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100227","url":null,"abstract":"Modern PCBs are increasingly subjected to real estate constraints. Often tradeoffs are made between ideal signaling conditions and placement feasibility. Traditional analysis of high speed signals has focused on the effects of through-channel characteristics such as insertion loss, return loss, transmitter/receiver equalization, and crosstalk due to adjacent signals of the same bus. This paper presents an issue in preproduction hardware in which a switching regulator's placement directly led to degraded margin in nearby high speed serial links via noise coupling. The phenomenon was characterized in a lab setting and subsequent hardware revisions implemented an isolation technique that proved highly effective.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"8 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133087450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100239
H. Shimada, S. Akita, Masami Ihiguro, M. Yasunaga, I. Yoshihara
In the GHz-domain, high signal-integrity (SI) is strongly demanded in PCB traces. Unfortunately, however, conventional techniques based on the characteristic-impedance-matching cannot work well in the GHz digital signals. In order to overcome this problem, we have proposed a novel PCB-trace structure called “Segmental-Transmission-Line (STL)” already. In this paper, we apply the STL to the 5 GHz differential transmission line and show its remarkable SI improvement ratios of 3.38 and 1.7 in the eye-height and eye-width, respectively.
{"title":"Signal-integrity improvement based on the segmental-transmission-line","authors":"H. Shimada, S. Akita, Masami Ihiguro, M. Yasunaga, I. Yoshihara","doi":"10.1109/EPEPS.2011.6100239","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100239","url":null,"abstract":"In the GHz-domain, high signal-integrity (SI) is strongly demanded in PCB traces. Unfortunately, however, conventional techniques based on the characteristic-impedance-matching cannot work well in the GHz digital signals. In order to overcome this problem, we have proposed a novel PCB-trace structure called “Segmental-Transmission-Line (STL)” already. In this paper, we apply the STL to the 5 GHz differential transmission line and show its remarkable SI improvement ratios of 3.38 and 1.7 in the eye-height and eye-width, respectively.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133301690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100187
M. Aleksic
This paper presents a method for jitter parameter extraction from bit error rate measurements, that can be used as an alternative to the dual-Dirac method. The method offers more accurate estimates of random and deterministic jitter, at the expense of a slight increase in complexity. The model underlying the method can be used for extrapolation of bit error rate to the values that are impractical to measure.
{"title":"Extraction of jitter parameters from BER measurements","authors":"M. Aleksic","doi":"10.1109/EPEPS.2011.6100187","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100187","url":null,"abstract":"This paper presents a method for jitter parameter extraction from bit error rate measurements, that can be used as an alternative to the dual-Dirac method. The method offers more accurate estimates of random and deterministic jitter, at the expense of a slight increase in complexity. The model underlying the method can be used for extrapolation of bit error rate to the values that are impractical to measure.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114274839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100232
A. Charest, M. Nakhla, R. Achar
In this paper, a new algorithm for passive model-order reduction of RLC networks with embedded general Time-Delay Descriptor (TDD) systems is presented. In addition, a new passivity verification algorithm for TDD systems is developed. Numerical results validating the proposed algorithms are also presented.
{"title":"Passive model-order reduction of RLC circuits with embedded time-delay descriptor systems","authors":"A. Charest, M. Nakhla, R. Achar","doi":"10.1109/EPEPS.2011.6100232","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100232","url":null,"abstract":"In this paper, a new algorithm for passive model-order reduction of RLC networks with embedded general Time-Delay Descriptor (TDD) systems is presented. In addition, a new passivity verification algorithm for TDD systems is developed. Numerical results validating the proposed algorithms are also presented.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123509760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100192
Se-jung Moon, E. Acar, R. Mellitz
This paper proposes new frequency-domain (FD) metrics to evaluate and optimize interconnects for high-speed IO. In this paper, we focused on a spring-probe socket for interconnects and PCIe Gen3 for the high-speed IO. For design optimization, we adapted a holistic approach utilizing response surface methodology. Using the proposed metrics, the spring-probe socket design was optimized to minimize impact on the IO channel performance. In order to check the validity of the new metrics, an optimized socket design via voltage margin and timing margin from eye opening was compared.
{"title":"New interconnect evaluation metric for high-speed IO","authors":"Se-jung Moon, E. Acar, R. Mellitz","doi":"10.1109/EPEPS.2011.6100192","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100192","url":null,"abstract":"This paper proposes new frequency-domain (FD) metrics to evaluate and optimize interconnects for high-speed IO. In this paper, we focused on a spring-probe socket for interconnects and PCIe Gen3 for the high-speed IO. For design optimization, we adapted a holistic approach utilizing response surface methodology. Using the proposed metrics, the spring-probe socket design was optimized to minimize impact on the IO channel performance. In order to check the validity of the new metrics, an optimized socket design via voltage margin and timing margin from eye opening was compared.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128933812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100189
M. Ballicchia, M. Farina, A. Morini, T. Rozzi, C. Turchetti, S. Orcioni
The present paper proposes a methodology that, starting from a set of calibration measurements picked up only at the external pins of the package, allows the determination of its representative matrix. Such a matrix can be used both for a correct measurement of the embedded device and in view of improving its design, by accounting for the effect of the package. The technique is demonstrated over a packaged passive integrated inductor.
{"title":"A methodology for RF modeling of packages using IC known-loads","authors":"M. Ballicchia, M. Farina, A. Morini, T. Rozzi, C. Turchetti, S. Orcioni","doi":"10.1109/EPEPS.2011.6100189","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100189","url":null,"abstract":"The present paper proposes a methodology that, starting from a set of calibration measurements picked up only at the external pins of the package, allows the determination of its representative matrix. Such a matrix can be used both for a correct measurement of the embedded device and in view of improving its design, by accounting for the effect of the package. The technique is demonstrated over a packaged passive integrated inductor.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130537870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100211
Wei Wang, J. Buckwalter
M-ary pulsewidth modulation (M-PWM) and double-edge pulsewidth modulation (DPWM) are compared to non-return-to-zero (NRZ) modulation in bandwidth-limited channels. DPWM features spectral characteristics that concentrate energy at lower frequencies compared to NRZ for a given data rate. Here, channel characteristics are studied that favor DPWM transmission. Each modulation format is compared at 10 Gb/s over two different electrical channels to study the signal integrity with respect to a fixed data rate and fixed minimum pulsewidth.
{"title":"Interconnect channel characteristics favoring double-edge pulsewidth modulation","authors":"Wei Wang, J. Buckwalter","doi":"10.1109/EPEPS.2011.6100211","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100211","url":null,"abstract":"M-ary pulsewidth modulation (M-PWM) and double-edge pulsewidth modulation (DPWM) are compared to non-return-to-zero (NRZ) modulation in bandwidth-limited channels. DPWM features spectral characteristics that concentrate energy at lower frequencies compared to NRZ for a given data rate. Here, channel characteristics are studied that favor DPWM transmission. Each modulation format is compared at 10 Gb/s over two different electrical channels to study the signal integrity with respect to a fixed data rate and fixed minimum pulsewidth.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125940027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100184
Stefano Grivet-Talocia, S. Olivadese, P. Triverio
Rational macromodeling via Vector Fitting algorithms is a standard practice in Signal and Power Integrity analysis and design flows. However, despite the robustness and reliability of the Vector Fitting scheme, some challenges remain for those applications requiring models with a very large port count. Fully coupled signal and/or power distribution networks may require concurrent modeling of hundreds of simultaneously coupled ports over extended frequency bands. Direct rational fitting is impractical for such structures due to a large computational cost. In this work, we present a compression strategy aimed at representing the dynamic behavior of the structure through few carefully selected “basis functions”. We show that model accuracy can be traded for complexity, with full control over approximation errors. Application of standard Vector Fitting to the obtained low-dimensional compressed system leads to the construction of a global state-space macromodel with significantly reduced runtime and memory consumption. Several benchmarks demonstrate the effectiveness of the approach.
{"title":"A compression strategy for rational macromodeling of large interconnect structures","authors":"Stefano Grivet-Talocia, S. Olivadese, P. Triverio","doi":"10.1109/EPEPS.2011.6100184","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100184","url":null,"abstract":"Rational macromodeling via Vector Fitting algorithms is a standard practice in Signal and Power Integrity analysis and design flows. However, despite the robustness and reliability of the Vector Fitting scheme, some challenges remain for those applications requiring models with a very large port count. Fully coupled signal and/or power distribution networks may require concurrent modeling of hundreds of simultaneously coupled ports over extended frequency bands. Direct rational fitting is impractical for such structures due to a large computational cost. In this work, we present a compression strategy aimed at representing the dynamic behavior of the structure through few carefully selected “basis functions”. We show that model accuracy can be traded for complexity, with full control over approximation errors. Application of standard Vector Fitting to the obtained low-dimensional compressed system leads to the construction of a global state-space macromodel with significantly reduced runtime and memory consumption. Several benchmarks demonstrate the effectiveness of the approach.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125809137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100249
Chia-Han Chang, R. Fang, Chun-Long Wang
In this paper, a bended differential transmission line using a short-circuited coupled line is proposed to efficiently suppress the common-mode noise. It has been shown that the bended differential transmission line using the short-circuited coupled line can greatly reduce the mode conversion from −5.47 dB to −14.75 dB and the TDT common-mode noise from 0.068 V to 0.02 V as compared with the bended differential transmission line using the right-angle bend. In order to verify the simulation results, measurement is done in the frequency and time domains where the measurement results are in good agreement with the simulation results.
{"title":"Bended differential transmission line using short-circuited coupled line for common-mode noise suppression","authors":"Chia-Han Chang, R. Fang, Chun-Long Wang","doi":"10.1109/EPEPS.2011.6100249","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100249","url":null,"abstract":"In this paper, a bended differential transmission line using a short-circuited coupled line is proposed to efficiently suppress the common-mode noise. It has been shown that the bended differential transmission line using the short-circuited coupled line can greatly reduce the mode conversion from −5.47 dB to −14.75 dB and the TDT common-mode noise from 0.068 V to 0.02 V as compared with the bended differential transmission line using the right-angle bend. In order to verify the simulation results, measurement is done in the frequency and time domains where the measurement results are in good agreement with the simulation results.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114903419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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