Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100191
U. Arz, M. Rohland, K. Kuhlmann, S. Buttgenbach
In this paper we present an optimized interconnect structure which allows for the accurate broadband characterization of coplanar waveguides (CPWs) built in membrane technology. For both the membrane CPW and the silicon part of the interconnect structure, we compare measurements against calculations, and, where available, also against full-wave simulations. The agreement for the membrane CPW part is very good over a frequency range of 110 GHz. In addition, we detect a tangible sensitivity of the broadband propagation characteristics to the relative permittivity of the membrane material for both parts of the interconnect structure.
{"title":"Optimized coplanar waveguides in membrane technology for wideband on-wafer calibrations","authors":"U. Arz, M. Rohland, K. Kuhlmann, S. Buttgenbach","doi":"10.1109/EPEPS.2011.6100191","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100191","url":null,"abstract":"In this paper we present an optimized interconnect structure which allows for the accurate broadband characterization of coplanar waveguides (CPWs) built in membrane technology. For both the membrane CPW and the silicon part of the interconnect structure, we compare measurements against calculations, and, where available, also against full-wave simulations. The agreement for the membrane CPW part is very good over a frequency range of 110 GHz. In addition, we detect a tangible sensitivity of the broadband propagation characteristics to the relative permittivity of the membrane material for both parts of the interconnect structure.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128691978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100210
Jihong Ren, D. Oh, R. Kollipara, Brian Tsang, Yue Lu, J. Zerbe, Qi Lin
A 5Gb/s source-synchronous signaling system was developed utilizing embedded common-mode clocking technology to minimize clock distribution delays and to reduce the total pin count. The common-mode clocking scheme forwards the clock on the common mode of the differential data channels. In addition to the signal integrity issues present in differential signaling systems, the embedded common-mode clocking scheme presents additional challenges in system design. By means of impedance control for both common mode and differential mode, careful trace length matching, 5W spacing rule etc, we achieved good signal integrity and the link exhibits good margin. Mode conversion is one of the key issues in the common-mode clocking technology, and it is covered in detail. Measurement results show that the clocking scheme can tolerate −13dB mode conversion on both differential pairs at 5Gb/s.
{"title":"System design considerations for a 5Gb/s source-synchronous link with common-mode clocking","authors":"Jihong Ren, D. Oh, R. Kollipara, Brian Tsang, Yue Lu, J. Zerbe, Qi Lin","doi":"10.1109/EPEPS.2011.6100210","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100210","url":null,"abstract":"A 5Gb/s source-synchronous signaling system was developed utilizing embedded common-mode clocking technology to minimize clock distribution delays and to reduce the total pin count. The common-mode clocking scheme forwards the clock on the common mode of the differential data channels. In addition to the signal integrity issues present in differential signaling systems, the embedded common-mode clocking scheme presents additional challenges in system design. By means of impedance control for both common mode and differential mode, careful trace length matching, 5W spacing rule etc, we achieved good signal integrity and the link exhibits good margin. Mode conversion is one of the key issues in the common-mode clocking technology, and it is covered in detail. Measurement results show that the clocking scheme can tolerate −13dB mode conversion on both differential pairs at 5Gb/s.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124028225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100205
P. Goh, J. Schutt-Ainé
In this paper, we present an application of the latency insertion method (LIM) to the transient simulations of CMOS circuits and compare it to traditional SPICE based methods. In addition, we extend the multi-rate simulation technique and apply it to the simulation of CMOS circuits in the LIM environment and illustrate its computational efficiently over the basic LIM.
{"title":"Latency insertion method (LIM) for CMOS circuit simulations with multi-rate considerations","authors":"P. Goh, J. Schutt-Ainé","doi":"10.1109/EPEPS.2011.6100205","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100205","url":null,"abstract":"In this paper, we present an application of the latency insertion method (LIM) to the transient simulations of CMOS circuits and compare it to traditional SPICE based methods. In addition, we extend the multi-rate simulation technique and apply it to the simulation of CMOS circuits in the LIM environment and illustrate its computational efficiently over the basic LIM.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129401708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100243
G. Charles, P. Franzon, Jaemin Kim, Alex Levin
In this paper, we model and analyse a hierarchical TSV-based chip-package co-design of the power delivery network (PDN) for three-dimensional integrated circuits (3DICs). It is a significant design consideration to combine chip/package PDN structures, accurately characterize and quantify their overall impedance, 1st-droop effect and resonant noise behaviour for multi-stacked chips. To better understand how to reduce noise, particularly simultaneous switching noise (SSN) and determine voltage drop impact on power delivery networks for 3DICs, an analytical model is enhanced and applied to estimate the different noise levels of hierarchical TSV-based PDN structures. The on-chip parasitic capacitances and intentionally added decoupling capacitors help counter any Ldi/dt variations from the power supply rails as a result of the inductive effects in TSVs. With technology interest in embedded applications, the hierarchical chip-package TSV-based PDN design is modeled after a multi-stacked memory subsystem, a silicon interposer and package structure. A segmentation-based method is used to calculate the overall impedance of the hierarchical PDN system. An analytical expression is modified and used to quantify the transient response characteristics of 1st-droop and resonant noise property.
{"title":"Analysis and approach of TSV-based hierarchical power distribution networks for estimating 1st-Droop and resonant noise in 3DIC","authors":"G. Charles, P. Franzon, Jaemin Kim, Alex Levin","doi":"10.1109/EPEPS.2011.6100243","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100243","url":null,"abstract":"In this paper, we model and analyse a hierarchical TSV-based chip-package co-design of the power delivery network (PDN) for three-dimensional integrated circuits (3DICs). It is a significant design consideration to combine chip/package PDN structures, accurately characterize and quantify their overall impedance, 1st-droop effect and resonant noise behaviour for multi-stacked chips. To better understand how to reduce noise, particularly simultaneous switching noise (SSN) and determine voltage drop impact on power delivery networks for 3DICs, an analytical model is enhanced and applied to estimate the different noise levels of hierarchical TSV-based PDN structures. The on-chip parasitic capacitances and intentionally added decoupling capacitors help counter any Ldi/dt variations from the power supply rails as a result of the inductive effects in TSVs. With technology interest in embedded applications, the hierarchical chip-package TSV-based PDN design is modeled after a multi-stacked memory subsystem, a silicon interposer and package structure. A segmentation-based method is used to calculate the overall impedance of the hierarchical PDN system. An analytical expression is modified and used to quantify the transient response characteristics of 1st-droop and resonant noise property.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115320097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100214
A. Rong, A. Cangellaris
A methodology is presented for the calculation of the transient transmission-line response of package-level or board-level interconnects in the presence of layout and routing uncertainty. The proposed methodology makes use of the generalized polynomial chaos framework and advances in sparse stochastic collocation for interpolation and sampling in the probability space defined by the random variables that describe routing uncertainty. In this manner, a modeling framework is established that facilitates the computation of the statistics of the transient response and its post-processing for the purpose of assessing the impact of interconnect layout and routing uncertainty on signal distortion and crosstalk.
{"title":"Interconnect transient simulation in the presence of layout and routing uncertainty","authors":"A. Rong, A. Cangellaris","doi":"10.1109/EPEPS.2011.6100214","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100214","url":null,"abstract":"A methodology is presented for the calculation of the transient transmission-line response of package-level or board-level interconnects in the presence of layout and routing uncertainty. The proposed methodology makes use of the generalized polynomial chaos framework and advances in sparse stochastic collocation for interpolation and sampling in the probability space defined by the random variables that describe routing uncertainty. In this manner, a modeling framework is established that facilitates the computation of the statistics of the transient response and its post-processing for the purpose of assessing the impact of interconnect layout and routing uncertainty on signal distortion and crosstalk.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125030036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100250
Ping Liu, Jilin Tan, Zhongyong Zhou, J. Schutt-Ainé, P. Goh
This paper compares two different formulations of the latency insertion method (LIM) for the analysis of circuits with dependent sources. One is the scalar LIM and the other is the amplification matrix LIM. Numerical experiments demonstrate that the scalar LIM necessitates much smaller time step than the amplification matrix LIM when handling certain types of dependent sources indicating better performance of the latter technique without a sacrifice in accuracy.
{"title":"A comparison of two latency insertion methods in dependent sources applications","authors":"Ping Liu, Jilin Tan, Zhongyong Zhou, J. Schutt-Ainé, P. Goh","doi":"10.1109/EPEPS.2011.6100250","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100250","url":null,"abstract":"This paper compares two different formulations of the latency insertion method (LIM) for the analysis of circuits with dependent sources. One is the scalar LIM and the other is the amplification matrix LIM. Numerical experiments demonstrate that the scalar LIM necessitates much smaller time step than the amplification matrix LIM when handling certain types of dependent sources indicating better performance of the latter technique without a sacrifice in accuracy.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124403914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100247
Kuan-Wei Li, K. Wu, R. Wu
Stitching decoupling capacitors are utilized to suppress the edge electromagnetic radiation in a pair of power/ground planes in this paper. The parasitic effects, ESL and ESR, of decoupling capacitors connecting the power and ground in the board periphery are introduced into the normal mode waveguide theory to optimize the placements and specification of the decoupling capacitors. Applications to practical structures demonstrate an additional 18dB EMI suppression up to several GHz range by choosing suitable ESL and an ultra-high suppression at several hundred MHz by choosing suitable capacitor value. Both the full-wave simulation and experiment validate the design idea.
{"title":"Optimal decoupling capacitors design for suppressing edge radiation of power/ground planes","authors":"Kuan-Wei Li, K. Wu, R. Wu","doi":"10.1109/EPEPS.2011.6100247","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100247","url":null,"abstract":"Stitching decoupling capacitors are utilized to suppress the edge electromagnetic radiation in a pair of power/ground planes in this paper. The parasitic effects, ESL and ESR, of decoupling capacitors connecting the power and ground in the board periphery are introduced into the normal mode waveguide theory to optimize the placements and specification of the decoupling capacitors. Applications to practical structures demonstrate an additional 18dB EMI suppression up to several GHz range by choosing suitable ESL and an ultra-high suppression at several hundred MHz by choosing suitable capacitor value. Both the full-wave simulation and experiment validate the design idea.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131743807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100236
Taigon Song, S. Lim
In this paper, we propose a methodology which can co-simulate IR-drop noise for 3D IC, silicon interposer, and PCB simultaneously, and demonstrate how severe the IR-drop is in the silicon interposer. This methodology uses not only PCB and package (silicon interposer) stacking information, but also full transistor-level 3D IC switching information for a precise IR-drop calculation. By utilizing these information, we show the IR-drop noise map of the PDN (Power Distribution Network) in the interposer and the 3D IC mounted on it. Based on our results, we found that (1) the IR-drop noise caused by silicon interposer is very severe to few tens of mV, and (2) our co-analysis method fixes the overestimation of IR-drop caused by the traditional method.
{"title":"A fine-grained co-simulation methodology for IR-drop noise in silicon interposer and TSV-based 3D IC","authors":"Taigon Song, S. Lim","doi":"10.1109/EPEPS.2011.6100236","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100236","url":null,"abstract":"In this paper, we propose a methodology which can co-simulate IR-drop noise for 3D IC, silicon interposer, and PCB simultaneously, and demonstrate how severe the IR-drop is in the silicon interposer. This methodology uses not only PCB and package (silicon interposer) stacking information, but also full transistor-level 3D IC switching information for a precise IR-drop calculation. By utilizing these information, we show the IR-drop noise map of the PDN (Power Distribution Network) in the interposer and the 3D IC mounted on it. Based on our results, we found that (1) the IR-drop noise caused by silicon interposer is very severe to few tens of mV, and (2) our co-analysis method fixes the overestimation of IR-drop caused by the traditional method.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124816023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100233
Yu Chang, C. Madden, R. Schmitt
Analysis of high-speed links requires modeling of timing noise in devices and clock architecture as well as passive inter-connections. With the increased demand on data rate and low power in mobile devices such as 3D PoP, it is more challenging to predict bit error rate (BER) due to their tighten timing and voltage constraints. Phase relationship among different jitter sources becomes a key player deciding how well links perform. A new method based on the subspace concept is proposed to estimate the phases in multi-tone jitter sequences. Its accuracy is much less sensitive to the size of data than FFT based method. For the first time, the phase of one on-chip jitter sensitivity function is characterized out using limited data from measurement.
{"title":"A new method to estimate phases of sinusoidal jitter to evaluate high-speed links","authors":"Yu Chang, C. Madden, R. Schmitt","doi":"10.1109/EPEPS.2011.6100233","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100233","url":null,"abstract":"Analysis of high-speed links requires modeling of timing noise in devices and clock architecture as well as passive inter-connections. With the increased demand on data rate and low power in mobile devices such as 3D PoP, it is more challenging to predict bit error rate (BER) due to their tighten timing and voltage constraints. Phase relationship among different jitter sources becomes a key player deciding how well links perform. A new method based on the subspace concept is proposed to estimate the phases in multi-tone jitter sequences. Its accuracy is much less sensitive to the size of data than FFT based method. For the first time, the phase of one on-chip jitter sensitivity function is characterized out using limited data from measurement.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121896755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100201
M. Farhan, N. Nakhla, M. Nakhla, R. Achar, Albert Ruehliy
The large number of interconnects in high-speed circuits is a major bottleneck for fast simulation of such circuits. Recently, waveform relaxation methods based on transverse partitioning (WR-TP) were proposed to address this issue. It was shown that the complexity of WR-TP grows only linearly with the number of lines. However, as the coupling between the lines becomes stronger, the WR-TP algorithm either fails to converge or the number of iterations required for convergence increases. In this paper, an overlapping partitioning method for WR-TP is presented, which minimizes the number of iterations in the presence of strong coupling between the lines.
{"title":"Waveform relaxation and overlapping partitioning techniques for tightly coupled interconnects","authors":"M. Farhan, N. Nakhla, M. Nakhla, R. Achar, Albert Ruehliy","doi":"10.1109/EPEPS.2011.6100201","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100201","url":null,"abstract":"The large number of interconnects in high-speed circuits is a major bottleneck for fast simulation of such circuits. Recently, waveform relaxation methods based on transverse partitioning (WR-TP) were proposed to address this issue. It was shown that the complexity of WR-TP grows only linearly with the number of lines. However, as the coupling between the lines becomes stronger, the WR-TP algorithm either fails to converge or the number of iterations required for convergence increases. In this paper, an overlapping partitioning method for WR-TP is presented, which minimizes the number of iterations in the presence of strong coupling between the lines.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126077996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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