Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100174
T. Zhou, J. Friedrich, W. Becker
A well defined power supply tolerance specification is very important for designing processor circuits with sufficient performance margin. We introduce a design flow to derive the voltage tolerance specification by including power noise components due to the significant contributors, namely, voltage drop, voltage gradient, middle frequency chip package resonance noise, high frequency simultaneous switching noise (SSN), and voltage regulation module (VRM) tolerance. This method has been serving well for power tolerance specifications of multiple generations of IBM processor designs. However, the methodology needs further refinement to design the off-chip serial interfaces. As the interfaces are increasing in frequency, the voltage levels and swings are minimized to meet the performance criteria of maximizing the data transfer rate per watt.
{"title":"Deriving voltage tolerance specification for processor circuit design","authors":"T. Zhou, J. Friedrich, W. Becker","doi":"10.1109/EPEPS.2011.6100174","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100174","url":null,"abstract":"A well defined power supply tolerance specification is very important for designing processor circuits with sufficient performance margin. We introduce a design flow to derive the voltage tolerance specification by including power noise components due to the significant contributors, namely, voltage drop, voltage gradient, middle frequency chip package resonance noise, high frequency simultaneous switching noise (SSN), and voltage regulation module (VRM) tolerance. This method has been serving well for power tolerance specifications of multiple generations of IBM processor designs. However, the methodology needs further refinement to design the off-chip serial interfaces. As the interfaces are increasing in frequency, the voltage levels and swings are minimized to meet the performance criteria of maximizing the data transfer rate per watt.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114923535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100177
X. Gu, L. Turlapati, B. Dang, C. Tsang, P. Andry, T. Dickson, Michael P. Beakes, J. Knickerbocker, D. Friedman
Two differential stripline configurations with pitches of 8µm and 22µm are designed for ultra dense interconnect on silicon carrier. The transmission lines are implemented using four wiring levels to support chip-to-chip communication at 11.5Gb/s data rate over 2cm without equalization. Loss characteristics are extracted from test coupons with good model-to-hardware correlation. Impedance and temperature dependent loss performance are analyzed with simulation. Crosstalk performance between two pairs with and without ground shielding, as well as between two twisted pairs, are also evaluated with hardware measurement.
{"title":"High-density silicon carrier transmission line design for chip-to-chip interconnects","authors":"X. Gu, L. Turlapati, B. Dang, C. Tsang, P. Andry, T. Dickson, Michael P. Beakes, J. Knickerbocker, D. Friedman","doi":"10.1109/EPEPS.2011.6100177","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100177","url":null,"abstract":"Two differential stripline configurations with pitches of 8µm and 22µm are designed for ultra dense interconnect on silicon carrier. The transmission lines are implemented using four wiring levels to support chip-to-chip communication at 11.5Gb/s data rate over 2cm without equalization. Loss characteristics are extracted from test coupons with good model-to-hardware correlation. Impedance and temperature dependent loss performance are analyzed with simulation. Crosstalk performance between two pairs with and without ground shielding, as well as between two twisted pairs, are also evaluated with hardware measurement.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125172142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100195
Xi Chen, W. R. Davis, P. Franzon
Clock distribution in three-dimensional integrated circuits (3D ICs) is faced with many challenges. In this work, we present new techniques for realizing highly adaptive and reliable clock distribution for 3D ICs. Firstly, an efficient clock distribution topology without need of balanced H-tree is proposed. Secondly, a robust tunable-delay-buffer (TDB) circuit and a novel active de-skew method are developed in order to handle the cross-die variations, thermal gradients, and wiring asymmetry. Moreover, a design optimization flow is constructed for improving the adaptive clock design based on the thermal profiles. Experiment results show that the clock skews are significantly reduced using the proposed techniques.
{"title":"Adaptive clock distribution for 3D integrated circuits","authors":"Xi Chen, W. R. Davis, P. Franzon","doi":"10.1109/EPEPS.2011.6100195","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100195","url":null,"abstract":"Clock distribution in three-dimensional integrated circuits (3D ICs) is faced with many challenges. In this work, we present new techniques for realizing highly adaptive and reliable clock distribution for 3D ICs. Firstly, an efficient clock distribution topology without need of balanced H-tree is proposed. Secondly, a robust tunable-delay-buffer (TDB) circuit and a novel active de-skew method are developed in order to handle the cross-die variations, thermal gradients, and wiring asymmetry. Moreover, a design optimization flow is constructed for improving the adaptive clock design based on the thermal profiles. Experiment results show that the clock skews are significantly reduced using the proposed techniques.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124384918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100252
R. Fang, Chia-fen Liu, Chun-Long Wang
In this paper, a compact stepped-impedance resonator (SIR) transformer is proposed The implemented CB-CPW to SIW transition using the SIR transformer has shown a 50% reduction in size with only 2.09% reduction in the 15-dB fractional bandwidth as compared with using the quarter-wavelength transformer.
{"title":"Compact stepped-impedance resonator transformer","authors":"R. Fang, Chia-fen Liu, Chun-Long Wang","doi":"10.1109/EPEPS.2011.6100252","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100252","url":null,"abstract":"In this paper, a compact stepped-impedance resonator (SIR) transformer is proposed The implemented CB-CPW to SIW transition using the SIR transformer has shown a 50% reduction in size with only 2.09% reduction in the 15-dB fractional bandwidth as compared with using the quarter-wavelength transformer.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125006203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100203
F. Broydé, E. Clavelier
A new model for resistive losses can be used within the multiconductor transmission line model of a multiconductor interconnection. It provides accurate results at low and high frequencies. We prove that this model is passive.
{"title":"An analytical resistive loss model for multiconductor transmission lines and the proof of its passivity","authors":"F. Broydé, E. Clavelier","doi":"10.1109/EPEPS.2011.6100203","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100203","url":null,"abstract":"A new model for resistive losses can be used within the multiconductor transmission line model of a multiconductor interconnection. It provides accurate results at low and high frequencies. We prove that this model is passive.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129955405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100215
R. Ding, L. Tsang, H. Braunisch
We study the effects of random roughness on wave propagation in a parallel plate metallic waveguide with finite conductivity. The rough surface is three dimensional (3D) with roughness heights varying in both horizontal directions. Integral equations are obtained from the extinction theorem formulated with layered medium Green's function. The second order small perturbation method is then applied to solve the integral equations. A closed form expression for the coherent wave is derived, which is expressed in terms of a three-fold Sommerfeld type integral due to the waveguide structure. Approximate methods are applied to calculate the Sommerfeld integral. The coherent wave enhancement factors of absorption are computed. The results for waveguides are also compared with the results obtained for a plane wave incident on a metal surface with 3D roughness. Results are illustrated for 3D roughness with a variety of power spectra. It is shown that enhancement factors for a waveguide are larger than that of the plane wave case.
{"title":"Random rough surface effects in interconnects studied by small perturbation theory in waveguide model","authors":"R. Ding, L. Tsang, H. Braunisch","doi":"10.1109/EPEPS.2011.6100215","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100215","url":null,"abstract":"We study the effects of random roughness on wave propagation in a parallel plate metallic waveguide with finite conductivity. The rough surface is three dimensional (3D) with roughness heights varying in both horizontal directions. Integral equations are obtained from the extinction theorem formulated with layered medium Green's function. The second order small perturbation method is then applied to solve the integral equations. A closed form expression for the coherent wave is derived, which is expressed in terms of a three-fold Sommerfeld type integral due to the waveguide structure. Approximate methods are applied to calculate the Sommerfeld integral. The coherent wave enhancement factors of absorption are computed. The results for waveguides are also compared with the results obtained for a plane wave incident on a metal surface with 3D roughness. Results are illustrated for 3D roughness with a variety of power spectra. It is shown that enhancement factors for a waveguide are larger than that of the plane wave case.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133981486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100248
S. Huh, M. Swaminathan, D. Keezer
Return path discontinuities (RPDs) cause the coupling between signal lines and the power delivery network, resulting in power supply noise and reduced timing and voltage margins at high speed. Prior work focused at reducing the RPD effect, usually through the use of power planes and decoupling capacitors. A new approach to address this issue replaces the plane structure with power transmission lines (PTLs), which removes the RPD effect. By eliminating the RPDs, the power supply noise is minimized. Therefore, voltage and timing margins can be improved to support higher data rates. In this paper, the application of the PTL is extended to the transmission of multiple parallel bits, and the resulting waveforms are compared to those using conventional power planes. Also, a new pseudo-balanced signaling scheme is used to further enhance signal integrity when using the PTL approach.
{"title":"Design of power delivery networks using power transmission lines and pseudo-balanced signaling for multiple I/Os","authors":"S. Huh, M. Swaminathan, D. Keezer","doi":"10.1109/EPEPS.2011.6100248","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100248","url":null,"abstract":"Return path discontinuities (RPDs) cause the coupling between signal lines and the power delivery network, resulting in power supply noise and reduced timing and voltage margins at high speed. Prior work focused at reducing the RPD effect, usually through the use of power planes and decoupling capacitors. A new approach to address this issue replaces the plane structure with power transmission lines (PTLs), which removes the RPD effect. By eliminating the RPDs, the power supply noise is minimized. Therefore, voltage and timing margins can be improved to support higher data rates. In this paper, the application of the PTL is extended to the transmission of multiple parallel bits, and the resulting waveforms are compared to those using conventional power planes. Also, a new pseudo-balanced signaling scheme is used to further enhance signal integrity when using the PTL approach.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123557634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100242
D. Klokotov, J. Schutt-Ainé, W. Beyene, D. Mullen, Ming Li, R. Schmitt, Ling Yang
In this paper, a fast circuit simulation technique based on the Latency Insertion Method (LIM) is proposed for the electro-thermal analysis of circuits and high-performance systems. The method is applied to the modeling of on-chip and off-chip 3D-interconnect networks. The proposed method is shown to be capable of modeling both electrical and thermal phenomena occurring in high speed, high performance VLSI circuits at the pre-layout design stages.
{"title":"Application of the latency insertion method to electro-thermal circuit analysis","authors":"D. Klokotov, J. Schutt-Ainé, W. Beyene, D. Mullen, Ming Li, R. Schmitt, Ling Yang","doi":"10.1109/EPEPS.2011.6100242","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100242","url":null,"abstract":"In this paper, a fast circuit simulation technique based on the Latency Insertion Method (LIM) is proposed for the electro-thermal analysis of circuits and high-performance systems. The method is applied to the modeling of on-chip and off-chip 3D-interconnect networks. The proposed method is shown to be capable of modeling both electrical and thermal phenomena occurring in high speed, high performance VLSI circuits at the pre-layout design stages.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121808680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100178
Ho-Hsin Yeh, N. Hiramatsu, K. Melde
Free space wireless transmission via the 60 GHz antenna in the Multi-Chip Multi-Core (MCMC) architecture is proposed in this paper. Antenna in package (AiP) solution is chosen as the 60GHz antenna configuration and the antenna is designed based on low temperature co-fired ceramic (LTCC) superstrate that could connect to the silicon circuitry via the flip-chip technology. The designed antenna having ground shielded structures and the artificial magnetic conductor (AMC) will demonstrate the azimuth plane signal transmission with the high radiation efficiency.
提出了一种基于多芯片多核(MCMC)架构的60ghz天线自由空间无线传输方案。60GHz天线配置采用封装天线(Antenna in package, AiP)方案，采用低温共烧陶瓷(LTCC)衬底设计，可通过倒装芯片技术与硅电路连接。所设计的天线具有接地屏蔽结构和人工磁导体(AMC)，能够以较高的辐射效率传输方位面信号。
{"title":"Wireless RF data communications using 60 GHz antennas in Multi-Core systems","authors":"Ho-Hsin Yeh, N. Hiramatsu, K. Melde","doi":"10.1109/EPEPS.2011.6100178","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100178","url":null,"abstract":"Free space wireless transmission via the 60 GHz antenna in the Multi-Chip Multi-Core (MCMC) architecture is proposed in this paper. Antenna in package (AiP) solution is chosen as the 60GHz antenna configuration and the antenna is designed based on low temperature co-fired ceramic (LTCC) superstrate that could connect to the silicon circuitry via the flip-chip technology. The designed antenna having ground shielded structures and the artificial magnetic conductor (AMC) will demonstrate the azimuth plane signal transmission with the high radiation efficiency.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122014920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-12DOI: 10.1109/EPEPS.2011.6100225
A. Dey, H. Song
Timing jitter remains one of the most important design issues for successful operation of high speed serial links. This abstract introduces methods to model and estimate data dependent jitter (DDJ), in presence of capacitive and inductive discontinuities that result due to vias and right angular bends. The model shows that these discontinuities can have significant impact on DDJ, especially at high data rates. The proposed model is extensively verified with SPICE and show very good results.
{"title":"Modeling of ISI in high speed serial I/Os terminated with discontinuities","authors":"A. Dey, H. Song","doi":"10.1109/EPEPS.2011.6100225","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100225","url":null,"abstract":"Timing jitter remains one of the most important design issues for successful operation of high speed serial links. This abstract introduces methods to model and estimate data dependent jitter (DDJ), in presence of capacitive and inductive discontinuities that result due to vias and right angular bends. The model shows that these discontinuities can have significant impact on DDJ, especially at high data rates. The proposed model is extensively verified with SPICE and show very good results.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129034937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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