Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896977
Min-Do Kwon, S. Seo, Il-Ki Kim
The EFMCU (Embedded Flash MCU) for digital multimedia applications is designed and fabricated with a ARM7TDMI/sup TM/ CPU core, 192 K bytes flash memory, 4 K bytes SRAM, 10-bit ADC and various functional peripherals. These modules are connected to AMBA (Advanced Microcontroller Bus Architecture) bus. The EFMCU is operated with a clock frequency of 66 MHz at 3.3 V single power, and can support both on-chip and on-board programming of the embedded flash. The technology of EFMCU is the 0.35 /spl mu/m triple-well 2-poly 3-Metal CMOS process. The chip size is 36.8 mm/sup 2/, and the package type is 100 TQFP.
{"title":"A cost-effective 16-bit embedded flash MCU for digital multimedia applications","authors":"Min-Do Kwon, S. Seo, Il-Ki Kim","doi":"10.1109/APASIC.2000.896977","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896977","url":null,"abstract":"The EFMCU (Embedded Flash MCU) for digital multimedia applications is designed and fabricated with a ARM7TDMI/sup TM/ CPU core, 192 K bytes flash memory, 4 K bytes SRAM, 10-bit ADC and various functional peripherals. These modules are connected to AMBA (Advanced Microcontroller Bus Architecture) bus. The EFMCU is operated with a clock frequency of 66 MHz at 3.3 V single power, and can support both on-chip and on-board programming of the embedded flash. The technology of EFMCU is the 0.35 /spl mu/m triple-well 2-poly 3-Metal CMOS process. The chip size is 36.8 mm/sup 2/, and the package type is 100 TQFP.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124050520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896968
Seungjong Lee, Moo-Kyung Jung, I. Park, C. Kyung
This paper presents a behavioral emulation system called iSAVE (in-System Algorithm Verification), which performs in-system verification of the behavioral description in C of a chip in the context of its application board at the early design stage. We were able to significantly increase the emulation speed by modeling the interface of the target chip with both the software part, which runs as thread, and the hardware part, mapped into FPGA logic. The proposed idea is validated by demonstrating the behavioral emulation of MP3 decoder chip, as obtained from the public domain MP3 program.
本文提出了一种名为iSAVE (in- system Algorithm Verification)的行为仿真系统，该系统在设计初期就在应用板的背景下对芯片的C语言行为描述进行系统内验证。通过将软件部分(作为线程运行)和硬件部分映射到FPGA逻辑中，对目标芯片的接口进行建模，我们能够显著提高仿真速度。通过对MP3解码器芯片的行为仿真，验证了所提思想的有效性。
{"title":"iSAVE: a behavioral emulator for in-system algorithm verification","authors":"Seungjong Lee, Moo-Kyung Jung, I. Park, C. Kyung","doi":"10.1109/APASIC.2000.896968","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896968","url":null,"abstract":"This paper presents a behavioral emulation system called iSAVE (in-System Algorithm Verification), which performs in-system verification of the behavioral description in C of a chip in the context of its application board at the early design stage. We were able to significantly increase the emulation speed by modeling the interface of the target chip with both the software part, which runs as thread, and the hardware part, mapped into FPGA logic. The proposed idea is validated by demonstrating the behavioral emulation of MP3 decoder chip, as obtained from the public domain MP3 program.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126934777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896954
Sung-Woo Kwon, J. Kwak, D. Roh, Dongku Kim, M. Lee
We propose an architecture of a new frequency-efficient W-CDMA system that saves the spectrum from 36864 MHz to 2.458 MHz to accommodate the IS-95 narrowband CDMA system by using vestigial sideband (VSB) modulation. In addition, we introduce new cost-effective low-power design technique called CSD-CSCF (Canonical Signed Digit-Common Sub-coefficient Common Filter) and common energy calculator to alleviate the additional hardware cost that is needed to accomplish the VSB modulation and to obtain performance identical to that of the double sideband (DSB) system. It is shown that the proposed VSB W-CDMA system has 30% less spectrum than the DSB W-CDMA system and 30.6% less hardware cost than the system neither exploiting CSD-CSCF nor common energy calculator architectures.
{"title":"Cost-effective low-power architecture of vestigial sideband W-CDMA system","authors":"Sung-Woo Kwon, J. Kwak, D. Roh, Dongku Kim, M. Lee","doi":"10.1109/APASIC.2000.896954","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896954","url":null,"abstract":"We propose an architecture of a new frequency-efficient W-CDMA system that saves the spectrum from 36864 MHz to 2.458 MHz to accommodate the IS-95 narrowband CDMA system by using vestigial sideband (VSB) modulation. In addition, we introduce new cost-effective low-power design technique called CSD-CSCF (Canonical Signed Digit-Common Sub-coefficient Common Filter) and common energy calculator to alleviate the additional hardware cost that is needed to accomplish the VSB modulation and to obtain performance identical to that of the double sideband (DSB) system. It is shown that the proposed VSB W-CDMA system has 30% less spectrum than the DSB W-CDMA system and 30.6% less hardware cost than the system neither exploiting CSD-CSCF nor common energy calculator architectures.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128943292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896933
D. Yamazaki, S. Ide, T. Chiba, A. Hayakawa, H. Rokugawa, M. Kawai
A 3R one chip IC at 156 Mbit/s using PLL retiming technology has been fabricated with a 0.35 /spl mu/m CMOS. We developed a new voltage controlled oscillator (VCO) that has less deviation of free run frequency so that any adjustment is not required. We have also developed a wide dynamic range preamplifier. The use of this preamplifier and VCO realizes a 38 dB dynamic range without any requirement for adjustment of a PLL.
利用锁相环重定时技术，采用0.35 /spl μ m CMOS，制作了156mbit /s的3R单片集成电路。我们开发了一种新的电压控制振荡器(VCO)，它具有较小的自由运行频率偏差，因此不需要任何调整。我们还开发了一种宽动态范围前置放大器。使用该前置放大器和压控振荡器实现38db动态范围，无需调整锁相环。
{"title":"3R one chip CMOS IC at 156 Mbit/s","authors":"D. Yamazaki, S. Ide, T. Chiba, A. Hayakawa, H. Rokugawa, M. Kawai","doi":"10.1109/APASIC.2000.896933","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896933","url":null,"abstract":"A 3R one chip IC at 156 Mbit/s using PLL retiming technology has been fabricated with a 0.35 /spl mu/m CMOS. We developed a new voltage controlled oscillator (VCO) that has less deviation of free run frequency so that any adjustment is not required. We have also developed a wide dynamic range preamplifier. The use of this preamplifier and VCO realizes a 38 dB dynamic range without any requirement for adjustment of a PLL.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130456360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896917
M. Nogawa, Y. Ohtomo
A new high-speed dynamic CMOS frequency divider that operates at frequencies of over 16 GHz is proposed. The core of the proposed 2:1 divider consists of only three inverters and one transmission gate, and it has no DC current. Using the 2:1 divider, we developed a 64:1 divider with 0.2-/spl mu/m CMOS/SIMOX technology. Experimental results show that the maximum input frequency of the proposed divider is 1.4 times as high as that of a conventional one. The proposed 64:1 divider has a high input frequency of 16.3 GHz with a power consumption of 45 mW at 2.0-V power supply, and a low power consumption of 2.0 mW with a input frequency of 7.0 GHz at 0.8-V power supply.
{"title":"A 16.3-GHz 64:1 CMOS frequency divider","authors":"M. Nogawa, Y. Ohtomo","doi":"10.1109/APASIC.2000.896917","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896917","url":null,"abstract":"A new high-speed dynamic CMOS frequency divider that operates at frequencies of over 16 GHz is proposed. The core of the proposed 2:1 divider consists of only three inverters and one transmission gate, and it has no DC current. Using the 2:1 divider, we developed a 64:1 divider with 0.2-/spl mu/m CMOS/SIMOX technology. Experimental results show that the maximum input frequency of the proposed divider is 1.4 times as high as that of a conventional one. The proposed 64:1 divider has a high input frequency of 16.3 GHz with a power consumption of 45 mW at 2.0-V power supply, and a low power consumption of 2.0 mW with a input frequency of 7.0 GHz at 0.8-V power supply.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132544382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896906
J. Terada, Y. Matsuya, F. Morisawa, Y. Kado
A very low-power, high-speed flash A/D converter front-end composed of a new transconductance latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at 1 V and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.
{"title":"8-mW, 1-V, 100-Msps, 6-bit A/D converter using a transconductance latched comparator","authors":"J. Terada, Y. Matsuya, F. Morisawa, Y. Kado","doi":"10.1109/APASIC.2000.896906","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896906","url":null,"abstract":"A very low-power, high-speed flash A/D converter front-end composed of a new transconductance latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at 1 V and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131891746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896928
Honam Lee, Bonggeun Lee, Youngho Lee, B. Kang
Proposes the optimized hardware architecture for a high performance image downscaler. The proposed downscaler uses nonlinear digital filters for horizontal and vertical scalings. In order to achieve the optimization the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The usefulness of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using VHDL and implemented by using the IDEC-C632 0.65 /spl mu/m cell library.
{"title":"Optimized VLSI design for enhanced image downscaler","authors":"Honam Lee, Bonggeun Lee, Youngho Lee, B. Kang","doi":"10.1109/APASIC.2000.896928","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896928","url":null,"abstract":"Proposes the optimized hardware architecture for a high performance image downscaler. The proposed downscaler uses nonlinear digital filters for horizontal and vertical scalings. In order to achieve the optimization the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The usefulness of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using VHDL and implemented by using the IDEC-C632 0.65 /spl mu/m cell library.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133281468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896914
Zhi-Ming Lin, K. Huang, Jun-Da Chen, Mei-Yuan Liao
A CMOS ring-oscillator VCO with temperature compensation has been designed by using 0.6 /spl mu/m CMOS technology. The proposed VCO has a wide operating range from 224 MHz to 974 MHz with a good linearity between the output frequency and the control input voltage. The operating frequency has a temperature coefficient of 86.3 ppm//spl deg/C in the 15/spl sim/125/spl deg/C range. The power consumption of this VCO is 8.3 mW.
采用0.6 /spl μ m CMOS工艺设计了一种带温度补偿的CMOS环振压控振荡器。所提出的VCO工作范围从224 MHz到974 MHz，输出频率和控制输入电压之间具有良好的线性关系。在15/spl sim/125/spl℃范围内，工作频率的温度系数为86.3 ppm//spl℃。该VCO的功耗为8.3 mW。
{"title":"A CMOS voltage-controlled oscillator with temperature compensation","authors":"Zhi-Ming Lin, K. Huang, Jun-Da Chen, Mei-Yuan Liao","doi":"10.1109/APASIC.2000.896914","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896914","url":null,"abstract":"A CMOS ring-oscillator VCO with temperature compensation has been designed by using 0.6 /spl mu/m CMOS technology. The proposed VCO has a wide operating range from 224 MHz to 974 MHz with a good linearity between the output frequency and the control input voltage. The operating frequency has a temperature coefficient of 86.3 ppm//spl deg/C in the 15/spl sim/125/spl deg/C range. The power consumption of this VCO is 8.3 mW.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129371696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896971
Sanghun Park, Kijo Lee, Changbum Im, N. Kwak, Kihyun Kim, Youngdoo Choi
This paper describes practical issues on designing and implementing industrial built-in self-test circuits for embedded memory test. The proposed test circuits are power conscious, fault locatable, and scan-based-test friendly. These features are notable and useful practically in system-on-a-chip design test because many memories that are repairable and large-sized are commonly embedded in the design. We applied the proposed test circuits to actual RAMs available in industry. Experimental results show that the test circuits are powerful for the RAM test with small penalties of area, delay, and power consumption, compared with no use of the test circuit. Furthermore, the test circuits improve the scan-based testability for the glue logic surrounding the RAMs.
{"title":"Designing built-in self-test circuits for embedded memories test","authors":"Sanghun Park, Kijo Lee, Changbum Im, N. Kwak, Kihyun Kim, Youngdoo Choi","doi":"10.1109/APASIC.2000.896971","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896971","url":null,"abstract":"This paper describes practical issues on designing and implementing industrial built-in self-test circuits for embedded memory test. The proposed test circuits are power conscious, fault locatable, and scan-based-test friendly. These features are notable and useful practically in system-on-a-chip design test because many memories that are repairable and large-sized are commonly embedded in the design. We applied the proposed test circuits to actual RAMs available in industry. Experimental results show that the test circuits are powerful for the RAM test with small penalties of area, delay, and power consumption, compared with no use of the test circuit. Furthermore, the test circuits improve the scan-based testability for the glue logic surrounding the RAMs.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115947910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896951
J. Bae, Seong-Jun Kyung, M. Ahn, Seong-Sik Kim, Ji-Soo Lim, Wook-Jin Cha, Jong-Oh Lee, H. Kwon, Se-Jin Yoo, Dong-Soo Cho, Jay S. Chae
Evolutional enhancement in VLSI technology makes a complicated system integrated in a chip. To design a system with large complexity, well-designed macro block, IP (Intellectual Property), is preferred to reduce design time enormously. A system, named ART (automatic RTL translation), is developed to generate synthesizable RTL IPs from legacy hard macros. With help of the ART system, we developed a soft IP of an 8-bit embedded microcontroller. The operating frequency of the IP is up to 80 MHz with a 0.6 /spl mu/m CMOS technology. An MCU for Digital Tuning System (DTS) was also developed using the IP with the same technology.
{"title":"An efficient system to develop various soft IPs","authors":"J. Bae, Seong-Jun Kyung, M. Ahn, Seong-Sik Kim, Ji-Soo Lim, Wook-Jin Cha, Jong-Oh Lee, H. Kwon, Se-Jin Yoo, Dong-Soo Cho, Jay S. Chae","doi":"10.1109/APASIC.2000.896951","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896951","url":null,"abstract":"Evolutional enhancement in VLSI technology makes a complicated system integrated in a chip. To design a system with large complexity, well-designed macro block, IP (Intellectual Property), is preferred to reduce design time enormously. A system, named ART (automatic RTL translation), is developed to generate synthesizable RTL IPs from legacy hard macros. With help of the ART system, we developed a soft IP of an 8-bit embedded microcontroller. The operating frequency of the IP is up to 80 MHz with a 0.6 /spl mu/m CMOS technology. An MCU for Digital Tuning System (DTS) was also developed using the IP with the same technology.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116078620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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