Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896904
J. Chung, K. Yoon
A low power 10 bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent the ADC from increasing the FR excessively, but also to perform at high resolution with a single power supply of 3.3 V. The proposed ADC is implemented by a 0.6 /spl mu/m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of /spl plusmn/0.5 LSB, an integral nonlinearity (INL) of /spl plusmn/1.0 LSB.
{"title":"Design of 3.3 V 10 bit current-mode folding/interpolating CMOS A/D converter with an arithmetic functionality","authors":"J. Chung, K. Yoon","doi":"10.1109/APASIC.2000.896904","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896904","url":null,"abstract":"A low power 10 bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent the ADC from increasing the FR excessively, but also to perform at high resolution with a single power supply of 3.3 V. The proposed ADC is implemented by a 0.6 /spl mu/m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of /spl plusmn/0.5 LSB, an integral nonlinearity (INL) of /spl plusmn/1.0 LSB.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133045276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896922
Y. Hung, Bin-Da Liu
In this paper, a multiple function filter with configurable capability for 1-V supply voltage is proposed. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover without modifying the circuit, the WTA/k-WTA, maximum, minimum and medium function can be easily configured. The circuit has been designed using 0.5 /spl mu/m 2P2M CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE simulation show that the operating speed of the circuit is 2 /spl mu/s for each rank-order operation, that the input dynamic range is rail-to-rail, and that the resolution is 10 mV for 1 V supply voltage. The static power dissipation of the circuit is 11 /spl mu/W.
{"title":"A 1-V low power rail-to-rail analog CMOS multi-function filter with configurable capability","authors":"Y. Hung, Bin-Da Liu","doi":"10.1109/APASIC.2000.896922","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896922","url":null,"abstract":"In this paper, a multiple function filter with configurable capability for 1-V supply voltage is proposed. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover without modifying the circuit, the WTA/k-WTA, maximum, minimum and medium function can be easily configured. The circuit has been designed using 0.5 /spl mu/m 2P2M CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE simulation show that the operating speed of the circuit is 2 /spl mu/s for each rank-order operation, that the input dynamic range is rail-to-rail, and that the resolution is 10 mV for 1 V supply voltage. The static power dissipation of the circuit is 11 /spl mu/W.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124966032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896917
M. Nogawa, Y. Ohtomo
A new high-speed dynamic CMOS frequency divider that operates at frequencies of over 16 GHz is proposed. The core of the proposed 2:1 divider consists of only three inverters and one transmission gate, and it has no DC current. Using the 2:1 divider, we developed a 64:1 divider with 0.2-/spl mu/m CMOS/SIMOX technology. Experimental results show that the maximum input frequency of the proposed divider is 1.4 times as high as that of a conventional one. The proposed 64:1 divider has a high input frequency of 16.3 GHz with a power consumption of 45 mW at 2.0-V power supply, and a low power consumption of 2.0 mW with a input frequency of 7.0 GHz at 0.8-V power supply.
{"title":"A 16.3-GHz 64:1 CMOS frequency divider","authors":"M. Nogawa, Y. Ohtomo","doi":"10.1109/APASIC.2000.896917","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896917","url":null,"abstract":"A new high-speed dynamic CMOS frequency divider that operates at frequencies of over 16 GHz is proposed. The core of the proposed 2:1 divider consists of only three inverters and one transmission gate, and it has no DC current. Using the 2:1 divider, we developed a 64:1 divider with 0.2-/spl mu/m CMOS/SIMOX technology. Experimental results show that the maximum input frequency of the proposed divider is 1.4 times as high as that of a conventional one. The proposed 64:1 divider has a high input frequency of 16.3 GHz with a power consumption of 45 mW at 2.0-V power supply, and a low power consumption of 2.0 mW with a input frequency of 7.0 GHz at 0.8-V power supply.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132544382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896906
J. Terada, Y. Matsuya, F. Morisawa, Y. Kado
A very low-power, high-speed flash A/D converter front-end composed of a new transconductance latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at 1 V and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.
{"title":"8-mW, 1-V, 100-Msps, 6-bit A/D converter using a transconductance latched comparator","authors":"J. Terada, Y. Matsuya, F. Morisawa, Y. Kado","doi":"10.1109/APASIC.2000.896906","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896906","url":null,"abstract":"A very low-power, high-speed flash A/D converter front-end composed of a new transconductance latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at 1 V and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131891746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896928
Honam Lee, Bonggeun Lee, Youngho Lee, B. Kang
Proposes the optimized hardware architecture for a high performance image downscaler. The proposed downscaler uses nonlinear digital filters for horizontal and vertical scalings. In order to achieve the optimization the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The usefulness of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using VHDL and implemented by using the IDEC-C632 0.65 /spl mu/m cell library.
{"title":"Optimized VLSI design for enhanced image downscaler","authors":"Honam Lee, Bonggeun Lee, Youngho Lee, B. Kang","doi":"10.1109/APASIC.2000.896928","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896928","url":null,"abstract":"Proposes the optimized hardware architecture for a high performance image downscaler. The proposed downscaler uses nonlinear digital filters for horizontal and vertical scalings. In order to achieve the optimization the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The usefulness of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using VHDL and implemented by using the IDEC-C632 0.65 /spl mu/m cell library.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133281468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896902
Kuo-Hsing Cheng, Yung-Chong Huang
In this paper, a new TSPC logic circuit is proposed for low-voltage high-speed applications. The proposed new circuit using non-full voltage swing scheme in internal nodes to reduce logic evaluation time and to save dynamic power. Thus the advantages of the new TSPC logic circuit over the conventional TSPC logic circuit are speed and power-delay product. Based upon the 0.35 /spl mu/m CMOS technology, the proposed new TSPC logic has 25% improvement over the conventional TSPC circuit in power-delay product. The new circuit can be operated at 250 MHz with 1.2 V supply voltage.
{"title":"The non-full voltage swing TSPC (NSTSPC) logic design","authors":"Kuo-Hsing Cheng, Yung-Chong Huang","doi":"10.1109/APASIC.2000.896902","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896902","url":null,"abstract":"In this paper, a new TSPC logic circuit is proposed for low-voltage high-speed applications. The proposed new circuit using non-full voltage swing scheme in internal nodes to reduce logic evaluation time and to save dynamic power. Thus the advantages of the new TSPC logic circuit over the conventional TSPC logic circuit are speed and power-delay product. Based upon the 0.35 /spl mu/m CMOS technology, the proposed new TSPC logic has 25% improvement over the conventional TSPC circuit in power-delay product. The new circuit can be operated at 250 MHz with 1.2 V supply voltage.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116494006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896893
W. Song, C. Oh, G. Cho, H. Jung
A novel CMOS Variable Gain Amplifier (VGA) with high frequency and high dynamic range is proposed. It has a controllable gain range from -45 dB to +45 dB by external control voltage as well as enhanced operating frequency up to 200 MHz. It is fabricated in 0.35 /spl mu/m CMOS technology with the core area of 580 /spl mu/m/spl times/660 /spl mu/m. It consumes only 10.8 mA at 3.3 V supply voltage.
{"title":"A 200 MHz/90 dB gain range CMOS VGA","authors":"W. Song, C. Oh, G. Cho, H. Jung","doi":"10.1109/APASIC.2000.896893","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896893","url":null,"abstract":"A novel CMOS Variable Gain Amplifier (VGA) with high frequency and high dynamic range is proposed. It has a controllable gain range from -45 dB to +45 dB by external control voltage as well as enhanced operating frequency up to 200 MHz. It is fabricated in 0.35 /spl mu/m CMOS technology with the core area of 580 /spl mu/m/spl times/660 /spl mu/m. It consumes only 10.8 mA at 3.3 V supply voltage.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"339 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115701344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896915
Myung-woon Hwang, J. Hwang, G. Cho
A high-speed divide-by-2 prescaler is designed in a 0.8 um CMOS. New ECL-like D flip-flop is proposed having source-folded diode clamping. Significant amount of speed up can be obtained using source-folded diode with proper sizing ratio of transistors, and lower power consumption can be obtained by designing low power D flip-flop and removing additional input-amplifying buffer. The simulated maximum input frequency of the suggested prescaler reaches up to 3.15 GHz with only 5 mA and 1.8 GHz with 1.6 mA at 3.3 V.
在0.8 um CMOS上设计了一个高速除以2的预分频器。提出了一种具有源折叠二极管箝位的新型类ecl D触发器。采用适当晶体管尺寸比的源折叠二极管可以获得显著的速度提升，通过设计低功耗D触发器并去除额外的输入放大缓冲器可以降低功耗。该预分频器的模拟最大输入频率在5ma时可达3.15 GHz，在3.3 V时1.6 mA时可达1.8 GHz。
{"title":"Design of high speed CMOS prescaler","authors":"Myung-woon Hwang, J. Hwang, G. Cho","doi":"10.1109/APASIC.2000.896915","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896915","url":null,"abstract":"A high-speed divide-by-2 prescaler is designed in a 0.8 um CMOS. New ECL-like D flip-flop is proposed having source-folded diode clamping. Significant amount of speed up can be obtained using source-folded diode with proper sizing ratio of transistors, and lower power consumption can be obtained by designing low power D flip-flop and removing additional input-amplifying buffer. The simulated maximum input frequency of the suggested prescaler reaches up to 3.15 GHz with only 5 mA and 1.8 GHz with 1.6 mA at 3.3 V.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123396066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896927
T. Nezuka, J. Akita, M. Ikeda, K. Asada
The quad-tree scan is realized by scanning nodes of a two-dimensional tree structure applied to the image. Only activated or effective pixels are scanned with quad-tree scan. We designed the image sensor using 0.6 /spl mu/m CMOS 3-metal 2-poly-Si process. A 32/spl times/32 pixel array and a quad-tree scan controller are integrated on a 4.5 mm/spl times/4.5 mm die. Each pixel has an A/D conversion circuit and a motion detection circuit in a 96 /spl mu/m/spl times/96 /spl mu/m area. The quad-tree scan controller works at 10 Mcycles/s with 10 mW power dissipation.
{"title":"A smart image sensor with novel implementation of quad-tree scan","authors":"T. Nezuka, J. Akita, M. Ikeda, K. Asada","doi":"10.1109/APASIC.2000.896927","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896927","url":null,"abstract":"The quad-tree scan is realized by scanning nodes of a two-dimensional tree structure applied to the image. Only activated or effective pixels are scanned with quad-tree scan. We designed the image sensor using 0.6 /spl mu/m CMOS 3-metal 2-poly-Si process. A 32/spl times/32 pixel array and a quad-tree scan controller are integrated on a 4.5 mm/spl times/4.5 mm die. Each pixel has an A/D conversion circuit and a motion detection circuit in a 96 /spl mu/m/spl times/96 /spl mu/m area. The quad-tree scan controller works at 10 Mcycles/s with 10 mW power dissipation.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124724155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896972
Daehan Youn, Ohyoung Song, Hoon Chang
This paper describes design-for-testability of the floating point digital signal processor, called FLOVA, which is based on VLIW architecture with 4 stage pipeline operation. Full-scan design, BIST (Built-In-Self-Test), and IEEE 1149.1 boundary-scan are applied to the flip-flops, the floating point processing units/the embedded memory units, and the I/O cells, respectively.
{"title":"Design-for-testability of the FLOVA","authors":"Daehan Youn, Ohyoung Song, Hoon Chang","doi":"10.1109/APASIC.2000.896972","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896972","url":null,"abstract":"This paper describes design-for-testability of the floating point digital signal processor, called FLOVA, which is based on VLIW architecture with 4 stage pipeline operation. Full-scan design, BIST (Built-In-Self-Test), and IEEE 1149.1 boundary-scan are applied to the flip-flops, the floating point processing units/the embedded memory units, and the I/O cells, respectively.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121987590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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