Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896932
Po-Chiun Huang, Yi-Huei Chen, Chien-Chih Liu, Chorng-Kuang Wang
This paper presents a low-voltage low-power IF 455 kHz signal processor that contains a three-stage limiting amplifier and an FM/FSK demodulator. The limiting amplifier uses an on-chip feedforward offset cancellation circuit. The FM/FSK demodulator employs a quadrature detector that is composed of an on-chip phase detector and an external tank phase shifter. The demodulation constant is 20 mV/kHz with maximum /spl plusmn/10 kHz frequency deviation. The IF signal processor that consumes 2.3 mW from a single 2-V power supply demonstrates a high sensitivity of -72 dBm. It occupies an active area of 0.2 mm/sup 2/ using 0.6 /spl mu/m digital CMOS technology.
{"title":"A 2-V CMOS 455 kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier","authors":"Po-Chiun Huang, Yi-Huei Chen, Chien-Chih Liu, Chorng-Kuang Wang","doi":"10.1109/APASIC.2000.896932","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896932","url":null,"abstract":"This paper presents a low-voltage low-power IF 455 kHz signal processor that contains a three-stage limiting amplifier and an FM/FSK demodulator. The limiting amplifier uses an on-chip feedforward offset cancellation circuit. The FM/FSK demodulator employs a quadrature detector that is composed of an on-chip phase detector and an external tank phase shifter. The demodulation constant is 20 mV/kHz with maximum /spl plusmn/10 kHz frequency deviation. The IF signal processor that consumes 2.3 mW from a single 2-V power supply demonstrates a high sensitivity of -72 dBm. It occupies an active area of 0.2 mm/sup 2/ using 0.6 /spl mu/m digital CMOS technology.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114278938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896953
J. Ryoo, G. Cho
Describes the design of 2 GHz LC-oscillator for IMT-2000 frequency band application. The LC-oscillator has a simple automatic swing control circuit for providing constant output power to mixer and prescaler. Total circuit consists of oscillator core, buffer, bandgap reference and drive amp. The oscillator core consumes 1.3 mA. A frequency tuning range is about 360 MHz. The output power of the LC-oscillator varies within 1.1 dBm. This chip is implemented in 60 GHz SiGe BiCMOS process by ST Microelectronics. Total power consumption is 31.5 mW at a 2.7 V single power supply.
{"title":"A 2 GHz LC-oscillator with automatic swing control for IMT-2000 application","authors":"J. Ryoo, G. Cho","doi":"10.1109/APASIC.2000.896953","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896953","url":null,"abstract":"Describes the design of 2 GHz LC-oscillator for IMT-2000 frequency band application. The LC-oscillator has a simple automatic swing control circuit for providing constant output power to mixer and prescaler. Total circuit consists of oscillator core, buffer, bandgap reference and drive amp. The oscillator core consumes 1.3 mA. A frequency tuning range is about 360 MHz. The output power of the LC-oscillator varies within 1.1 dBm. This chip is implemented in 60 GHz SiGe BiCMOS process by ST Microelectronics. Total power consumption is 31.5 mW at a 2.7 V single power supply.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114807887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896907
Tae-Hyoung Kim, J. Sung, S. Kim, Woong Joo, Seung-Bin You, Suki Kim
This paper describes a 10-bit, 10-Msamples/s CMOS folding and interpolating analog-to-digital converter (F&I ADC). A new cascading architecture is proposed to reduce the number of comparators and power consumption, and to increase input signal bandwidth. To reduce the nonlinear errors in the sample-and-holder (S/H), a charge-pump circuit is used. By using a wide range error correction scheme, the relaxed design of comparators is possible. The ADC was designed using a 0.25 /spl mu/m 1-poly 5-metal CMOS process. It consumes 62 mW at 40 Msamples/s. The INL/DNL is less than 0.5 LSB/0.4 LSB by MATLAB presimulation.
{"title":"A 10-bit, 40 Msamples/s cascading folding and interpolating A/D converter with wide range error correction","authors":"Tae-Hyoung Kim, J. Sung, S. Kim, Woong Joo, Seung-Bin You, Suki Kim","doi":"10.1109/APASIC.2000.896907","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896907","url":null,"abstract":"This paper describes a 10-bit, 10-Msamples/s CMOS folding and interpolating analog-to-digital converter (F&I ADC). A new cascading architecture is proposed to reduce the number of comparators and power consumption, and to increase input signal bandwidth. To reduce the nonlinear errors in the sample-and-holder (S/H), a charge-pump circuit is used. By using a wide range error correction scheme, the relaxed design of comparators is possible. The ADC was designed using a 0.25 /spl mu/m 1-poly 5-metal CMOS process. It consumes 62 mW at 40 Msamples/s. The INL/DNL is less than 0.5 LSB/0.4 LSB by MATLAB presimulation.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115115376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896985
Young-Wook Jeon, Young-Su Kwon, Y. Im, Jun-Hee Lee, S. Nam, Byung-Woon Kim, C. Kyung
To process enormous 3D data, we have designed a VLIW (Very Long Instruction Word) processor called FLOVA (Floating-Point VLIW Architecture) exploiting the ILP (Instruction-Level Parallelism) in 3D programs. This paper presents FGA (FLOVA Geometry Accelerator) that is the 3D graphics system and it almost removes the time required to process in the geometry stage. We have developed the 3D graphics library, FGA-GL, to supports the FGA system. The deferred primitive rendering algorithm of FGA-GL enables the geometry processing of the primitive data to be done concurrently with the host job such as primitive data management or game play. FGA improves the average performance of 3D graphics system by 2.5-3.0.
为了处理大量的3D数据，我们设计了一个名为FLOVA(浮点VLIW架构)的VLIW (Very Long Instruction Word)处理器，利用了3D程序中的ILP(指令级并行性)。本文介绍了三维图形系统FGA (FLOVA Geometry Accelerator)，它几乎省去了几何阶段的处理时间。我们开发了3D图形库FGA- gl来支持FGA系统。FGA-GL的延迟原语呈现算法使原语数据的几何处理能够与主机作业(如原语数据管理或游戏)并发完成。FGA使三维图形系统的平均性能提高2.5-3.0。
{"title":"3D graphics system with VLIW processor for geometry acceleration","authors":"Young-Wook Jeon, Young-Su Kwon, Y. Im, Jun-Hee Lee, S. Nam, Byung-Woon Kim, C. Kyung","doi":"10.1109/APASIC.2000.896985","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896985","url":null,"abstract":"To process enormous 3D data, we have designed a VLIW (Very Long Instruction Word) processor called FLOVA (Floating-Point VLIW Architecture) exploiting the ILP (Instruction-Level Parallelism) in 3D programs. This paper presents FGA (FLOVA Geometry Accelerator) that is the 3D graphics system and it almost removes the time required to process in the geometry stage. We have developed the 3D graphics library, FGA-GL, to supports the FGA system. The deferred primitive rendering algorithm of FGA-GL enables the geometry processing of the primitive data to be done concurrently with the host job such as primitive data management or game play. FGA improves the average performance of 3D graphics system by 2.5-3.0.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115683430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896960
Hyeokman Kwon, Joohyeong Moon, Jinsoo Byun, Sangwook Park, Jinyong Chung
An intelligent method of repair analysis that can repair a RAM block with 4 spare rows and 4 spare columns is implemented with CAM that has the function of datamatch, count-sub-entry, search-empty-entry. The key idea of this algorithm is on-the-fly repair analysis by rearrangement of the CAM array contents and repair analysis processing by one row or one column unit with a dual error buffer.
{"title":"Linear search algorithm for repair analysis with 4 spare row/4 spare column","authors":"Hyeokman Kwon, Joohyeong Moon, Jinsoo Byun, Sangwook Park, Jinyong Chung","doi":"10.1109/APASIC.2000.896960","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896960","url":null,"abstract":"An intelligent method of repair analysis that can repair a RAM block with 4 spare rows and 4 spare columns is implemented with CAM that has the function of datamatch, count-sub-entry, search-empty-entry. The key idea of this algorithm is on-the-fly repair analysis by rearrangement of the CAM array contents and repair analysis processing by one row or one column unit with a dual error buffer.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129025620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896986
Y. Sasaki, K. Yano
Our method of calculating crosstalk delay degradation for timing analysis provides the quantitative degradation even when the signal arrival times change dynamically depending on the input patterns and there are multiple aggressors for one victim. We have developed a means of library building that makes it possible to accelerate the calculation speed by using characteristic-point-based representation for the delay degradation table. We have also determined effective parameters for representing typical conditions in the library.
{"title":"Building a crosstalk library for relative window methods-timing analysis that includes crosstalk delay degradation","authors":"Y. Sasaki, K. Yano","doi":"10.1109/APASIC.2000.896986","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896986","url":null,"abstract":"Our method of calculating crosstalk delay degradation for timing analysis provides the quantitative degradation even when the signal arrival times change dynamically depending on the input patterns and there are multiple aggressors for one victim. We have developed a means of library building that makes it possible to accelerate the calculation speed by using characteristic-point-based representation for the delay degradation table. We have also determined effective parameters for representing typical conditions in the library.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124690885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896955
Myung-Soon Kim, Dae-Ik Kim, Jin-Gyun Chung, M. Lim
In this paper, an efficient pulse shaping filter architecture for SSB/BPSK-DS/CDMA is proposed. The filter satisfies the specifications in 1S-95. The proposed architecture is based on polyphase decomposition and look-up table method. By exploiting the linear phase property of the decomposed filter coefficients, the chip area required for the look-up table can be reduced by half compared with the conventional methods. By Synopsys simulations, it is shown that the use of the proposed method can result in reduction in the number of gates by 43%.
{"title":"1:N interpolation FIR filter design for SSB/BPSK-DS/CDMA","authors":"Myung-Soon Kim, Dae-Ik Kim, Jin-Gyun Chung, M. Lim","doi":"10.1109/APASIC.2000.896955","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896955","url":null,"abstract":"In this paper, an efficient pulse shaping filter architecture for SSB/BPSK-DS/CDMA is proposed. The filter satisfies the specifications in 1S-95. The proposed architecture is based on polyphase decomposition and look-up table method. By exploiting the linear phase property of the decomposed filter coefficients, the chip area required for the look-up table can be reduced by half compared with the conventional methods. By Synopsys simulations, it is shown that the use of the proposed method can result in reduction in the number of gates by 43%.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121374044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896973
Kilwhan Lee, Jang-Soo Lee, G. Park, Jung-Hoon Lee, T. Han, Shin-Dug Kim, Yongchun Kim, Seh-Woong Jung, Kwang-Yup Lee
The cache memory system for CalmRISC32 embedded processor is described in this paper. A dual data cache system structure called a cooperative cache that takes advantage of design flexibilities of a dual cache structure is used as the cache memory system for CalmRISC32 to improve performance and reduce power consumption. The cooperative cache system is applied to both data cache and instruction cache. This paper describes the structure and operational model of the cache memory system for CalmRISC32. The implementation of the cache memory system for CalmRISC32 is also presented.
{"title":"The cache memory system for CalmRISC32","authors":"Kilwhan Lee, Jang-Soo Lee, G. Park, Jung-Hoon Lee, T. Han, Shin-Dug Kim, Yongchun Kim, Seh-Woong Jung, Kwang-Yup Lee","doi":"10.1109/APASIC.2000.896973","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896973","url":null,"abstract":"The cache memory system for CalmRISC32 embedded processor is described in this paper. A dual data cache system structure called a cooperative cache that takes advantage of design flexibilities of a dual cache structure is used as the cache memory system for CalmRISC32 to improve performance and reduce power consumption. The cooperative cache system is applied to both data cache and instruction cache. This paper describes the structure and operational model of the cache memory system for CalmRISC32. The implementation of the cache memory system for CalmRISC32 is also presented.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134310716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896916
Chorng-Sii Hwang, Wang-Chih Chung, Chih-Yong Wang, H. Tsao, Shen-Iuan Liu
A 2 V clock synchronizer chip using digital delay-locked loop is presented. It is targeted to provide synchronous clock distribution in high-speed digital systems. A simple structure with a counter-based delay line is used for compensating the skew caused by process, voltage, temperature and length. A stability criterion is also obtained. Experimental results have demonstrated its advantages like good stability, wide tuning range and low power consumption.
{"title":"A 2 V clock synchronizer using digital delay-locked loop","authors":"Chorng-Sii Hwang, Wang-Chih Chung, Chih-Yong Wang, H. Tsao, Shen-Iuan Liu","doi":"10.1109/APASIC.2000.896916","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896916","url":null,"abstract":"A 2 V clock synchronizer chip using digital delay-locked loop is presented. It is targeted to provide synchronous clock distribution in high-speed digital systems. A simple structure with a counter-based delay line is used for compensating the skew caused by process, voltage, temperature and length. A stability criterion is also obtained. Experimental results have demonstrated its advantages like good stability, wide tuning range and low power consumption.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132763695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896947
Hee-Chul Kim, Jong-Suk Chae, Hwa-Hyun Cho, Byong-Heon Kwon, Myung-Ryul Choi
In this paper, we propose a digital image interpolation method that improves the reconstruction of the edge component by selectively transposing the sub windows of the pseudomedian filter that shows relatively better performance than others. In order to compare the picture quality of the proposed method with that of the conventional methods, computer simulation has been executed by checking the PSNR, which is better than the others from the point of view of the edge and local characteristics of the image. When we judge the images with our eyes, the simulation results showed that the proposed method is better than the others from the point of view of the edge and local characteristics of the image.
{"title":"An interpolation algorithm by using the adaptive pseudomedian filter","authors":"Hee-Chul Kim, Jong-Suk Chae, Hwa-Hyun Cho, Byong-Heon Kwon, Myung-Ryul Choi","doi":"10.1109/APASIC.2000.896947","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896947","url":null,"abstract":"In this paper, we propose a digital image interpolation method that improves the reconstruction of the edge component by selectively transposing the sub windows of the pseudomedian filter that shows relatively better performance than others. In order to compare the picture quality of the proposed method with that of the conventional methods, computer simulation has been executed by checking the PSNR, which is better than the others from the point of view of the edge and local characteristics of the image. When we judge the images with our eyes, the simulation results showed that the proposed method is better than the others from the point of view of the edge and local characteristics of the image.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124795799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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