Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896941
Ming-Der Shieh, Chien-Hsing Wu, M. Sheu, Jia-Lin Sheu, Che-Han Wu
This paper presents an efficient VLSI implementation of the modular exponentiation, commonly used in RSA cryptography, based on the asynchronous behavior of the modular multiplication. The basic idea is to partition the operand (multiplier) into several equal-sized segments and then to perform the multiplication and residue calculation of each segment in a micropipelining fashion. Experimental results show that on the average, more than 20% operations can be saved by taking into account the asynchronous behavior of the modular multiplication. The resulting implementation has the characteristics of modular design, simple control, expandable structure, and the critical path is independent of the size of the modulus.
{"title":"Asynchronous implementation of modular exponentiation for RSA cryptography","authors":"Ming-Der Shieh, Chien-Hsing Wu, M. Sheu, Jia-Lin Sheu, Che-Han Wu","doi":"10.1109/APASIC.2000.896941","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896941","url":null,"abstract":"This paper presents an efficient VLSI implementation of the modular exponentiation, commonly used in RSA cryptography, based on the asynchronous behavior of the modular multiplication. The basic idea is to partition the operand (multiplier) into several equal-sized segments and then to perform the multiplication and residue calculation of each segment in a micropipelining fashion. Experimental results show that on the average, more than 20% operations can be saved by taking into account the asynchronous behavior of the modular multiplication. The resulting implementation has the characteristics of modular design, simple control, expandable structure, and the critical path is independent of the size of the modulus.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127936935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/APASIC.2000.896913
Chan-Hong Park, Ook Kim, Beomsup Kim
A 1.8 GHz phase-locked loop (PLL) with a self-calibration circuit implemented in 0.35 /spl mu/m CMOS process is presented. The calibration circuit continuously adjusts the delay mismatches among the delay cells in a ring-type voltage controlled oscillator (VCO) and automatically cancels the phase offsets in the multi-phase clock signals generated from the VCO. An edge-combining fractional-N frequency synthesizer with the self-calibrated PLL has been implemented and successfully eliminates -13 dBc fractional spur due to the delay mismatches in the VCO.
{"title":"A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching","authors":"Chan-Hong Park, Ook Kim, Beomsup Kim","doi":"10.1109/APASIC.2000.896913","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896913","url":null,"abstract":"A 1.8 GHz phase-locked loop (PLL) with a self-calibration circuit implemented in 0.35 /spl mu/m CMOS process is presented. The calibration circuit continuously adjusts the delay mismatches among the delay cells in a ring-type voltage controlled oscillator (VCO) and automatically cancels the phase offsets in the multi-phase clock signals generated from the VCO. An edge-combining fractional-N frequency synthesizer with the self-calibrated PLL has been implemented and successfully eliminates -13 dBc fractional spur due to the delay mismatches in the VCO.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127028318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/APASIC.2000.896966
Hong-Sik Kim, Il Seok Seo, Sungho Kang, G. Han
This paper describes the test strategy and the DFT (Design for Testability) methodology of CalmRISC32. CalmRISC32 is a 32 bit microcontrol unit, which consists of a 32 bit IU core, an FPU and a Cache Unit. The embedded memory arrays are tested by memory BIST (Built-in Self Test) and the logic blocks are tested by functional test methodology at the instruction level. To increase the test efficiency, a new scan chain methodology using a module called a TSU (Test Scan Unit) is developed.
{"title":"Testability strategy and DFT methodology of CalmRISC32","authors":"Hong-Sik Kim, Il Seok Seo, Sungho Kang, G. Han","doi":"10.1109/APASIC.2000.896966","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896966","url":null,"abstract":"This paper describes the test strategy and the DFT (Design for Testability) methodology of CalmRISC32. CalmRISC32 is a 32 bit microcontrol unit, which consists of a 32 bit IU core, an FPU and a Cache Unit. The embedded memory arrays are tested by memory BIST (Built-in Self Test) and the logic blocks are tested by functional test methodology at the instruction level. To increase the test efficiency, a new scan chain methodology using a module called a TSU (Test Scan Unit) is developed.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114553785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/APASIC.2000.896959
Keun-Ok Seo, Sancho Park
This paper addresses the Avant! silicon proven single pass design methodology for the recent very deep submicron (VDSM) era. Avant!'s single pass process is a predictable and controllable design process with closure in mind, not only for timing but also for signal/power integrity. By applying the right technology to the root cause of a design problem, this process can generate an optimal result in the shortest time.
{"title":"Proven single pass design methodology for high reliable VDSM","authors":"Keun-Ok Seo, Sancho Park","doi":"10.1109/APASIC.2000.896959","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896959","url":null,"abstract":"This paper addresses the Avant! silicon proven single pass design methodology for the recent very deep submicron (VDSM) era. Avant!'s single pass process is a predictable and controllable design process with closure in mind, not only for timing but also for signal/power integrity. By applying the right technology to the root cause of a design problem, this process can generate an optimal result in the shortest time.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126262870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/APASIC.2000.896987
H. Jeon, Sang-Yoon Lee, Dae-Keun Han
This paper described the new design technology for implementation of noise-free microcontroller unit (MCU), called Nfree/sup TM/ technology that is the solution proposed by Hyundai Electronics Co. Ltd. Preventing an erroneous operation due to noise is one of the basic requirements of many systems and is more seriously required by the MCU that controls the system. Also the power noise is one of the most serious noise sources that causes the MCU to malfunction. Therefore, we proposed the novel power noise preventing circuit scheme, called Nfree/sup TM/ technology. If the power falls below the voltage level of power failure, the MCU with Nfree/sup TM/ technology can be reset, frozen or stopped to preserve the system from the malfunction due to the power noise. In an MCU with Nfree/sup TM/ technology, the voltage level of power failure and the operating mode that resets, freezes or stops the MCU can be selected by software according to the applications.
{"title":"Design of a noise-free microcontroller","authors":"H. Jeon, Sang-Yoon Lee, Dae-Keun Han","doi":"10.1109/APASIC.2000.896987","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896987","url":null,"abstract":"This paper described the new design technology for implementation of noise-free microcontroller unit (MCU), called Nfree/sup TM/ technology that is the solution proposed by Hyundai Electronics Co. Ltd. Preventing an erroneous operation due to noise is one of the basic requirements of many systems and is more seriously required by the MCU that controls the system. Also the power noise is one of the most serious noise sources that causes the MCU to malfunction. Therefore, we proposed the novel power noise preventing circuit scheme, called Nfree/sup TM/ technology. If the power falls below the voltage level of power failure, the MCU with Nfree/sup TM/ technology can be reset, frozen or stopped to preserve the system from the malfunction due to the power noise. In an MCU with Nfree/sup TM/ technology, the voltage level of power failure and the operating mode that resets, freezes or stops the MCU can be selected by software according to the applications.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115678784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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