Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896910
Hwang-Cherng Chow, Chen-Yi Huang
A high and low speed output buffer with controlled slew rate is proposed for Universal Serial Bus (USB) applications. This novel output buffer design is low cost due to its easy realization in a digital CMOS process. The disclosed output buffer has been integrated in a complete USB transceiver circuit. Based on measured silicon data, satisfactory functions of the whole USB application IC have been obtained.
{"title":"Novel output buffer design for Universal Serial Bus applications","authors":"Hwang-Cherng Chow, Chen-Yi Huang","doi":"10.1109/APASIC.2000.896910","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896910","url":null,"abstract":"A high and low speed output buffer with controlled slew rate is proposed for Universal Serial Bus (USB) applications. This novel output buffer design is low cost due to its easy realization in a digital CMOS process. The disclosed output buffer has been integrated in a complete USB transceiver circuit. Based on measured silicon data, satisfactory functions of the whole USB application IC have been obtained.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126594416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896969
H. Rahaman, D. Das, B. B. Bhattacharya
This paper presents a BIST design suitable for detecting multiple stuck-open faults in two-level CMOS single complex cells. The test pattern generator (TPG) generates a sequence of length 2n.2/sup n/ that includes all n.2/sup n/ single-input-change (SIC) ordered test pairs for an n-input circuit under test (CUT). The signature analyzer (SA) counts the number of alternate transitions at the output. Design of the corresponding TPG and SA is straightforward.
{"title":"Transition count based BIST for detecting multiple stuck-open faults in CMOS circuits","authors":"H. Rahaman, D. Das, B. B. Bhattacharya","doi":"10.1109/APASIC.2000.896969","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896969","url":null,"abstract":"This paper presents a BIST design suitable for detecting multiple stuck-open faults in two-level CMOS single complex cells. The test pattern generator (TPG) generates a sequence of length 2n.2/sup n/ that includes all n.2/sup n/ single-input-change (SIC) ordered test pairs for an n-input circuit under test (CUT). The signature analyzer (SA) counts the number of alternate transitions at the output. Design of the corresponding TPG and SA is straightforward.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130382911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896926
Hwa-Hyun Cho, C. Choi, Byong-Heon Kwon, Myung-Ryul Choi
In this paper, we propose a contrast control for image improvement of multi-gray scale image. The proposed method does not require filed and frame memory for computed data. In addition, we propose that a contrast control can improve image regardless of input gray level. The proposed method can be easily applied to the FPD for real-time processing because of its lower hardware complexity compared to conventional methods. Also it can flexibly control the contrast of input gray level by varying the weight values that control the contrast range. The function of the proposed method has been verified using Synopsys VHDL and computer simulation. In addition, its results show that the proposed method can effect image improvement.
{"title":"A design of contrast controller for image improvement of multi-gray scale image","authors":"Hwa-Hyun Cho, C. Choi, Byong-Heon Kwon, Myung-Ryul Choi","doi":"10.1109/APASIC.2000.896926","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896926","url":null,"abstract":"In this paper, we propose a contrast control for image improvement of multi-gray scale image. The proposed method does not require filed and frame memory for computed data. In addition, we propose that a contrast control can improve image regardless of input gray level. The proposed method can be easily applied to the FPD for real-time processing because of its lower hardware complexity compared to conventional methods. Also it can flexibly control the contrast of input gray level by varying the weight values that control the contrast range. The function of the proposed method has been verified using Synopsys VHDL and computer simulation. In addition, its results show that the proposed method can effect image improvement.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131234650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896896
Seung-Chul Lee, Dong-soo Park, Jung-Hee Song, Myung-Whan Choi, Seung-Hoon Lee
This paper describes a switched-capacitor type DC-DC up converter with high efficiency and low-ripple output. Identical charge pumps operating sequentially in the proposed DC-DC converter reduce the magnitude of output voltage ripples to 20% of the conventional converters. A new charge pump adopting PMOS switches near the output stage improves the power efficiency of the DC-DC converter by 10%. The proposed DC-DC converter is applied, as a test vehicle, to a phase-locked loop circuit which is sensitive to power supply noise. All circuits are simulated and fabricated in a 0.65-/spl mu/m CMOS process.
{"title":"A low-ripple switched-capacitor DC-DC up converter for low-voltage applications","authors":"Seung-Chul Lee, Dong-soo Park, Jung-Hee Song, Myung-Whan Choi, Seung-Hoon Lee","doi":"10.1109/APASIC.2000.896896","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896896","url":null,"abstract":"This paper describes a switched-capacitor type DC-DC up converter with high efficiency and low-ripple output. Identical charge pumps operating sequentially in the proposed DC-DC converter reduce the magnitude of output voltage ripples to 20% of the conventional converters. A new charge pump adopting PMOS switches near the output stage improves the power efficiency of the DC-DC converter by 10%. The proposed DC-DC converter is applied, as a test vehicle, to a phase-locked loop circuit which is sensitive to power supply noise. All circuits are simulated and fabricated in a 0.65-/spl mu/m CMOS process.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134620046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896925
Kwangho Yoon
This paper presents hybrid-level charge recycling scheme which can be helpful in implementing low power LCD column drivers. The proposed scheme eliminates the necessity of polarity reversing circuit of the conventional method, simplifying the control. Another technique which merges two external capacitors into one is also described. This makes the multi-level recycling operation in column driving IC more practical.
{"title":"A hybrid-level multi-phase charge-recycler with reduced number of external capacitors for low-power LCD column drivers","authors":"Kwangho Yoon","doi":"10.1109/APASIC.2000.896925","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896925","url":null,"abstract":"This paper presents hybrid-level charge recycling scheme which can be helpful in implementing low power LCD column drivers. The proposed scheme eliminates the necessity of polarity reversing circuit of the conventional method, simplifying the control. Another technique which merges two external capacitors into one is also described. This makes the multi-level recycling operation in column driving IC more practical.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"92 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114021810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896970
Ing-Jer Huang, Chung-Fu Kao
This paper explores architectural alternatives in the integration of embedded in-circuit emulation into a SoC (System-on-Chip) chip with multiple microprocessor (microcontroller) cores. The alternatives include distributed, centralized and hierarchical styles. Advantages and disadvantages of these alternatives are analyzed.
{"title":"Exploration of multiple ICEs for embedded microprocessor cores in an SoC chip","authors":"Ing-Jer Huang, Chung-Fu Kao","doi":"10.1109/APASIC.2000.896970","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896970","url":null,"abstract":"This paper explores architectural alternatives in the integration of embedded in-circuit emulation into a SoC (System-on-Chip) chip with multiple microprocessor (microcontroller) cores. The alternatives include distributed, centralized and hierarchical styles. Advantages and disadvantages of these alternatives are analyzed.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132984186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896944
Jin Park, Seung-Chul Lee, Jin-Sik Yoon, Seunghoon Lee
This paper describes a 10 b 100 MS/s CMOS digital-to-analog converter (DAC) for cable modem applications. Differential switches with the proposed deglitching circuit and the cascode current sources, separated from the unit decoded current cell matrix improve the dynamic performance. The proposed and conventional prototype DAC's are fabricated in a 0.35 /spl mu/m CMOS process. The measured differential and integral nonlinearities of the proposed DAC shows /spl plusmn/0.17 LSB and /spl plusmn/0.43 LSB at a 10b level, respectively. At 100 MS/s, the spurious-free dynamic range is 66 dB for a 100 kHz input signal and 52 dB for a 10 MHz input signal.
{"title":"A 3 V 10 b 100 MS/s digital-to-analog converter for cable modem applications","authors":"Jin Park, Seung-Chul Lee, Jin-Sik Yoon, Seunghoon Lee","doi":"10.1109/APASIC.2000.896944","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896944","url":null,"abstract":"This paper describes a 10 b 100 MS/s CMOS digital-to-analog converter (DAC) for cable modem applications. Differential switches with the proposed deglitching circuit and the cascode current sources, separated from the unit decoded current cell matrix improve the dynamic performance. The proposed and conventional prototype DAC's are fabricated in a 0.35 /spl mu/m CMOS process. The measured differential and integral nonlinearities of the proposed DAC shows /spl plusmn/0.17 LSB and /spl plusmn/0.43 LSB at a 10b level, respectively. At 100 MS/s, the spurious-free dynamic range is 66 dB for a 100 kHz input signal and 52 dB for a 10 MHz input signal.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123609846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896982
H. Kang, H. Kye, D. Kim, Je-Hoon Park, Soo-Nam Jang, Ji-Hwan Ryu, Jin-Yong Chung
A 256 Kb ITIC FeRAM with sol-gel SBT provides wide operation of supply voltages ranging from 2.7 V to 5.5 V without a word-line boost scheme, and is composed of a novel power-on/off protection circuit with synchronized operation method to /CE pulse during the unintentional power-on/off.
{"title":"Low voltage protection circuit for FeRAM macro","authors":"H. Kang, H. Kye, D. Kim, Je-Hoon Park, Soo-Nam Jang, Ji-Hwan Ryu, Jin-Yong Chung","doi":"10.1109/APASIC.2000.896982","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896982","url":null,"abstract":"A 256 Kb ITIC FeRAM with sol-gel SBT provides wide operation of supply voltages ranging from 2.7 V to 5.5 V without a word-line boost scheme, and is composed of a novel power-on/off protection circuit with synchronized operation method to /CE pulse during the unintentional power-on/off.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125198292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896935
Jin-Su Ko, Hyun-seok Kim, Bonkee Kim, Byeong-ha Park
By Volterra series analysis using only several device parameters (Cje,/spl beta/,/spl tau/, and rb), the high-frequency nonlinear behavior of cascode amplifiers is analyzed. To verify the validity of this simple analysis, theoretical analysis, simulation, and measurement of intermodulation behavior of cascode amplifier are compared. The results show that simple Volterra series analysis agrees with the simulation and measurement, varying with emitter degeneration inductor and bias current. This simple Volterra series analysis is suitable to estimate the nonlinear characteristics and gives an insight into the conceptual circuit analysis.
{"title":"High-frequency intermodulation analysis of cascode amplifier","authors":"Jin-Su Ko, Hyun-seok Kim, Bonkee Kim, Byeong-ha Park","doi":"10.1109/APASIC.2000.896935","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896935","url":null,"abstract":"By Volterra series analysis using only several device parameters (Cje,/spl beta/,/spl tau/, and rb), the high-frequency nonlinear behavior of cascode amplifiers is analyzed. To verify the validity of this simple analysis, theoretical analysis, simulation, and measurement of intermodulation behavior of cascode amplifier are compared. The results show that simple Volterra series analysis agrees with the simulation and measurement, varying with emitter degeneration inductor and bias current. This simple Volterra series analysis is suitable to estimate the nonlinear characteristics and gives an insight into the conceptual circuit analysis.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122634488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896957
H.-C. Oh, H.-G. Kim, H.-S. Jung, J.-W. Lee, B. Kim, J. Jung, B.-G. Min, J.-Y. Lim, H. Lee, Kyeonghwan Kwon
The ADC's EISC microprocessor family has been developed to address the need for reduction in the amount of memory access of today's embedded applications. In this paper, we introduce the microarchitecture of the AE32000 processor, a 32-bit member of the ADC's EISC family. Specifically, we discuss the pipelining scheme and LERI-instruction folding, and we present the performance of our current implementation. We also introduce a system implementation utilizing the AE32000 processor.
{"title":"AE32000: an embedded microprocessor core","authors":"H.-C. Oh, H.-G. Kim, H.-S. Jung, J.-W. Lee, B. Kim, J. Jung, B.-G. Min, J.-Y. Lim, H. Lee, Kyeonghwan Kwon","doi":"10.1109/APASIC.2000.896957","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896957","url":null,"abstract":"The ADC's EISC microprocessor family has been developed to address the need for reduction in the amount of memory access of today's embedded applications. In this paper, we introduce the microarchitecture of the AE32000 processor, a 32-bit member of the ADC's EISC family. Specifically, we discuss the pipelining scheme and LERI-instruction folding, and we present the performance of our current implementation. We also introduce a system implementation utilizing the AE32000 processor.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124142857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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