Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9962996
Ziyue Chen, Yihui Shi, Ao Hu, Jiarui Xu, Guoyi Yu, Chao Wang
This paper presents a novel fold-back current limiting protection circuit used in sub-threshold low dropout regulator (LDO) for wireless sensor applications. By sensing the output current and output voltage, then comparing the sampled results with VREF, the proposed protection circuit can control the gate voltage of the power transistor to limit the output current. The maximum output current and short current of the sub-threshold LDO can be limited to 330 mA and 90 mA, respectively, which can save up to 71.9% of power consumption in the case of an output short-circuit condition compared with traditional constant current limiting protection methods. In a 0.35-μm CMOS technology, the sub-threshold LDO can provide a 3.3 V output voltage stably under the 5 V input voltage when the load current changes from 1 μA to 200 mA, and the load regulation rate is only 0.019 mV/mA.
{"title":"A Novel Fold-Back Current Limiting Protection used in Sub-threshold LDO for Wireless Sensor Applications","authors":"Ziyue Chen, Yihui Shi, Ao Hu, Jiarui Xu, Guoyi Yu, Chao Wang","doi":"10.1109/ICTA56932.2022.9962996","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962996","url":null,"abstract":"This paper presents a novel fold-back current limiting protection circuit used in sub-threshold low dropout regulator (LDO) for wireless sensor applications. By sensing the output current and output voltage, then comparing the sampled results with VREF, the proposed protection circuit can control the gate voltage of the power transistor to limit the output current. The maximum output current and short current of the sub-threshold LDO can be limited to 330 mA and 90 mA, respectively, which can save up to 71.9% of power consumption in the case of an output short-circuit condition compared with traditional constant current limiting protection methods. In a 0.35-μm CMOS technology, the sub-threshold LDO can provide a 3.3 V output voltage stably under the 5 V input voltage when the load current changes from 1 μA to 200 mA, and the load regulation rate is only 0.019 mV/mA.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129437770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963105
Yifan Yao, Chuqi Chen, Chenchang Zhan
In this paper, a 5.05MHz, 2.06μW/MHz, 22ppm/°C relaxation oscillator working as temperature varies from -40°C to 125°C and supply voltage varies from 1.1V to 2V is proposed and designed in a 180nm CMOS process. By using a single comparator control method and a reduced charging/discharging capacitance, the energy-per-cycle figure of merit reaches 2.06μW/MHz. With on-chip voltage and current reference and optimized comparator delay times, the output frequency has a temperature coefficient of only 22ppm/°C. The frequency changes for only 16% when supply voltage varies from 1.1V to 2V.
{"title":"A 2.06μW/MHz, 5.05-MHz, -40-125°C, 22ppm/°C Relaxation Oscillatior with Single Comparator Control","authors":"Yifan Yao, Chuqi Chen, Chenchang Zhan","doi":"10.1109/ICTA56932.2022.9963105","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963105","url":null,"abstract":"In this paper, a 5.05MHz, 2.06μW/MHz, 22ppm/°C relaxation oscillator working as temperature varies from -40°C to 125°C and supply voltage varies from 1.1V to 2V is proposed and designed in a 180nm CMOS process. By using a single comparator control method and a reduced charging/discharging capacitance, the energy-per-cycle figure of merit reaches 2.06μW/MHz. With on-chip voltage and current reference and optimized comparator delay times, the output frequency has a temperature coefficient of only 22ppm/°C. The frequency changes for only 16% when supply voltage varies from 1.1V to 2V.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130901287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963062
Yuqing Fang, Qingxuan Li, Tianyu Wang, Jialin Meng, Q. Sun, D. Zhang, Lin Chen
With the development of artificial intelligence technology, the usage of perception, storage and computing integrated devices for neuromorphic computing has become a research hotspot. We have successfully fabricated a photonmemristive device with optical sensing ability, which could simulate the synaptic behaviors in the human brain. The device could receive and respond to ultraviolet light, and realize synaptic functions, such as short-term plasticity, long-term potentiation and paired-pulse facilitation. In addition, it was able to be applied in the image identification field, the recognition rate could reach 92.2%. The device still had high stability and low operating current after light pulses excitation. The two-terminal photonic memristive unit is expected to be integrated into a 3D system and have broad application prospects in the field of artificial intelligence.
{"title":"Photon-Memristive Device for Neuromorphic Computing","authors":"Yuqing Fang, Qingxuan Li, Tianyu Wang, Jialin Meng, Q. Sun, D. Zhang, Lin Chen","doi":"10.1109/ICTA56932.2022.9963062","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963062","url":null,"abstract":"With the development of artificial intelligence technology, the usage of perception, storage and computing integrated devices for neuromorphic computing has become a research hotspot. We have successfully fabricated a photonmemristive device with optical sensing ability, which could simulate the synaptic behaviors in the human brain. The device could receive and respond to ultraviolet light, and realize synaptic functions, such as short-term plasticity, long-term potentiation and paired-pulse facilitation. In addition, it was able to be applied in the image identification field, the recognition rate could reach 92.2%. The device still had high stability and low operating current after light pulses excitation. The two-terminal photonic memristive unit is expected to be integrated into a 3D system and have broad application prospects in the field of artificial intelligence.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131309293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a peak-tunable PAM-4 linear equalizer for 200-Gb/s communication in 130-nm SiGe BiCMOS process. It consists of two stage continuous-time linear equalizers (CTLE) and an output driver. The feedforward and degeneration techniques are employed to realize multiple peaks at high, middle and low frequency points, respectively. Moreover, the equalizer can reach a maximum 20.6-dB compensation with a fixed peaking frequency at 51 GHz. The simulation results show that with an 18-dB lossy channel, the proposed equalizer provides a 53-GHz bandwidth and 200-Gb/s PAM-4 eye. It consumes 159-mW power under 2.8/3.3-V supply and achieves 0.80-pJ/bit power efficiency.
{"title":"A 200-Gb/s PAM-4 Feedforward Linear Equalizer with Multiple-Peaking and Fixed Maximum Peaking Frequencies in 130nm SiGe BiCMOS","authors":"Zhengzhe Jia, Taiyang Fan, Dongfan Xu, Dongshen Zhan, Linxuan Hu, Zhengyang Zhang, Yanchao Wang, Chun-Zhang Chen, Xuhui Liu, Hanming Wu, Quan Pan","doi":"10.1109/ICTA56932.2022.9963128","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963128","url":null,"abstract":"This paper presents a peak-tunable PAM-4 linear equalizer for 200-Gb/s communication in 130-nm SiGe BiCMOS process. It consists of two stage continuous-time linear equalizers (CTLE) and an output driver. The feedforward and degeneration techniques are employed to realize multiple peaks at high, middle and low frequency points, respectively. Moreover, the equalizer can reach a maximum 20.6-dB compensation with a fixed peaking frequency at 51 GHz. The simulation results show that with an 18-dB lossy channel, the proposed equalizer provides a 53-GHz bandwidth and 200-Gb/s PAM-4 eye. It consumes 159-mW power under 2.8/3.3-V supply and achieves 0.80-pJ/bit power efficiency.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129228578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963063
Haoyang Li, Yuyang Fu, Tian-Qing Wan, Yi Lu, Ling Yang, Yi Li
Fluctuations in Vth distribution can pose reliability problems for true random number generators (TRNGs). Here, we propose an explanation of the mechanism for voltage-to-time transformation scheme, which improve the reliability of TRNGs by fine-grained segmentation of time. Compared with conventional schemes, test scheme in this work can tolerate 50% cycle-to-cycle (C2C) and device-to-device (D2D) distribution shift and ensure the independence of random bits. This work provides a distinct and reliable evidence for tolerating frequent parameter shifts in voltage-to-time transformation scheme, which increase Vth robustness, reduce device requirements in practical use, and avoid redundant measurements and extra calibration in the test.
{"title":"Improve the Robustness of Diffusive Memristor based True Random Number Generator via Voltage-to-Time Transformation","authors":"Haoyang Li, Yuyang Fu, Tian-Qing Wan, Yi Lu, Ling Yang, Yi Li","doi":"10.1109/ICTA56932.2022.9963063","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963063","url":null,"abstract":"Fluctuations in Vth distribution can pose reliability problems for true random number generators (TRNGs). Here, we propose an explanation of the mechanism for voltage-to-time transformation scheme, which improve the reliability of TRNGs by fine-grained segmentation of time. Compared with conventional schemes, test scheme in this work can tolerate 50% cycle-to-cycle (C2C) and device-to-device (D2D) distribution shift and ensure the independence of random bits. This work provides a distinct and reliable evidence for tolerating frequent parameter shifts in voltage-to-time transformation scheme, which increase Vth robustness, reduce device requirements in practical use, and avoid redundant measurements and extra calibration in the test.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121183114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a low power, low phase noise, and small chip area transformer-based PMOS-only stacked-g», LC VCO in a 28-nm process. Both the top and bottom use PMOS cross-coupled pairs to provide negative resistances with suppressing the flicker noise. An interleaved transformer is used to get a higher coupling coefficient to achieve small chip area and high passive voltage gain. The VCO exhibits a wide turning range from 4.2 to 5.6 GHz, and low phase noise from -120 dBc/Hz to -113 dBc/Hz at 1MHz frequency offset, respectively. It consumes minimum 678 μ W and maximum 680 μ W from a 0.8V supply voltage which does not require internal LDO or DC-DC converter to reduce the supply voltage.
{"title":"A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS","authors":"Mingkang Zhang, Zihao Zhu, Yueduo Liu, Zehao Zhang, Rongxin Bao, Jiahui Lin, Haovu Zhuang, Jiaxin Liu, Xiong Zhou, Shiheng Yang, Qiang Li","doi":"10.1109/ICTA56932.2022.9962984","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962984","url":null,"abstract":"This paper presents a low power, low phase noise, and small chip area transformer-based PMOS-only stacked-g», LC VCO in a 28-nm process. Both the top and bottom use PMOS cross-coupled pairs to provide negative resistances with suppressing the flicker noise. An interleaved transformer is used to get a higher coupling coefficient to achieve small chip area and high passive voltage gain. The VCO exhibits a wide turning range from 4.2 to 5.6 GHz, and low phase noise from -120 dBc/Hz to -113 dBc/Hz at 1MHz frequency offset, respectively. It consumes minimum 678 μ W and maximum 680 μ W from a 0.8V supply voltage which does not require internal LDO or DC-DC converter to reduce the supply voltage.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114290310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design and simulations of a 224-Gb/s inverter-based transimpedance amplifier (TIA) designed in 28-nm CMOS process. The co-design of the photodiode and CMOS TIA efficiently optimize the optical receiver. The TIA achieves the bandwidth enhancement with the distributed peaking and interleaved active-feedback (IAFB) technology. The simulations result show that the proposed TIA has 39-dBΩ transimpedance gain and 70-GHz bandwidth (BW). Overall, it achieves a clear 224-Gb/s PAM4 eye diagram. The total power consumption is 20.7mW at 0.9-V supply voltage. And the input referred noise current is 8.2uArms.
{"title":"A 224-Gb/s Inverter-Based TIA with Interleaved Active-Feedback and Distributed Peaking in 28-nm CMOS for Silicon Photonic Receivers","authors":"Sikai Chen, Jintao Xue, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Liyuan Liu, Binhao Wang, Yingtao Li, Nan Qi","doi":"10.1109/ICTA56932.2022.9963090","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963090","url":null,"abstract":"This paper presents the design and simulations of a 224-Gb/s inverter-based transimpedance amplifier (TIA) designed in 28-nm CMOS process. The co-design of the photodiode and CMOS TIA efficiently optimize the optical receiver. The TIA achieves the bandwidth enhancement with the distributed peaking and interleaved active-feedback (IAFB) technology. The simulations result show that the proposed TIA has 39-dBΩ transimpedance gain and 70-GHz bandwidth (BW). Overall, it achieves a clear 224-Gb/s PAM4 eye diagram. The total power consumption is 20.7mW at 0.9-V supply voltage. And the input referred noise current is 8.2uArms.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122590505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963059
Shuyue Fang, Jinrui Hu, Haigang Feng, Xinpeng Xing, Han Wang, Lei Yang
Herein a digitally controlled ring oscillator (DCRO) using noise cancellation technology is presented for an all digital phase-locked loops (ADPLLs) system. The design introduced a noise insensitive current source combined with current digital-to-analog converter (DAC) to achieve high resolution with wide tuning range, and better supply noise immunization. Meanwhile, regulated cascode topology is utilized to ensure the equality of drain source voltage of current mirror arrays under various current injecting into DCRO alleviating the channel-length modulation effect. The proposed design was implemented in 40 nm CMOS process operating from 4 to 5GHz with 100kHz resolution. Simulation results show that the supply sensitivity of current source can averagely reach -151.5dB and DCRO achieves static and dynamic supply noise immunity of 0.021 %-fout/1% VDD and 0.011 %-fout/1 %-VDD respectively at 4.5GHz. The overall power dissipation is 0.84mW from a 1.2V supply.
{"title":"A 4 to 5GHz Digitally Controlled Ring Oscillator with 100kHz Resolution using Noise Cancellation Technology in 40nm CMOS","authors":"Shuyue Fang, Jinrui Hu, Haigang Feng, Xinpeng Xing, Han Wang, Lei Yang","doi":"10.1109/ICTA56932.2022.9963059","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963059","url":null,"abstract":"Herein a digitally controlled ring oscillator (DCRO) using noise cancellation technology is presented for an all digital phase-locked loops (ADPLLs) system. The design introduced a noise insensitive current source combined with current digital-to-analog converter (DAC) to achieve high resolution with wide tuning range, and better supply noise immunization. Meanwhile, regulated cascode topology is utilized to ensure the equality of drain source voltage of current mirror arrays under various current injecting into DCRO alleviating the channel-length modulation effect. The proposed design was implemented in 40 nm CMOS process operating from 4 to 5GHz with 100kHz resolution. Simulation results show that the supply sensitivity of current source can averagely reach -151.5dB and DCRO achieves static and dynamic supply noise immunity of 0.021 %-fout/1% VDD and 0.011 %-fout/1 %-VDD respectively at 4.5GHz. The overall power dissipation is 0.84mW from a 1.2V supply.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131592087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963025
Jinyu Xie, Xiaojun Bi
this paper presents a 110-GHz wideband direct-detection imaging unit integrating balanced power detector and log-periodic antenna in 0.25 μm GaAs pHEMT technology. The detector mainly consists of a 90° bridge, two identical transistors for detection, and a low-pass filter. Coplanar waveguides (CPW) are deployed to implement transmission lines in a compact size. In addition, an on-chip log-periodic antenna is co-designed to connect with the detector. Simulation results demonstrate that the peak responsivity of the detector is 8 kV/ W at 98 GHz with a 3 dB bandwidth from 85.9 GHz to 128.9 GHz and a low in-band noise equivalent power (NEP) of 0.87-1.5 pW/Hz1/2. The simulated $boldsymbol{S}_{11}$ is less than -7.6 dB at 75–140 GHz. The overall size of the chip is 2.7 × 1 mm2including pads.
{"title":"A Fully-integrated 110-GHz Wideband Direct-detection Imaging Unit MMIC Integrating Balanced Power Detector and Log-periodic Antenna","authors":"Jinyu Xie, Xiaojun Bi","doi":"10.1109/ICTA56932.2022.9963025","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963025","url":null,"abstract":"this paper presents a 110-GHz wideband direct-detection imaging unit integrating balanced power detector and log-periodic antenna in 0.25 μm GaAs pHEMT technology. The detector mainly consists of a 90° bridge, two identical transistors for detection, and a low-pass filter. Coplanar waveguides (CPW) are deployed to implement transmission lines in a compact size. In addition, an on-chip log-periodic antenna is co-designed to connect with the detector. Simulation results demonstrate that the peak responsivity of the detector is 8 kV/ W at 98 GHz with a 3 dB bandwidth from 85.9 GHz to 128.9 GHz and a low in-band noise equivalent power (NEP) of 0.87-1.5 pW/Hz1/2. The simulated $boldsymbol{S}_{11}$ is less than -7.6 dB at 75–140 GHz. The overall size of the chip is 2.7 × 1 mm2including pads.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115137031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963030
Y. Xie, Xufeng Liao, Xincai Liu, Lianxi Liu
A DLL-based offset calibration loop (OCL) is proposed to eliminate the DC offset and low-frequency flicker noise of the two differential paths to optimize the input signal-to-noise ratio before signal demodulation. The loop technology that can effectively calibrate the offset reduces the false alarm rate of the wake-up receiver (WuRX), and improves the sensitivity and robustness. This design uses 65nm LP CMOS process for layout design and simulation verification. With a supply voltage of 0.4V, the DC offset voltage on the signal path is reduced from an initial 5mV to a calibrated 39µV, resulting in a total system power consumption of 7.4nW.
{"title":"A DLL-Based Offset Calibration Loop Technology for Wake-Up Receivers","authors":"Y. Xie, Xufeng Liao, Xincai Liu, Lianxi Liu","doi":"10.1109/ICTA56932.2022.9963030","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963030","url":null,"abstract":"A DLL-based offset calibration loop (OCL) is proposed to eliminate the DC offset and low-frequency flicker noise of the two differential paths to optimize the input signal-to-noise ratio before signal demodulation. The loop technology that can effectively calibrate the offset reduces the false alarm rate of the wake-up receiver (WuRX), and improves the sensitivity and robustness. This design uses 65nm LP CMOS process for layout design and simulation verification. With a supply voltage of 0.4V, the DC offset voltage on the signal path is reduced from an initial 5mV to a calibrated 39µV, resulting in a total system power consumption of 7.4nW.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133093324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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