Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963117
Jiahao Hu, Zhongxian Huang, B. Duan, Qing Li, Ziqi Song, Dian He
In this paper, a Multiplying Delay-Locked Loop (MDLL) for high-precision Time to Digital Converter(TDC) is proposed, which has low jitter and high delay linearity. In order to reduce the phase noise, an internally compensated charge pump(CP) is used to achieve better current matching between charging and discharging. The improved reverse differential delay cell structure is used to improve the resolution of multi-phase clock. An MDLL with an output frequency of 80-240MHz and an area of 0.08mm2 is realized by using 0.18um CMOS process. The test results show that the total power consumption under 1.8V power supply is 11.52mW@240MHz, RMS jitter is 10ps@240MHz.
{"title":"A Multiplying Delay-Locked Loop design with low jitter and high linearity","authors":"Jiahao Hu, Zhongxian Huang, B. Duan, Qing Li, Ziqi Song, Dian He","doi":"10.1109/ICTA56932.2022.9963117","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963117","url":null,"abstract":"In this paper, a Multiplying Delay-Locked Loop (MDLL) for high-precision Time to Digital Converter(TDC) is proposed, which has low jitter and high delay linearity. In order to reduce the phase noise, an internally compensated charge pump(CP) is used to achieve better current matching between charging and discharging. The improved reverse differential delay cell structure is used to improve the resolution of multi-phase clock. An MDLL with an output frequency of 80-240MHz and an area of 0.08mm2 is realized by using 0.18um CMOS process. The test results show that the total power consumption under 1.8V power supply is 11.52mW@240MHz, RMS jitter is 10ps@240MHz.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127868948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963014
Jiacong Ke, Guangyin Feng, Yanjie Wang
This paper presents a compact low-noise amplifier (LNA) design for 60 GHz phased-array applications. Utilizing single transformer-based 4th-order resonators for input and inter-stage matching, a compact core area of only 0.08mm2 is achieved. A unit transistor-cell layout design technique for millimeter-wave (mm-Wave) circuit design is adopted to reduce the uncertain high-frequency coupling effects, leading a peak gain of 22.7dB. A 4.4-dB noise figure (NF) and a 3-dB bandwidth from 54 to 63 GHz are achieved based on the post layout simulation results, with a total power consumption of 29.9 mW.
{"title":"A Compact 60 GHz LNA with 22.7-dB Gain and 4.4-dB NF in 40nm CMOS","authors":"Jiacong Ke, Guangyin Feng, Yanjie Wang","doi":"10.1109/ICTA56932.2022.9963014","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963014","url":null,"abstract":"This paper presents a compact low-noise amplifier (LNA) design for 60 GHz phased-array applications. Utilizing single transformer-based 4th-order resonators for input and inter-stage matching, a compact core area of only 0.08mm2 is achieved. A unit transistor-cell layout design technique for millimeter-wave (mm-Wave) circuit design is adopted to reduce the uncertain high-frequency coupling effects, leading a peak gain of 22.7dB. A 4.4-dB noise figure (NF) and a 3-dB bandwidth from 54 to 63 GHz are achieved based on the post layout simulation results, with a total power consumption of 29.9 mW.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126990268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963098
Haitao Ge, Weiwei Shan, Yicheng Lu, Jun Yang
Previous on-chip training accelerators improved training efficiency but seldomly considered inference efficiency. We propose to convert back propagation to be compatible with inference, use interleaved memory allocation to reduce external memory access and zero-skipping loss propagation. Working at 40MHz, 0.48V core voltage, our 28nm one-core OCT chip has peak training efficiency of 4.69TOPS/W and the best inference energy of 2.34 µJ/inf/ image, 9.1× better than SoTA work.
{"title":"A 28nm, 4.69TOPS/W Training, 2.34µJ/lmage Inference, on-chip Training Accelerator with Inference-compatible Back Propagation","authors":"Haitao Ge, Weiwei Shan, Yicheng Lu, Jun Yang","doi":"10.1109/ICTA56932.2022.9963098","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963098","url":null,"abstract":"Previous on-chip training accelerators improved training efficiency but seldomly considered inference efficiency. We propose to convert back propagation to be compatible with inference, use interleaved memory allocation to reduce external memory access and zero-skipping loss propagation. Working at 40MHz, 0.48V core voltage, our 28nm one-core OCT chip has peak training efficiency of 4.69TOPS/W and the best inference energy of 2.34 µJ/inf/ image, 9.1× better than SoTA work.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128070723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963125
Jinrui Hu, Shuyue Fang, Haigang Feng, Xinpeng Xing, Han Wang, Lei Yang
A 2.4GHz LC-DCO with low frequency drift is presented to support frequency synthesizer under narrow band system like BLE. In the LC-DCO, a comprehensive temperature compensation scheme, which includes a Proportional To Absolute Temperature (PTAT) current bias and the varactor arrays varying linearly with voltage, is proposed to reduces the frequency drift of LC-DCO as a result of temperature fluctuations. By applying the circuit, frequency drift is reduced from 31MHz (without compensation) to 6MHz within the temperature from -40°C to 120 °C. And the results show that no extra in-band noise is added to LC tank. It consumes 860uW from a 0.9V supply in 40nm CMOS process technology.
{"title":"A Low Frequency Drift LC-DCO with Wide Temperature Range","authors":"Jinrui Hu, Shuyue Fang, Haigang Feng, Xinpeng Xing, Han Wang, Lei Yang","doi":"10.1109/ICTA56932.2022.9963125","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963125","url":null,"abstract":"A 2.4GHz LC-DCO with low frequency drift is presented to support frequency synthesizer under narrow band system like BLE. In the LC-DCO, a comprehensive temperature compensation scheme, which includes a Proportional To Absolute Temperature (PTAT) current bias and the varactor arrays varying linearly with voltage, is proposed to reduces the frequency drift of LC-DCO as a result of temperature fluctuations. By applying the circuit, frequency drift is reduced from 31MHz (without compensation) to 6MHz within the temperature from -40°C to 120 °C. And the results show that no extra in-band noise is added to LC tank. It consumes 860uW from a 0.9V supply in 40nm CMOS process technology.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126709302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963108
Yujie Liu, Zhilong Xiao, Shiquan Zhu, Huanpeng Wanq, Shuman Mao, Qingzhi Wu, R. Xu, B. Yan, Yuehang Xu
A Ku-band high power amplifier (HPA) is designed based on the 0.15µm GaN HEMT process. To improve the power added efficiency and gain, a high gate-width drive ratio of 1:6:38.4 is selected for a three-stage topology. Multi-order Chebyshev impedance transformers are used for realizing this high impedance transformation ratio match networks. Meanwhile, a compact 8-way power combining network with low insertion loss is adopted to improve the output power and power added efficiency. The measured results under continuous wave (CW) show that the small signal gain exceeds 30 dB over 13–17 GHz, and the input return loss (IRL) is better than -11dB. The output power is between 42–44 dBm and the power-added efficiency (PAE) is more than 30%. The chip size is 2.6 mm×4.3mm.
设计了一种基于0.15µm GaN HEMT工艺的ku波段高功率放大器。为了提高功率附加效率和增益，对于三级拓扑结构，选择了1:6:38.4的高栅极宽驱动比。采用多阶切比雪夫阻抗变压器实现高阻抗变换比匹配网络。同时，采用紧凑的低插入损耗8路并网，提高了输出功率和功率附加效率。连续波(CW)下的测量结果表明，在13-17 GHz范围内，小信号增益超过30 dB，输入回波损耗(IRL)优于-11dB。输出功率在42dbm ~ 44dbm之间，PAE (power-added efficiency)大于30%。芯片尺寸为2.6 mm×4.3mm。
{"title":"A Broadband 20W GaN High Power Amplifier for Ku-band satellite communication","authors":"Yujie Liu, Zhilong Xiao, Shiquan Zhu, Huanpeng Wanq, Shuman Mao, Qingzhi Wu, R. Xu, B. Yan, Yuehang Xu","doi":"10.1109/ICTA56932.2022.9963108","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963108","url":null,"abstract":"A Ku-band high power amplifier (HPA) is designed based on the 0.15µm GaN HEMT process. To improve the power added efficiency and gain, a high gate-width drive ratio of 1:6:38.4 is selected for a three-stage topology. Multi-order Chebyshev impedance transformers are used for realizing this high impedance transformation ratio match networks. Meanwhile, a compact 8-way power combining network with low insertion loss is adopted to improve the output power and power added efficiency. The measured results under continuous wave (CW) show that the small signal gain exceeds 30 dB over 13–17 GHz, and the input return loss (IRL) is better than -11dB. The output power is between 42–44 dBm and the power-added efficiency (PAE) is more than 30%. The chip size is 2.6 mm×4.3mm.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131472667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963111
Peng Chen, Yucheng Yu, Chao Yu
this paper investigates wideband behavioral modeling of Gallium Nitride (GaN) power amplifiers (PAs) using long short-term memory (LSTM) networks. Due to the memory mechanisms used in LSTM networks, they have the capability of accurately capturing both the short term and long term memory effects presenting in GaN PAs. The LSTM network-based model is verified experimentally on a GaN sequential power amplifier (SPA) under wideband multi-channel modulated signals, with showing good alignment between the modeled and measured data.
{"title":"Long Short-Term Memory Networks for Behavioral Modeling of A GaN Sequential Power Amplifier","authors":"Peng Chen, Yucheng Yu, Chao Yu","doi":"10.1109/ICTA56932.2022.9963111","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963111","url":null,"abstract":"this paper investigates wideband behavioral modeling of Gallium Nitride (GaN) power amplifiers (PAs) using long short-term memory (LSTM) networks. Due to the memory mechanisms used in LSTM networks, they have the capability of accurately capturing both the short term and long term memory effects presenting in GaN PAs. The LSTM network-based model is verified experimentally on a GaN sequential power amplifier (SPA) under wideband multi-channel modulated signals, with showing good alignment between the modeled and measured data.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130358806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9962986
Zhehan Wang, Dingxuan Kang, Jiayi Chen, Xiao Xu, Xu Jing, Li Tao
Two-dimensional transition metal dichalcogenide (TMDs) holds great promise for future wearable technologies. The large-scale synthesis of TMDs and the investigation of their molecular sensing properties are current research hotspots. Herein, we construct flexible PtTe2 molecular sensors directly on polyimide, followed by the exploration on ammonia sensing properties and stability under strain. The sensor shows an excellent ammonia response of 0.4% ppm-1surpassing most reported semimetal-based sensors. In-situ sensing testing reveals 500% enhancement in response after controlled strain engineering, which suggests the potential to expand limit of detection and linearity range.
{"title":"Strain-regulated flexible molecular sensors enabled by 2D PtTe2","authors":"Zhehan Wang, Dingxuan Kang, Jiayi Chen, Xiao Xu, Xu Jing, Li Tao","doi":"10.1109/ICTA56932.2022.9962986","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962986","url":null,"abstract":"Two-dimensional transition metal dichalcogenide (TMDs) holds great promise for future wearable technologies. The large-scale synthesis of TMDs and the investigation of their molecular sensing properties are current research hotspots. Herein, we construct flexible PtTe2 molecular sensors directly on polyimide, followed by the exploration on ammonia sensing properties and stability under strain. The sensor shows an excellent ammonia response of 0.4% ppm-1surpassing most reported semimetal-based sensors. In-situ sensing testing reveals 500% enhancement in response after controlled strain engineering, which suggests the potential to expand limit of detection and linearity range.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116616794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963064
Cona Shi, Sihao Chen, Haibina Wana, Zhenaaina Zhona, P. Li, Junxian He, Tengxiao Wang, Jianyi Yu, Min Tian
For edge intelligent applications, this work proposes a tiny neuromorphic hardware core embedding high-speed on-chip synaptic plasticity, by adopting the proposed Temporal-Integrate neuron model and a simplified supervised spike-driven synaptic plasticity rule for on-chip learning. The proposed hardware core was prototyped on a very-low-cost Zybo Zynq-7010 FPGA device, and attained comparably high classification accuracies on many datasets (e.g. 90.4% on MNIST), with a learning and inference speed as high as 11,268 and 11,749 f $r$ ame/s, respectively, while dissipating only 39 mW power under a 250 MHz clock frequency.
对于边缘智能应用，本工作提出了一个嵌入高速片上突触可塑性的微小神经形态硬件核心，采用所提出的时间集成神经元模型和简化的监督spike驱动的片上学习突触可塑性规则。所提出的硬件核心在极低成本的Zybo Zynq-7010 FPGA器件上进行了原型设计，并在许多数据集上获得了相当高的分类精度(例如在MNIST上的90.4%)，学习和推理速度分别高达11,268和11,749 f $r$ ame/s，而在250 MHz时钟频率下仅消耗39 mW功率。
{"title":"TEDOP: A Tiny Event-Driven Neural Network Hardware Core Enabling On-Chip Spike-Driven Synaptic Plasticity","authors":"Cona Shi, Sihao Chen, Haibina Wana, Zhenaaina Zhona, P. Li, Junxian He, Tengxiao Wang, Jianyi Yu, Min Tian","doi":"10.1109/ICTA56932.2022.9963064","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963064","url":null,"abstract":"For edge intelligent applications, this work proposes a tiny neuromorphic hardware core embedding high-speed on-chip synaptic plasticity, by adopting the proposed Temporal-Integrate neuron model and a simplified supervised spike-driven synaptic plasticity rule for on-chip learning. The proposed hardware core was prototyped on a very-low-cost Zybo Zynq-7010 FPGA device, and attained comparably high classification accuracies on many datasets (e.g. 90.4% on MNIST), with a learning and inference speed as high as 11,268 and 11,749 f $r$ ame/s, respectively, while dissipating only 39 mW power under a 250 MHz clock frequency.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132153725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963082
Wenbo Li, Qian Xie, Zheng Wang
In this paper, an analytical model for electrostatic doping effect in the charge-plasma-based TFET (CP-TFET) is proposed by solving Poisson's equation incorporating the mobile charge term. Closed forms of vertical potential and electrostatic doping concentration in CP-TFETs are developed. Meanwhile, the impacts of the electrode work functions and substrate thicknesses on them are analyzed. This predicted electrostatic doping concentration agrees well with the Sentaurus TCAD simulation results of the CP-TFET.
{"title":"An Analytical Model for doping effect in charge-plasma-based TFET","authors":"Wenbo Li, Qian Xie, Zheng Wang","doi":"10.1109/ICTA56932.2022.9963082","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963082","url":null,"abstract":"In this paper, an analytical model for electrostatic doping effect in the charge-plasma-based TFET (CP-TFET) is proposed by solving Poisson's equation incorporating the mobile charge term. Closed forms of vertical potential and electrostatic doping concentration in CP-TFETs are developed. Meanwhile, the impacts of the electrode work functions and substrate thicknesses on them are analyzed. This predicted electrostatic doping concentration agrees well with the Sentaurus TCAD simulation results of the CP-TFET.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116310569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963070
Tianqi Xu, Shumeng Li, Fukun Su, Xian Tang
This paper presents a computing-in-memory (CIM) SRAM macro utilizing current domain computing for multiply-and-accumulate (MAC) operations. A 32x64 8T bitcell array is used to store the weight data. This design adopts the modulated word line pulse-width method to convert 4-bit digital input data to analog domain. The MAC operation of weight and input data is accomplished through bitwise multiplication and the result is transformed to current which accumulates on the reading bit line (RBL). In order to improve the signal margin without sacrificing the readout precision, a hybrid integrate-and-fire (IAF)-SAR ADC is proposed to convert the computing result into digital domain. The presented design is implemented in a standard 65nm CMOS process and simulation results indicate the proposed 32x64 CIM macro achieves energy efficiency of 18.76 TOPS/W and peak throughput of 10.24 GOPS with 4-bit inputs and 4-bit weights.
{"title":"A Current Domain Computing-in-Memory SRAM Macro with Hybrid IAF-SAR ADC for Signal Margin Enhancement","authors":"Tianqi Xu, Shumeng Li, Fukun Su, Xian Tang","doi":"10.1109/ICTA56932.2022.9963070","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963070","url":null,"abstract":"This paper presents a computing-in-memory (CIM) SRAM macro utilizing current domain computing for multiply-and-accumulate (MAC) operations. A 32x64 8T bitcell array is used to store the weight data. This design adopts the modulated word line pulse-width method to convert 4-bit digital input data to analog domain. The MAC operation of weight and input data is accomplished through bitwise multiplication and the result is transformed to current which accumulates on the reading bit line (RBL). In order to improve the signal margin without sacrificing the readout precision, a hybrid integrate-and-fire (IAF)-SAR ADC is proposed to convert the computing result into digital domain. The presented design is implemented in a standard 65nm CMOS process and simulation results indicate the proposed 32x64 CIM macro achieves energy efficiency of 18.76 TOPS/W and peak throughput of 10.24 GOPS with 4-bit inputs and 4-bit weights.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128581818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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