Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963029
Zhuang Zhang, Hanyu Shi, Danzhu Lu, Peng Cao, Zhiliang Hong
An adaptive on-time (AOT) buck converter with constant switching frequency and fast transient response is presented. A frequency-locked loop (FLL) is used to achieve constant switching frequency. The on-time (TON) is adjusted by a TON extender to achieve fast transient response. The proposed AOT buck converter is implemented in 0.18µm CMOS process. The simulation results show that the switching frequency is fixed at IMHz under various load condition and the output voltage undershoot and settling time are only 50m V and 2.5µs, respectively during 4A load transient.
{"title":"An AOT Buck Converter with Adaptive TON Extender Achieving 2.5µs Settling Time in 4A Load Transient","authors":"Zhuang Zhang, Hanyu Shi, Danzhu Lu, Peng Cao, Zhiliang Hong","doi":"10.1109/ICTA56932.2022.9963029","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963029","url":null,"abstract":"An adaptive on-time (AOT) buck converter with constant switching frequency and fast transient response is presented. A frequency-locked loop (FLL) is used to achieve constant switching frequency. The on-time (TON) is adjusted by a TON extender to achieve fast transient response. The proposed AOT buck converter is implemented in 0.18µm CMOS process. The simulation results show that the switching frequency is fixed at IMHz under various load condition and the output voltage undershoot and settling time are only 50m V and 2.5µs, respectively during 4A load transient.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133005793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963085
G. Gugliandolo, X. Bao, Haoyun Yuan, Jinkai Li, Junchena Bao, G. Crupi, N. Donato
This paper is focused on a microwave sensor for the evaluation of the dielectric properties of binary liquid mixtures at RF/microwave frequencies. The sensor consists of a split ring resonator (SRR), built using the microstrip technology. Interdigitated electrodes are integrated into the ring as a sensing element for liquid detection. A proper extraction procedure has been proposed for the accurate evaluation of the resonant frequency of the developed prototype. The resonant extraction procedure is based on the analysis of the frequency-dependent behavior of the complex forward transmission coefficient (S21) that is accurately modeled locally around the resonance by using a fitting function. According to the tests carried out with water-isopropanol liquid mixtures at various volume fractions, the studied device is more sensitive than the more conventional SRR sensor.
{"title":"A Split-Ring Resonator with Interdigitated Electrodes Aimed at the Dielectric Characterization of Liquid Mixtures (Invited Paper)","authors":"G. Gugliandolo, X. Bao, Haoyun Yuan, Jinkai Li, Junchena Bao, G. Crupi, N. Donato","doi":"10.1109/ICTA56932.2022.9963085","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963085","url":null,"abstract":"This paper is focused on a microwave sensor for the evaluation of the dielectric properties of binary liquid mixtures at RF/microwave frequencies. The sensor consists of a split ring resonator (SRR), built using the microstrip technology. Interdigitated electrodes are integrated into the ring as a sensing element for liquid detection. A proper extraction procedure has been proposed for the accurate evaluation of the resonant frequency of the developed prototype. The resonant extraction procedure is based on the analysis of the frequency-dependent behavior of the complex forward transmission coefficient (S21) that is accurately modeled locally around the resonance by using a fitting function. According to the tests carried out with water-isopropanol liquid mixtures at various volume fractions, the studied device is more sensitive than the more conventional SRR sensor.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132777423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963069
Renwei Chen, Yifei Zhang, Chenchang Zhan
A relaxation oscillator(RO) composed of a voltage and current reference (VCR) and a digital current comparator is presented in this paper. By using two different types of resistors with opposite temperature coefficient (TC) in the VCR, this design successfully stabilizes the operation frequency from -20 to 100° C with a very simple structure. Designed in a standard 180nm CMOS process, the proposed RO consumes 120nW under a 0.8V supply and operates at 121kHz, with a TC as low as 36.2 ppm/°C.
{"title":"A 120nW, 121 kHz, -20~100°C CMOS Relaxation Oscillator with Digital Current Comparator and On-Chip Voltage and Current Reference","authors":"Renwei Chen, Yifei Zhang, Chenchang Zhan","doi":"10.1109/ICTA56932.2022.9963069","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963069","url":null,"abstract":"A relaxation oscillator(RO) composed of a voltage and current reference (VCR) and a digital current comparator is presented in this paper. By using two different types of resistors with opposite temperature coefficient (TC) in the VCR, this design successfully stabilizes the operation frequency from -20 to 100° C with a very simple structure. Designed in a standard 180nm CMOS process, the proposed RO consumes 120nW under a 0.8V supply and operates at 121kHz, with a TC as low as 36.2 ppm/°C.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122359308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963047
Ziyang Chen, Miaocheng Zhang, Zixuan Ding, Aoze Han, Xinavu Chen, Xinpeng Wang, Lei Wang, Haotong Zhang, Yi Tong
Ferroelectric memristors are in principle a promising candidate for realizing effective computing in memory, for their advantages of multi-bit storage, ultra-fast switching behavior, and low power consumption. Here, we successfully fabricated the Cu/BaFe12O19/Pt ferroelectric memristive device with multi-resistance state (2 bits), reliable reproducibility (>102), and desired on/off ratio (103). The conductive mechanism of the device is attributed to the variation of ferroelectric barrier, which is verified by first-principle calculations. In addition, based on the randomness of the SET voltage of the devices, we innovatively propose a schematic diagram of true random number generator (TRNG) circuit. This work may pave the way for next-generation ferroelectric memristors and further enable a broad range of multifunctional applications.
{"title":"BaFe12O19 based Ferroelectric Memristor for Applications of True Random Number Generator","authors":"Ziyang Chen, Miaocheng Zhang, Zixuan Ding, Aoze Han, Xinavu Chen, Xinpeng Wang, Lei Wang, Haotong Zhang, Yi Tong","doi":"10.1109/ICTA56932.2022.9963047","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963047","url":null,"abstract":"Ferroelectric memristors are in principle a promising candidate for realizing effective computing in memory, for their advantages of multi-bit storage, ultra-fast switching behavior, and low power consumption. Here, we successfully fabricated the Cu/BaFe12O19/Pt ferroelectric memristive device with multi-resistance state (2 bits), reliable reproducibility (>102), and desired on/off ratio (103). The conductive mechanism of the device is attributed to the variation of ferroelectric barrier, which is verified by first-principle calculations. In addition, based on the randomness of the SET voltage of the devices, we innovatively propose a schematic diagram of true random number generator (TRNG) circuit. This work may pave the way for next-generation ferroelectric memristors and further enable a broad range of multifunctional applications.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131794169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963136
Pengfei Wu, Z. Wang, Zhiming Pan, Weilun Wang
Neural Processing Unit (NPU) has become the state-of-the-art solution for accelerating artificial neural networks and is increasingly integrated on the System-on-Chip (SoC) of edge devices such as smartphones and cameras. However, adopting NPU in mission-critical systems, such as aerospace aircraft and autonomous driving demands high reliability, which is currently less explored on industrial NPUs. In this work, we target one of the critical reliability issues - permanent fault - for modern NPUs and provide an instruction-driven fault detection method named LIPFD-NPU. The approach executes dedicated network instructions in a self-testing fashion and generates fine-grained information on the potential fault's location, type and level of impact. An FPGA-based fault emulation framework is used to verify LIPFD-NPU. The results indicate that LIPFD-NPU effectively detects faults with tiny overheads of 0.2% in silicon area and 0.5% in power consumption.
{"title":"LIPFD-NPU: Low-overhead Instruction-driven Permanent Fault Detection for Neural Processing Unit","authors":"Pengfei Wu, Z. Wang, Zhiming Pan, Weilun Wang","doi":"10.1109/ICTA56932.2022.9963136","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963136","url":null,"abstract":"Neural Processing Unit (NPU) has become the state-of-the-art solution for accelerating artificial neural networks and is increasingly integrated on the System-on-Chip (SoC) of edge devices such as smartphones and cameras. However, adopting NPU in mission-critical systems, such as aerospace aircraft and autonomous driving demands high reliability, which is currently less explored on industrial NPUs. In this work, we target one of the critical reliability issues - permanent fault - for modern NPUs and provide an instruction-driven fault detection method named LIPFD-NPU. The approach executes dedicated network instructions in a self-testing fashion and generates fine-grained information on the potential fault's location, type and level of impact. An FPGA-based fault emulation framework is used to verify LIPFD-NPU. The results indicate that LIPFD-NPU effectively detects faults with tiny overheads of 0.2% in silicon area and 0.5% in power consumption.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127494056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963121
Xuan Zhang, Haige Wu, Renyuan Zhang, Zihang Xu, Hao Zhang, Bo Liu, Hao Cai
Speaker verification (SV) is not only a convenient biometric recognition technology but also an important method to ensure information security. Since SV systems are often deployed in mobile terminals, this places a higher demand on the trade-off between ensuring recognition accuracy and reducing system power consumption. Thus, this paper proposes an implementation of a speaker verification system based on a ternary weight network (TWN). First, we design a TWN structure for the SV system. Then a weight quantization scheme to reduce hardware storage overhead is adopted. After that, the hardware of the SV system is designed and simulated. The recognition accuracy of the proposed TWN is tested to be 83.3%@5dB, 87.9%@15dB, and 93.1%@clean, respectively. Using an industry of 22nm ULL process, the overall power consumption of the system is 16.3µW.
{"title":"A TWN Inspired Speaker Verification Processor with Hardware-friendly Weight Quantization","authors":"Xuan Zhang, Haige Wu, Renyuan Zhang, Zihang Xu, Hao Zhang, Bo Liu, Hao Cai","doi":"10.1109/ICTA56932.2022.9963121","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963121","url":null,"abstract":"Speaker verification (SV) is not only a convenient biometric recognition technology but also an important method to ensure information security. Since SV systems are often deployed in mobile terminals, this places a higher demand on the trade-off between ensuring recognition accuracy and reducing system power consumption. Thus, this paper proposes an implementation of a speaker verification system based on a ternary weight network (TWN). First, we design a TWN structure for the SV system. Then a weight quantization scheme to reduce hardware storage overhead is adopted. After that, the hardware of the SV system is designed and simulated. The recognition accuracy of the proposed TWN is tested to be 83.3%@5dB, 87.9%@15dB, and 93.1%@clean, respectively. Using an industry of 22nm ULL process, the overall power consumption of the system is 16.3µW.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127553169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963130
Yifan Hu, Tao Huang, Run Run, Li Yin, Guolin Li, Xiang Xie
In the fields of CNN, there exists many multiply applications with one fixed operand. In view of such characteristics, this paper proposes a preprocessing-based power-efficient approximate multiplier (PPBAM) design for CNN. In the proposed design, the fixed operand is preprocessed to avoid additional dynamic power consumption due to repeated processing. To reduce the number of the partial products, the first ‘1’ of both two operands are found and then the operands are truncated by a method named weak rounding. What's more, a sub multiplier array utilizing an approximate 4:2 compressor are proposed to calculate the truncation results with low power. The experimental results show that, with the same accuracy, on average, our design has a 30% improvement in power consumption compared with state-of-the-art approximate multiplier designs without additional latency and area.
{"title":"PPBAM:A Preprocessing-based Power-Efficient Approximate Multiplier Design for CNN","authors":"Yifan Hu, Tao Huang, Run Run, Li Yin, Guolin Li, Xiang Xie","doi":"10.1109/ICTA56932.2022.9963130","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963130","url":null,"abstract":"In the fields of CNN, there exists many multiply applications with one fixed operand. In view of such characteristics, this paper proposes a preprocessing-based power-efficient approximate multiplier (PPBAM) design for CNN. In the proposed design, the fixed operand is preprocessed to avoid additional dynamic power consumption due to repeated processing. To reduce the number of the partial products, the first ‘1’ of both two operands are found and then the operands are truncated by a method named weak rounding. What's more, a sub multiplier array utilizing an approximate 4:2 compressor are proposed to calculate the truncation results with low power. The experimental results show that, with the same accuracy, on average, our design has a 30% improvement in power consumption compared with state-of-the-art approximate multiplier designs without additional latency and area.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125371881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9962998
Lingyun Liu, Chenglong Liang, Zhuoqi Guo, Zhongming Xue, Li Geng
Low dropout (LDO) voltage regulators are essential for noise-sensitive circuit systems in cryogenic temperature environments. This paper characterized and modeled a full-scale BSIM4-based 180nm MOSFET at cryogenic temperature. Then, a high PSR low output noise cap-less LDO is implemented with the cascade and feed-forward current technology for cryogenic applications. At 77K, simulation results show that PSR is -98dB at 10kHz and -78dB at 100kHz, and the integrated noise is 0.82 µVrms among the frequency from 100Hz to 100kHz.
{"title":"A Cap-Less High PSR and Low Output Noise Low-Dropout Regulator for Cryogenic Applications","authors":"Lingyun Liu, Chenglong Liang, Zhuoqi Guo, Zhongming Xue, Li Geng","doi":"10.1109/ICTA56932.2022.9962998","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962998","url":null,"abstract":"Low dropout (LDO) voltage regulators are essential for noise-sensitive circuit systems in cryogenic temperature environments. This paper characterized and modeled a full-scale BSIM4-based 180nm MOSFET at cryogenic temperature. Then, a high PSR low output noise cap-less LDO is implemented with the cascade and feed-forward current technology for cryogenic applications. At 77K, simulation results show that PSR is -98dB at 10kHz and -78dB at 100kHz, and the integrated noise is 0.82 µVrms among the frequency from 100Hz to 100kHz.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124538195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963110
Xiaoyun Tian, Zhong-Jian Bian, Hao Cai
Spin-transfer-torque magnetic random access memory (STT-MRAM) shows great potential to replace mainstream working memories thanks to its high energy efficiency and endurance. As RAM-like applications require higher speed, it is preferred to use a robust current-type sense amplifier (SA) with complex operating timing, which limits their working speed. The timing generated by the inverter chain is greatly affected by the process, voltage, and temperature (PVT) variations. In this work, a clock trimming sensing scheme is proposed to increase sensing speed and solve PVT variation in current-type SA. Since the timing is generated through voltage difference sampling between differential inputs, this scheme can achieve stable and fast sensing over a wide temperature range. According to the simulation results, the proposed scheme can sense data within 8-ns (near LLC working speed) and save up to 45.6% of energy consumption compared to the traditional SAs.
{"title":"Towards Near LLC Speed STT-MRAM Sensing Using Reconfigurable Clock Trimming","authors":"Xiaoyun Tian, Zhong-Jian Bian, Hao Cai","doi":"10.1109/ICTA56932.2022.9963110","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963110","url":null,"abstract":"Spin-transfer-torque magnetic random access memory (STT-MRAM) shows great potential to replace mainstream working memories thanks to its high energy efficiency and endurance. As RAM-like applications require higher speed, it is preferred to use a robust current-type sense amplifier (SA) with complex operating timing, which limits their working speed. The timing generated by the inverter chain is greatly affected by the process, voltage, and temperature (PVT) variations. In this work, a clock trimming sensing scheme is proposed to increase sensing speed and solve PVT variation in current-type SA. Since the timing is generated through voltage difference sampling between differential inputs, this scheme can achieve stable and fast sensing over a wide temperature range. According to the simulation results, the proposed scheme can sense data within 8-ns (near LLC working speed) and save up to 45.6% of energy consumption compared to the traditional SAs.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128350106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9962967
Nianquan Ran, Jia Li, Shuaizhe Ma, Yuye Yang, Wanqing Zhao, Hao Li, Dan Li
With the determination of the 50Gb/s PON communication network standard, there is a large demand for 50Gb/s PON chips. In this paper, we design a 50Gb/s transimpedance amplifier (TIA) chip with very low power consumption, which greatly reduces the manufacturing cost by adopting the 40nm standard CMOS process. In the high gain mode, the transimpedance gain is 66.0dBΩ and the bandwidth is 30.4GHz. In the low gain mode, the transimpedance is 52.4dBΩ and the bandwidth is 34.1GHz. The input signal range can reach 2mA at most and the maximum differential output swing is 440mVpp. The receiver front-end circuit consumes 23.4mW, and the energy efficiency is 0.47pJ/bit.
{"title":"Optical Receiver Front-End for 50G PON in 40nm CMOS","authors":"Nianquan Ran, Jia Li, Shuaizhe Ma, Yuye Yang, Wanqing Zhao, Hao Li, Dan Li","doi":"10.1109/ICTA56932.2022.9962967","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962967","url":null,"abstract":"With the determination of the 50Gb/s PON communication network standard, there is a large demand for 50Gb/s PON chips. In this paper, we design a 50Gb/s transimpedance amplifier (TIA) chip with very low power consumption, which greatly reduces the manufacturing cost by adopting the 40nm standard CMOS process. In the high gain mode, the transimpedance gain is 66.0dBΩ and the bandwidth is 30.4GHz. In the low gain mode, the transimpedance is 52.4dBΩ and the bandwidth is 34.1GHz. The input signal range can reach 2mA at most and the maximum differential output swing is 440mVpp. The receiver front-end circuit consumes 23.4mW, and the energy efficiency is 0.47pJ/bit.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115231750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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