Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963033
Huafeng Ye, Huipeng Deng, Jian Wang, Mingyu Wang, Zhiyi Yu
3D Convolutional neural networks (3D CNNs) perform better in some scenarios, such as video understanding and 3D medical image diagnosis. With the increase in the dimension and size of the convolution kernel, CNN's computational complexity and implementation difficulty increase severely. Winograd transformation can significantly reduce the number of multiplications in convolution operations. However, large convolution filters will bring numerical instability. In this article, we presented a novel method called 3D nested Winograd algorithm to address the problem. Compared with the state-of-art OLA-Winograd algorithm, the proposed algorithm reduces the multiplications by 1.72 to 5.83× for computing 5 × 5 × 5 to 9 × 9 × 9 convolutions. Finally, we demonstrate the efficiency of 3D-NWA on the FPGA platform (Xilinx VCU118) and achieve highest DSP efficiency up to 4.67× compared with the state-of-art accelerators.
{"title":"3D-NWA: A Nested-Winograd Accelerator for 3D CNNs","authors":"Huafeng Ye, Huipeng Deng, Jian Wang, Mingyu Wang, Zhiyi Yu","doi":"10.1109/ICTA56932.2022.9963033","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963033","url":null,"abstract":"3D Convolutional neural networks (3D CNNs) perform better in some scenarios, such as video understanding and 3D medical image diagnosis. With the increase in the dimension and size of the convolution kernel, CNN's computational complexity and implementation difficulty increase severely. Winograd transformation can significantly reduce the number of multiplications in convolution operations. However, large convolution filters will bring numerical instability. In this article, we presented a novel method called 3D nested Winograd algorithm to address the problem. Compared with the state-of-art OLA-Winograd algorithm, the proposed algorithm reduces the multiplications by 1.72 to 5.83× for computing 5 × 5 × 5 to 9 × 9 × 9 convolutions. Finally, we demonstrate the efficiency of 3D-NWA on the FPGA platform (Xilinx VCU118) and achieve highest DSP efficiency up to 4.67× compared with the state-of-art accelerators.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117131038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963079
Pengfei Wang, Minhan Mi, Sirui An, Xiang Du, Xiao-hua Ma, Yue Hao
In this letter, we demonstrate an AlGaN/GaN HEMT fabricated by synthesizing recess and planar devices along the gate width and incorporating N2O plasma treatment to form an oxide layer at the gate electrode of the proposed HEMT. The transconductance curve of the fabricated device has a plateau region larger than 7 V, with a flattened response curve of fT/fmaxwith respect to the gate bias voltage. At the operating frequency of 30 GHz, the maximum power-added efficiency (PAE) is 41%, the value of the power density ($mathrm{P}_{mathrm{o}mathrm{u}mathrm{t}}$ is 5.3 W/mm, and the associated 1dB compression point $(mathrm{p}_{mathrm{l}mathrm{d}mathrm{B}^{)}}$ is 28 dBm. The device presented in this article has excellent potential for millimeter-wave applications where high linearity is essential.
{"title":"A Novel Concept of using Double Threshold Voltage Coupling to Improve the linearity of AlGaN/GaN HEMTs for millimeter-wave applications","authors":"Pengfei Wang, Minhan Mi, Sirui An, Xiang Du, Xiao-hua Ma, Yue Hao","doi":"10.1109/ICTA56932.2022.9963079","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963079","url":null,"abstract":"In this letter, we demonstrate an AlGaN/GaN HEMT fabricated by synthesizing recess and planar devices along the gate width and incorporating N2O plasma treatment to form an oxide layer at the gate electrode of the proposed HEMT. The transconductance curve of the fabricated device has a plateau region larger than 7 V, with a flattened response curve of fT/fmaxwith respect to the gate bias voltage. At the operating frequency of 30 GHz, the maximum power-added efficiency (PAE) is 41%, the value of the power density ($mathrm{P}_{mathrm{o}mathrm{u}mathrm{t}}$ is 5.3 W/mm, and the associated 1dB compression point $(mathrm{p}_{mathrm{l}mathrm{d}mathrm{B}^{)}}$ is 28 dBm. The device presented in this article has excellent potential for millimeter-wave applications where high linearity is essential.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126548017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the oxide fused and anti-fused behavior has been observed in a simple metal-oxide-metal device: Pt/HfO2/NiOx/Ni. The anti-fused state and fused state can be achieved by applying program voltage on the devices with or without current compliance, respectively. And the resistance window of the two states reaches about 109, which can effectively reduce the possibility of incorrect programming. It also showed excellent retention characteristics and a simple structure friendly for integration. It can be well used in the field of high reliability of one-time programmable memory.
{"title":"A High-Density Large-Ratio Fuse Based Oxide Devices for One-time-programmable Memory Applications","authors":"Xuecheng Cui, Dong Liu, Jifang Cao, Xiao Yu, Bing Chen","doi":"10.1109/ICTA56932.2022.9962988","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962988","url":null,"abstract":"In this paper, the oxide fused and anti-fused behavior has been observed in a simple metal-oxide-metal device: Pt/HfO2/NiOx/Ni. The anti-fused state and fused state can be achieved by applying program voltage on the devices with or without current compliance, respectively. And the resistance window of the two states reaches about 109, which can effectively reduce the possibility of incorrect programming. It also showed excellent retention characteristics and a simple structure friendly for integration. It can be well used in the field of high reliability of one-time programmable memory.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124495987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963039
Zheng Lu, Shiquan Fan, Weiqing Ma, Ying Xie, Li Geng
In this paper, a wide input range boost converter is proposed. In consideration of the wide input voltage range, especially at very low input voltage, to guarantee the internal control circuit (ring oscillator and PFM controller) can operate correctly, an internal adaptive supply voltage generator is designed to produce 1 V supply voltage. The boost converter is fabricated with standard 0.18 µm 5P0 CMOS process. The active area of the boost converter is nearly 0.5 mm2. Measured results show that the boost converter can cold start with 700 mV input voltage and operate with input voltage range of 0.3 V-4 V, which demonstrate the design concepts of boost converter well.
本文提出了一种宽输入范围升压变换器。考虑到输入电压范围宽，特别是在输入电压很低的情况下，为了保证内部控制电路(环形振荡器和PFM控制器)能够正常工作，设计了一个内部自适应电源电压发生器，产生1 V的电源电压。升压变换器采用标准的0.18µm 5P0 CMOS工艺制造。升压变换器的有效面积接近0.5 mm2。实验结果表明，该升压变换器可以在700 mV输入电压下冷启动，在0.3 V ~ 4 V输入电压范围内工作，很好地体现了升压变换器的设计理念。
{"title":"A 0.3 V-4 V Input Voltage Range, 0.7 V Cold Start Boost Converter with 1 V Internal Voltage Supply Generator by Using 0.18 µm CMOS Process for Energy Harvesting Application","authors":"Zheng Lu, Shiquan Fan, Weiqing Ma, Ying Xie, Li Geng","doi":"10.1109/ICTA56932.2022.9963039","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963039","url":null,"abstract":"In this paper, a wide input range boost converter is proposed. In consideration of the wide input voltage range, especially at very low input voltage, to guarantee the internal control circuit (ring oscillator and PFM controller) can operate correctly, an internal adaptive supply voltage generator is designed to produce 1 V supply voltage. The boost converter is fabricated with standard 0.18 µm 5P0 CMOS process. The active area of the boost converter is nearly 0.5 mm2. Measured results show that the boost converter can cold start with 700 mV input voltage and operate with input voltage range of 0.3 V-4 V, which demonstrate the design concepts of boost converter well.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133945223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963007
Chi Chen, Kuan Hu, Weilin Luo, K. Yin, Ruiyuan Kang, Ying Zhao, Fei Yang
this paper presents a ka-band dual-port power amplifier, developed for low-orbit communication satellite. The power amplifier was designed based on 0.15 um gate length GaN MMIC power amplifiers. The RF output port is optional and controlled by external command. The maximum saturated power 25 W with a PAE of 33% has been achieved. The environmental tests for power amplifier have been carried out. The measured result and thermal vacuum test result have been shown in this paper. The power amplifier has been working well on-orbit for two years.
{"title":"A 20W Ka-Band Dual-Port Power Amplifier for Communication Satellites","authors":"Chi Chen, Kuan Hu, Weilin Luo, K. Yin, Ruiyuan Kang, Ying Zhao, Fei Yang","doi":"10.1109/ICTA56932.2022.9963007","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963007","url":null,"abstract":"this paper presents a ka-band dual-port power amplifier, developed for low-orbit communication satellite. The power amplifier was designed based on 0.15 um gate length GaN MMIC power amplifiers. The RF output port is optional and controlled by external command. The maximum saturated power 25 W with a PAE of 33% has been achieved. The environmental tests for power amplifier have been carried out. The measured result and thermal vacuum test result have been shown in this paper. The power amplifier has been working well on-orbit for two years.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"758 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132913318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963123
Xiaoqiang Tang, Jialin Cai
In this paper, a polynomial fitted poly-harmonic distortion (PHD) model is proposed, and it is implemented with frequency defined device (FDD). Polynomial fitting technique provides an effective method to including PHD model with different input power states through single set of model parameter. It can greatly reduce the model extraction complexity, and compact the model file size. The basic theory of PHD model, polynomial fitting method, and the FDD technique is provided in this work. A 10 W Gallium Nitride (GaN) packaged transistor is used in the test example. The results show that the proposed model has high accuracy for both fundamental and second harmonic behavioral predictions.
{"title":"Implementation of Polynomial Fitted Poly-Harmonic Distortion Model with Frequency Defined Device","authors":"Xiaoqiang Tang, Jialin Cai","doi":"10.1109/ICTA56932.2022.9963123","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963123","url":null,"abstract":"In this paper, a polynomial fitted poly-harmonic distortion (PHD) model is proposed, and it is implemented with frequency defined device (FDD). Polynomial fitting technique provides an effective method to including PHD model with different input power states through single set of model parameter. It can greatly reduce the model extraction complexity, and compact the model file size. The basic theory of PHD model, polynomial fitting method, and the FDD technique is provided in this work. A 10 W Gallium Nitride (GaN) packaged transistor is used in the test example. The results show that the proposed model has high accuracy for both fundamental and second harmonic behavioral predictions.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116154840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963134
L. Chang, Chenglong Li, Xin Zhao, Shuisheng Lin, Jun Zhou
Computing-in-memory (CIM) architecture is a promising solution toward energy-efficient artificial intelligent (AI) processor. Practically, the AI processor with CIM engine induces a series of issues including data updating and flexibility. For instance, in AI-oriented applications, the weight stored in the CIM must be reloaded due to the huge gap between limited capacity of CIM and growing weight parameter, which greatly reduces the computation efficiency of the AI processor. Moreover, the natural parallelism of CIM leads to the mismatch of various convolution kernel sizes in different networks and layers, which reduces hardware utilization efficiency. In this work, we explore a CIM engine with a ping-pong strategy as an alternative to traditional CIM macro and weight buffer, hiding the data update latency to enhance data reuse. In addition, we proposed a flexible CIM architecture adapting to different neural networks, namely IPOCIM, with a fine-grained data-flow mapping strategy. Based on the evaluation, IPOCIM achieves 1.4-7.1× performance improvement, and 2.2-6.1× energy efficiency, compared to baseline.
{"title":"IPOCIM: Artificial Intelligent Processor with Adaptive Ping-pong Computing-in-Memory Architecture","authors":"L. Chang, Chenglong Li, Xin Zhao, Shuisheng Lin, Jun Zhou","doi":"10.1109/ICTA56932.2022.9963134","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963134","url":null,"abstract":"Computing-in-memory (CIM) architecture is a promising solution toward energy-efficient artificial intelligent (AI) processor. Practically, the AI processor with CIM engine induces a series of issues including data updating and flexibility. For instance, in AI-oriented applications, the weight stored in the CIM must be reloaded due to the huge gap between limited capacity of CIM and growing weight parameter, which greatly reduces the computation efficiency of the AI processor. Moreover, the natural parallelism of CIM leads to the mismatch of various convolution kernel sizes in different networks and layers, which reduces hardware utilization efficiency. In this work, we explore a CIM engine with a ping-pong strategy as an alternative to traditional CIM macro and weight buffer, hiding the data update latency to enhance data reuse. In addition, we proposed a flexible CIM architecture adapting to different neural networks, namely IPOCIM, with a fine-grained data-flow mapping strategy. Based on the evaluation, IPOCIM achieves 1.4-7.1× performance improvement, and 2.2-6.1× energy efficiency, compared to baseline.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128764011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/icta56932.2022.9963058
{"title":"Proceedings of 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","authors":"","doi":"10.1109/icta56932.2022.9963058","DOIUrl":"https://doi.org/10.1109/icta56932.2022.9963058","url":null,"abstract":"","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123144159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a voltage error quantizer for digital low dropout regulators (DLDOs) with fast transient response and low steady-state error. Compared with traditional DLDOs quantizing the reference voltage and output voltage separately, the proposed voltage error quantizer quantifies the voltage difference directly with high quantization speed and accuracy. Implemented in 28nm CMOS process, the proposed quantizer with on-chip self-calibration identifies the voltage difference as small as 4mV and has stable output codes at sampling frequencies up to 500MHz, which satisfies the fast transient response and low steady-state error demands of DLDOs.
{"title":"A Voltage Error Quantizer For Digital Low Dropout Regulators With Fast Transient Response and Low Steady-State Error","authors":"Kaize Zhou, Dejian Li, Chongfei Shen, Yuxuan Du, Zhuo Chen, Weiwei Shan","doi":"10.1109/ICTA56932.2022.9962987","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962987","url":null,"abstract":"This paper proposes a voltage error quantizer for digital low dropout regulators (DLDOs) with fast transient response and low steady-state error. Compared with traditional DLDOs quantizing the reference voltage and output voltage separately, the proposed voltage error quantizer quantifies the voltage difference directly with high quantization speed and accuracy. Implemented in 28nm CMOS process, the proposed quantizer with on-chip self-calibration identifies the voltage difference as small as 4mV and has stable output codes at sampling frequencies up to 500MHz, which satisfies the fast transient response and low steady-state error demands of DLDOs.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134415619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9962977
Haiyang Yu, C. Kao
Due to its low cost, the Cu/Sn/Ni microbump is the most widely used structure in electronic packaging. Recent studies have characterized the evolution of the microstructure and phase formation in this system, and a unique (Cu,Ni)6Sn5 phase has been discovered with a high Ni content. However, there has been debate over the formation mechanism of this phase. This study builds a model of the formation mechanism of (Cu,Ni)6Sn5 and provides direct proof.
{"title":"Formation Mechanism of high Ni content (Cu, Ni)6Sn5 in Cu/Sn/Ni microbump for solid state aging","authors":"Haiyang Yu, C. Kao","doi":"10.1109/ICTA56932.2022.9962977","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962977","url":null,"abstract":"Due to its low cost, the Cu/Sn/Ni microbump is the most widely used structure in electronic packaging. Recent studies have characterized the evolution of the microstructure and phase formation in this system, and a unique (Cu,Ni)6Sn5 phase has been discovered with a high Ni content. However, there has been debate over the formation mechanism of this phase. This study builds a model of the formation mechanism of (Cu,Ni)6Sn5 and provides direct proof.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"129 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134505402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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