Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963086
Bowen Zhu
Flexible active-matrix sensor arrays provide large area and high spatial resolution for emerging sensing applications in electronic skin, health monitoring, and human-machine interfaces. However, it is still a challenge to achieve flexible active-matrix sensor arrays with low cost, low crosstalk, high sensitivity, and high uniformity characteristics. Here, we demonstrate a low-cost, high-resolution flexible sensor array by integrating solution-processed indium oxide (In2O3) transistor array with stimuli-sensitive (force, light, etc.) layers. This strategy provides an effective and universal solution to achieve large-area, active-matrix sensor arrays for future soft electronics applications.
{"title":"Dynamic Sensor Arrays Based on Solution-Processed Metal Oxide Semiconductor Thin-Film Transistors","authors":"Bowen Zhu","doi":"10.1109/ICTA56932.2022.9963086","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963086","url":null,"abstract":"Flexible active-matrix sensor arrays provide large area and high spatial resolution for emerging sensing applications in electronic skin, health monitoring, and human-machine interfaces. However, it is still a challenge to achieve flexible active-matrix sensor arrays with low cost, low crosstalk, high sensitivity, and high uniformity characteristics. Here, we demonstrate a low-cost, high-resolution flexible sensor array by integrating solution-processed indium oxide (In2O3) transistor array with stimuli-sensitive (force, light, etc.) layers. This strategy provides an effective and universal solution to achieve large-area, active-matrix sensor arrays for future soft electronics applications.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121331991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963060
Luhua Lin, Bowen Wang, W. Rhee, Zhihua Wang
This paper presents an analog-assisted digital low dropout regulator (LDO) by adopting a delta sigma modulator (DSM) and a finite impulse response (FIR) filter for reduced output ripple. By employing a dual-mode gain-controlled voltage detector (GCVD) and a gear-shift algorithm, reduced recovery time is achieved. An exponential-ratio array (ERA) is designed to expand the load current range. A charge pump (CP) LDO as an analog-assisted loop enhances transient performance. The proposed digital LDO is implemented in 180nm CMOS. For an output voltage of 0.9V, a maximum load current of 100mA and 5500× load current range are achieved with an input voltage of 1V. The undershooting voltage is 78mV when the load current changes from 210mA to 100mA, and the output ripple is 0.37mV.
{"title":"An Analog-Assisted Digital LDO with 0.37mV Output Ripple and 5500x Load Current Range in 180nm CMOS","authors":"Luhua Lin, Bowen Wang, W. Rhee, Zhihua Wang","doi":"10.1109/ICTA56932.2022.9963060","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963060","url":null,"abstract":"This paper presents an analog-assisted digital low dropout regulator (LDO) by adopting a delta sigma modulator (DSM) and a finite impulse response (FIR) filter for reduced output ripple. By employing a dual-mode gain-controlled voltage detector (GCVD) and a gear-shift algorithm, reduced recovery time is achieved. An exponential-ratio array (ERA) is designed to expand the load current range. A charge pump (CP) LDO as an analog-assisted loop enhances transient performance. The proposed digital LDO is implemented in 180nm CMOS. For an output voltage of 0.9V, a maximum load current of 100mA and 5500× load current range are achieved with an input voltage of 1V. The undershooting voltage is 78mV when the load current changes from 210mA to 100mA, and the output ripple is 0.37mV.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"291 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126022046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963079
Pengfei Wang, Minhan Mi, Sirui An, Xiang Du, Xiao-hua Ma, Yue Hao
In this letter, we demonstrate an AlGaN/GaN HEMT fabricated by synthesizing recess and planar devices along the gate width and incorporating N2O plasma treatment to form an oxide layer at the gate electrode of the proposed HEMT. The transconductance curve of the fabricated device has a plateau region larger than 7 V, with a flattened response curve of fT/fmaxwith respect to the gate bias voltage. At the operating frequency of 30 GHz, the maximum power-added efficiency (PAE) is 41%, the value of the power density ($mathrm{P}_{mathrm{o}mathrm{u}mathrm{t}}$ is 5.3 W/mm, and the associated 1dB compression point $(mathrm{p}_{mathrm{l}mathrm{d}mathrm{B}^{)}}$ is 28 dBm. The device presented in this article has excellent potential for millimeter-wave applications where high linearity is essential.
{"title":"A Novel Concept of using Double Threshold Voltage Coupling to Improve the linearity of AlGaN/GaN HEMTs for millimeter-wave applications","authors":"Pengfei Wang, Minhan Mi, Sirui An, Xiang Du, Xiao-hua Ma, Yue Hao","doi":"10.1109/ICTA56932.2022.9963079","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963079","url":null,"abstract":"In this letter, we demonstrate an AlGaN/GaN HEMT fabricated by synthesizing recess and planar devices along the gate width and incorporating N2O plasma treatment to form an oxide layer at the gate electrode of the proposed HEMT. The transconductance curve of the fabricated device has a plateau region larger than 7 V, with a flattened response curve of fT/fmaxwith respect to the gate bias voltage. At the operating frequency of 30 GHz, the maximum power-added efficiency (PAE) is 41%, the value of the power density ($mathrm{P}_{mathrm{o}mathrm{u}mathrm{t}}$ is 5.3 W/mm, and the associated 1dB compression point $(mathrm{p}_{mathrm{l}mathrm{d}mathrm{B}^{)}}$ is 28 dBm. The device presented in this article has excellent potential for millimeter-wave applications where high linearity is essential.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126548017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963007
Chi Chen, Kuan Hu, Weilin Luo, K. Yin, Ruiyuan Kang, Ying Zhao, Fei Yang
this paper presents a ka-band dual-port power amplifier, developed for low-orbit communication satellite. The power amplifier was designed based on 0.15 um gate length GaN MMIC power amplifiers. The RF output port is optional and controlled by external command. The maximum saturated power 25 W with a PAE of 33% has been achieved. The environmental tests for power amplifier have been carried out. The measured result and thermal vacuum test result have been shown in this paper. The power amplifier has been working well on-orbit for two years.
{"title":"A 20W Ka-Band Dual-Port Power Amplifier for Communication Satellites","authors":"Chi Chen, Kuan Hu, Weilin Luo, K. Yin, Ruiyuan Kang, Ying Zhao, Fei Yang","doi":"10.1109/ICTA56932.2022.9963007","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963007","url":null,"abstract":"this paper presents a ka-band dual-port power amplifier, developed for low-orbit communication satellite. The power amplifier was designed based on 0.15 um gate length GaN MMIC power amplifiers. The RF output port is optional and controlled by external command. The maximum saturated power 25 W with a PAE of 33% has been achieved. The environmental tests for power amplifier have been carried out. The measured result and thermal vacuum test result have been shown in this paper. The power amplifier has been working well on-orbit for two years.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"758 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132913318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963039
Zheng Lu, Shiquan Fan, Weiqing Ma, Ying Xie, Li Geng
In this paper, a wide input range boost converter is proposed. In consideration of the wide input voltage range, especially at very low input voltage, to guarantee the internal control circuit (ring oscillator and PFM controller) can operate correctly, an internal adaptive supply voltage generator is designed to produce 1 V supply voltage. The boost converter is fabricated with standard 0.18 µm 5P0 CMOS process. The active area of the boost converter is nearly 0.5 mm2. Measured results show that the boost converter can cold start with 700 mV input voltage and operate with input voltage range of 0.3 V-4 V, which demonstrate the design concepts of boost converter well.
本文提出了一种宽输入范围升压变换器。考虑到输入电压范围宽，特别是在输入电压很低的情况下，为了保证内部控制电路(环形振荡器和PFM控制器)能够正常工作，设计了一个内部自适应电源电压发生器，产生1 V的电源电压。升压变换器采用标准的0.18µm 5P0 CMOS工艺制造。升压变换器的有效面积接近0.5 mm2。实验结果表明，该升压变换器可以在700 mV输入电压下冷启动，在0.3 V ~ 4 V输入电压范围内工作，很好地体现了升压变换器的设计理念。
{"title":"A 0.3 V-4 V Input Voltage Range, 0.7 V Cold Start Boost Converter with 1 V Internal Voltage Supply Generator by Using 0.18 µm CMOS Process for Energy Harvesting Application","authors":"Zheng Lu, Shiquan Fan, Weiqing Ma, Ying Xie, Li Geng","doi":"10.1109/ICTA56932.2022.9963039","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963039","url":null,"abstract":"In this paper, a wide input range boost converter is proposed. In consideration of the wide input voltage range, especially at very low input voltage, to guarantee the internal control circuit (ring oscillator and PFM controller) can operate correctly, an internal adaptive supply voltage generator is designed to produce 1 V supply voltage. The boost converter is fabricated with standard 0.18 µm 5P0 CMOS process. The active area of the boost converter is nearly 0.5 mm2. Measured results show that the boost converter can cold start with 700 mV input voltage and operate with input voltage range of 0.3 V-4 V, which demonstrate the design concepts of boost converter well.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133945223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/icta56932.2022.9963058
{"title":"Proceedings of 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","authors":"","doi":"10.1109/icta56932.2022.9963058","DOIUrl":"https://doi.org/10.1109/icta56932.2022.9963058","url":null,"abstract":"","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123144159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963134
L. Chang, Chenglong Li, Xin Zhao, Shuisheng Lin, Jun Zhou
Computing-in-memory (CIM) architecture is a promising solution toward energy-efficient artificial intelligent (AI) processor. Practically, the AI processor with CIM engine induces a series of issues including data updating and flexibility. For instance, in AI-oriented applications, the weight stored in the CIM must be reloaded due to the huge gap between limited capacity of CIM and growing weight parameter, which greatly reduces the computation efficiency of the AI processor. Moreover, the natural parallelism of CIM leads to the mismatch of various convolution kernel sizes in different networks and layers, which reduces hardware utilization efficiency. In this work, we explore a CIM engine with a ping-pong strategy as an alternative to traditional CIM macro and weight buffer, hiding the data update latency to enhance data reuse. In addition, we proposed a flexible CIM architecture adapting to different neural networks, namely IPOCIM, with a fine-grained data-flow mapping strategy. Based on the evaluation, IPOCIM achieves 1.4-7.1× performance improvement, and 2.2-6.1× energy efficiency, compared to baseline.
{"title":"IPOCIM: Artificial Intelligent Processor with Adaptive Ping-pong Computing-in-Memory Architecture","authors":"L. Chang, Chenglong Li, Xin Zhao, Shuisheng Lin, Jun Zhou","doi":"10.1109/ICTA56932.2022.9963134","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963134","url":null,"abstract":"Computing-in-memory (CIM) architecture is a promising solution toward energy-efficient artificial intelligent (AI) processor. Practically, the AI processor with CIM engine induces a series of issues including data updating and flexibility. For instance, in AI-oriented applications, the weight stored in the CIM must be reloaded due to the huge gap between limited capacity of CIM and growing weight parameter, which greatly reduces the computation efficiency of the AI processor. Moreover, the natural parallelism of CIM leads to the mismatch of various convolution kernel sizes in different networks and layers, which reduces hardware utilization efficiency. In this work, we explore a CIM engine with a ping-pong strategy as an alternative to traditional CIM macro and weight buffer, hiding the data update latency to enhance data reuse. In addition, we proposed a flexible CIM architecture adapting to different neural networks, namely IPOCIM, with a fine-grained data-flow mapping strategy. Based on the evaluation, IPOCIM achieves 1.4-7.1× performance improvement, and 2.2-6.1× energy efficiency, compared to baseline.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128764011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963126
Yifa Wang, Tong Wu, Jianping Guo
This paper presents a low dropout regulator (LDO) with ampere-level loading capability and wide input range. The NMOS power transistor with built-in charge pump was adopted to reduce the dropout voltage thus increase the power efficiency effectively. To realize a wide input voltage range, the fully-integrated charge pump can be configured adaptively for different input voltage. The proposed LDO has been designed and implemented in a 180nm CMOS technology. Experimental results show that the LDO has a wide input voltage range of 1.0~6.5 V, a wide output voltage range of 0.8~5.5 V, and a maximum output current of 1.5 A. In addition, the dropout voltage is only 110 mV under 1.5 A loading condition.
{"title":"A Charge Pump Based 1.5A NMOS LDO with 1.0~6.5V Input Range and 110mV Dropout Voltage","authors":"Yifa Wang, Tong Wu, Jianping Guo","doi":"10.1109/ICTA56932.2022.9963126","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963126","url":null,"abstract":"This paper presents a low dropout regulator (LDO) with ampere-level loading capability and wide input range. The NMOS power transistor with built-in charge pump was adopted to reduce the dropout voltage thus increase the power efficiency effectively. To realize a wide input voltage range, the fully-integrated charge pump can be configured adaptively for different input voltage. The proposed LDO has been designed and implemented in a 180nm CMOS technology. Experimental results show that the LDO has a wide input voltage range of 1.0~6.5 V, a wide output voltage range of 0.8~5.5 V, and a maximum output current of 1.5 A. In addition, the dropout voltage is only 110 mV under 1.5 A loading condition.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131543316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a low noise and low power circuit for neural recording. A Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) with embedded DC feedback is proposed to reduce the noise of system. Implemented a continuous-time low-pass filter (LPF) at the output of the system and utilized bulk-feedback techniques to increase its output swing. Furthermore, the DC-block and Chopper-Capacitor-Chopper Integrator Based DC Servo Loop (C3IB-DSL) are combined to reduce the interferences. According to experiment, the circuit consumes only 0.3 µW at 1.2 V. In addition, the input-referred noise reached 2.1 µVrms and the noise efficiency factor (NEF) 3.6 at the same time. The proposed CCIA was simulated in a 180n CMOS process.
{"title":"A 0.3-µW,2.1-µVrms Neural Recording Chopper Amplifier with Low Noise DC-Servo-Loop","authors":"Yuchen Bao, Weijian Chen, Zhixian Li, Yongsen Chen, Yanhan Zeng","doi":"10.1109/ICTA56932.2022.9963006","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963006","url":null,"abstract":"This paper presents a low noise and low power circuit for neural recording. A Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) with embedded DC feedback is proposed to reduce the noise of system. Implemented a continuous-time low-pass filter (LPF) at the output of the system and utilized bulk-feedback techniques to increase its output swing. Furthermore, the DC-block and Chopper-Capacitor-Chopper Integrator Based DC Servo Loop (C3IB-DSL) are combined to reduce the interferences. According to experiment, the circuit consumes only 0.3 µW at 1.2 V. In addition, the input-referred noise reached 2.1 µVrms and the noise efficiency factor (NEF) 3.6 at the same time. The proposed CCIA was simulated in a 180n CMOS process.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131194274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a voltage error quantizer for digital low dropout regulators (DLDOs) with fast transient response and low steady-state error. Compared with traditional DLDOs quantizing the reference voltage and output voltage separately, the proposed voltage error quantizer quantifies the voltage difference directly with high quantization speed and accuracy. Implemented in 28nm CMOS process, the proposed quantizer with on-chip self-calibration identifies the voltage difference as small as 4mV and has stable output codes at sampling frequencies up to 500MHz, which satisfies the fast transient response and low steady-state error demands of DLDOs.
{"title":"A Voltage Error Quantizer For Digital Low Dropout Regulators With Fast Transient Response and Low Steady-State Error","authors":"Kaize Zhou, Dejian Li, Chongfei Shen, Yuxuan Du, Zhuo Chen, Weiwei Shan","doi":"10.1109/ICTA56932.2022.9962987","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962987","url":null,"abstract":"This paper proposes a voltage error quantizer for digital low dropout regulators (DLDOs) with fast transient response and low steady-state error. Compared with traditional DLDOs quantizing the reference voltage and output voltage separately, the proposed voltage error quantizer quantifies the voltage difference directly with high quantization speed and accuracy. Implemented in 28nm CMOS process, the proposed quantizer with on-chip self-calibration identifies the voltage difference as small as 4mV and has stable output codes at sampling frequencies up to 500MHz, which satisfies the fast transient response and low steady-state error demands of DLDOs.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134415619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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