Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963054
Zhiqiang Luo, Peng Wang, Fule Li, Chun Zhang, Zhihua Wang
This paper presents a statistics-based background capacitor mismatch calibration algorithm for successive approximation register (SAR) analog-to-digital converter (ADC). The calibration algorithm is capable of detecting capacitor mismatch errors based on statistical principles and signal correlation is eliminated by introducing additional dummy capacitors, leading to fast convergence. This calibration increases the signal-to-noise-and-distortion ratio (SNDR) from 64.57dB to 82.03dB and achieves 29dB spurious-free dynamic range (SFDR) improvement. The simulated differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.17/-0.13LSB and +0.36/-0.38LSB respectively.
{"title":"A statistics-based background capacitor mismatch calibration algorithm for SAR ADC","authors":"Zhiqiang Luo, Peng Wang, Fule Li, Chun Zhang, Zhihua Wang","doi":"10.1109/ICTA56932.2022.9963054","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963054","url":null,"abstract":"This paper presents a statistics-based background capacitor mismatch calibration algorithm for successive approximation register (SAR) analog-to-digital converter (ADC). The calibration algorithm is capable of detecting capacitor mismatch errors based on statistical principles and signal correlation is eliminated by introducing additional dummy capacitors, leading to fast convergence. This calibration increases the signal-to-noise-and-distortion ratio (SNDR) from 64.57dB to 82.03dB and achieves 29dB spurious-free dynamic range (SFDR) improvement. The simulated differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.17/-0.13LSB and +0.36/-0.38LSB respectively.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133974759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a fully synthesizable injection locked phase-locked loop (PLL), with a dual-DCO frequency tracking. The design has been fabricated in 55-nm CMOS and the layout is realized completely by digital flows. The proposed PLL covers a 0.2-to-1.2-GHz tuning range, achieving an absolute rms jitter (integrated from 100kHz to 100MHz) of 3.2ps at 4.3-mW power consumption, with a corresponding jitter-power figure of merit (FoM) of -224dB and the occupied core area is only 0.0225 mm2.
{"title":"A Fully Synthesizable Injection Locked PLL with Dual-DCO Frequency Tracking in 55nm CMOS","authors":"Xuanchi Yu, Yan Chen, Gaofena Jin, Fei Feng, Xun Luo, Xiang Gao","doi":"10.1109/ICTA56932.2022.9962990","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962990","url":null,"abstract":"This paper presents a fully synthesizable injection locked phase-locked loop (PLL), with a dual-DCO frequency tracking. The design has been fabricated in 55-nm CMOS and the layout is realized completely by digital flows. The proposed PLL covers a 0.2-to-1.2-GHz tuning range, achieving an absolute rms jitter (integrated from 100kHz to 100MHz) of 3.2ps at 4.3-mW power consumption, with a corresponding jitter-power figure of merit (FoM) of -224dB and the occupied core area is only 0.0225 mm2.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116412539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963005
Han Yang, Bin Yan, Jianjun Sur, Jian Pang, Guanavao Li, Ouvana Keqing, Shuaiana Zhang
This present report mainly covers 2.5/3DIC system efficient and accurate thermal analysis. This report not only conducts the thermal coupling among dies, PCB, package at system level, but also performs accurate and detailed thermal analysis on specific hotspot regions. More importantly, the BEOL/RDL layer has a signicant impact on the juction temperature of the die, especially the hotspot region, which is often ignored in both industrial and academic area. Thus, the BEOL/RDL layer is incorporated into the thermal simulation by simplying the BEOL/RDL layer as the metal density. According to the simulation results, under steady-state conditions, the BEOL layer has a greater impact on the junction temperature, and under transient conditions, it has less impact on the transient temperature rise rate.
{"title":"Accurate 3DIC thermal simulation for BEOL influence study","authors":"Han Yang, Bin Yan, Jianjun Sur, Jian Pang, Guanavao Li, Ouvana Keqing, Shuaiana Zhang","doi":"10.1109/ICTA56932.2022.9963005","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963005","url":null,"abstract":"This present report mainly covers 2.5/3DIC system efficient and accurate thermal analysis. This report not only conducts the thermal coupling among dies, PCB, package at system level, but also performs accurate and detailed thermal analysis on specific hotspot regions. More importantly, the BEOL/RDL layer has a signicant impact on the juction temperature of the die, especially the hotspot region, which is often ignored in both industrial and academic area. Thus, the BEOL/RDL layer is incorporated into the thermal simulation by simplying the BEOL/RDL layer as the metal density. According to the simulation results, under steady-state conditions, the BEOL layer has a greater impact on the junction temperature, and under transient conditions, it has less impact on the transient temperature rise rate.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127451890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Event-driven asynchronous circuits are gaining attention because of their low power consumption and robustness. Among asynchronous circuits, the Bundled data (BD) circuit used by Loihi has attracted attention because it can obtain a similar area as a synchronous circuit. Click circuit is a mainstream BD circuit, but due to the lack of DFT (Design For Test) architecture, the Click-based asynchronous circuit cannot be widely used. This paper proposes a DFT architecture suitable for BD circuits, which can be accomplished using traditional EDA tools rather than developing new ones. This paper verifies the proposed DFT architecture on a five-stage pipeline processor based on the RISC-V instruction set. The result is 99.62% coverage for stuck-at faults, 1.8398% area overhead, and 6.2259% power overhead.
事件驱动异步电路由于其低功耗和鲁棒性而受到越来越多的关注。在异步电路中，Loihi使用的捆绑数据(BD)电路因其可以获得与同步电路相似的面积而受到关注。Click电路是一种主流的BD电路，但由于缺乏DFT (Design For Test)架构，基于Click的异步电路无法得到广泛应用。本文提出了一种适用于双相电路的DFT体系结构，它可以使用传统的EDA工具来完成，而无需开发新的EDA工具。本文在基于RISC-V指令集的五级流水线处理器上验证了所提出的DFT架构。结果是99.62%的卡故障覆盖率、1.8398%的面积开销和6.2259%的功率开销。
{"title":"DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits","authors":"Ruimin Zhu, Zeyang Xu, Yuhao Huang, Shanlin Xiao, Zhiyi Yu","doi":"10.1109/ICTA56932.2022.9963092","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963092","url":null,"abstract":"Event-driven asynchronous circuits are gaining attention because of their low power consumption and robustness. Among asynchronous circuits, the Bundled data (BD) circuit used by Loihi has attracted attention because it can obtain a similar area as a synchronous circuit. Click circuit is a mainstream BD circuit, but due to the lack of DFT (Design For Test) architecture, the Click-based asynchronous circuit cannot be widely used. This paper proposes a DFT architecture suitable for BD circuits, which can be accomplished using traditional EDA tools rather than developing new ones. This paper verifies the proposed DFT architecture on a five-stage pipeline processor based on the RISC-V instruction set. The result is 99.62% coverage for stuck-at faults, 1.8398% area overhead, and 6.2259% power overhead.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121428225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963067
Qing Zhang, Keping Wang
This paper presents a 77–101 GHz active 6-bit phase shifter based on a vector-modulated technique in 65 $n$ m SOI CMOS technology for W-band phased-array systems. Optimizations of the impedance-invariant variable gain amplifier (VGA) are performed to reduce the phase error and gain error among the phase states. In addition, a quadrature signal generator composed of a 90-degree hybrid and a pair of Marchand balun is exploited for wideband applications. The proposed phase shifter achieves 5.6° phase step, < 2.0° RMS phase error and < 0.8dB RMS gain error over 77–101 GHz. The total power consumption is 31mW and the core area of the phase shifter is only 0.2mm2.
{"title":"A 77-101GHz 6-Bit Vector-Modulated Phase Shifter with Low RMS Error in 65nm SOI CMOS","authors":"Qing Zhang, Keping Wang","doi":"10.1109/ICTA56932.2022.9963067","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963067","url":null,"abstract":"This paper presents a 77–101 GHz active 6-bit phase shifter based on a vector-modulated technique in 65 $n$ m SOI CMOS technology for W-band phased-array systems. Optimizations of the impedance-invariant variable gain amplifier (VGA) are performed to reduce the phase error and gain error among the phase states. In addition, a quadrature signal generator composed of a 90-degree hybrid and a pair of Marchand balun is exploited for wideband applications. The proposed phase shifter achieves 5.6° phase step, < 2.0° RMS phase error and < 0.8dB RMS gain error over 77–101 GHz. The total power consumption is 31mW and the core area of the phase shifter is only 0.2mm2.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132638032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a single-input dual-output (SIDO) three-level buck converter to meet the requirements of multi-voltage domain and high voltage stress for SoC applications. The topology is based on three-level buck with standard 1.8V devices, where only an additional power switch is added. By using this structure, the second output can be powered by a fly capacitor, and $V$CF calibration is achieved by the control loop for reliability issues. Hence the efficiency and the power density are enhanced with standard devices and reducing the number of power switches. Moreover, the control loop with error processor and driver module is demonstrated based on the topology analysis. Ultimately, the proposed converter is designed and fabricated with 0.18μm CMOS process, which handles the input range of 3.3-2.8V and dual-output of 1.8V and 1.2V with 96.9% peak efficiency. The power density is 2.557W/mm2, and the active area is only 0.49 mm2.
{"title":"A Single-input Dual-output Three-level Buck Converter for SoC Applications","authors":"Zhuoneng Li, Zhonamina Xue, Chenalona Liang, Yongchao Zhang, Mengqi Duan, Shangzhou Zhao, Xihao Liu, Zhuoqi Guo, Li Geng","doi":"10.1109/ICTA56932.2022.9963024","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963024","url":null,"abstract":"This paper proposes a single-input dual-output (SIDO) three-level buck converter to meet the requirements of multi-voltage domain and high voltage stress for SoC applications. The topology is based on three-level buck with standard 1.8V devices, where only an additional power switch is added. By using this structure, the second output can be powered by a fly capacitor, and $V$CF calibration is achieved by the control loop for reliability issues. Hence the efficiency and the power density are enhanced with standard devices and reducing the number of power switches. Moreover, the control loop with error processor and driver module is demonstrated based on the topology analysis. Ultimately, the proposed converter is designed and fabricated with 0.18μm CMOS process, which handles the input range of 3.3-2.8V and dual-output of 1.8V and 1.2V with 96.9% peak efficiency. The power density is 2.557W/mm2, and the active area is only 0.49 mm2.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132646208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963017
Ke Han, Dao-ben Li
Large-scale matrix inversion is widely used in massive Multiple Input Multiple Output (MIMO) beamforming systems, but matrix inversion is very complicated in hardware implementation. In this paper, Hermitian matrix decomposition method based on partitioned systolic array is proposed, and the computing structure of the algorithm is improved flexibly by utilizing the partitioned characteristics of large-scale matrix. We compare our method with existing FPGA-based technologies on Xilinx ZCU102 FPGA. The results of the experiment show that our method has better performance than existing techniques in resource utilization, device delay and maximum working frequency when the size of Hermitian matrix is 32 × 32, which is a typical size for MIMO applications.
{"title":"Low-Latency FPGA Design and Implementation of Hermitian Matrix Inversion Based on Partitioned Systolic Array for Massive MIMO","authors":"Ke Han, Dao-ben Li","doi":"10.1109/ICTA56932.2022.9963017","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963017","url":null,"abstract":"Large-scale matrix inversion is widely used in massive Multiple Input Multiple Output (MIMO) beamforming systems, but matrix inversion is very complicated in hardware implementation. In this paper, Hermitian matrix decomposition method based on partitioned systolic array is proposed, and the computing structure of the algorithm is improved flexibly by utilizing the partitioned characteristics of large-scale matrix. We compare our method with existing FPGA-based technologies on Xilinx ZCU102 FPGA. The results of the experiment show that our method has better performance than existing techniques in resource utilization, device delay and maximum working frequency when the size of Hermitian matrix is 32 × 32, which is a typical size for MIMO applications.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124430842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963015
Jiahao Zhao, Xuansheng Ji, Su Han, Ziwei Wang, W. Rhee, Zhihua Wang
A 0.7-2.5GHz NB-IoT/GNSS/BLE hybrid PLL with a single D/VCO is implemented in 28nm CMOS. With careful frequency planning, the PA pulling effect is mitigated by using a multi-mode divider chain. A divider-by-2.5 relaxes the tuning range requirement of the D/VCO and mitigates the PA pulling for NB-IoT HB band, while a divider-by-6 is designed for NB-IoT LB. With an 8-tap FIR filtering method, a wideband fractional-N PLL is designed without increasing the out-of-band phase noise. The proposed PLL consumes the maximum 4.7mW with 0.9V supply. Experimental results show that the PLL meets the phase noise and spur requirements of the NB-IoT/GNSS/BLE standards.
{"title":"A 0.7-2.5GHz NB-loT/GNSS/BLE Hybrid PLL with PA Pulling Mitigation and Out-of-Band Phase Noise Reduction","authors":"Jiahao Zhao, Xuansheng Ji, Su Han, Ziwei Wang, W. Rhee, Zhihua Wang","doi":"10.1109/ICTA56932.2022.9963015","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963015","url":null,"abstract":"A 0.7-2.5GHz NB-IoT/GNSS/BLE hybrid PLL with a single D/VCO is implemented in 28nm CMOS. With careful frequency planning, the PA pulling effect is mitigated by using a multi-mode divider chain. A divider-by-2.5 relaxes the tuning range requirement of the D/VCO and mitigates the PA pulling for NB-IoT HB band, while a divider-by-6 is designed for NB-IoT LB. With an 8-tap FIR filtering method, a wideband fractional-N PLL is designed without increasing the out-of-band phase noise. The proposed PLL consumes the maximum 4.7mW with 0.9V supply. Experimental results show that the PLL meets the phase noise and spur requirements of the NB-IoT/GNSS/BLE standards.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121535851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963094
Sheng Zuo, Junjie Zhuang, Yao Liu, Mingyu Wang, Zhiyi Yu
Instruction set randomization has been proposed for many years as a strategy against code injection. However, most of the methods are based entirely on software, which is vulnerable to possible threats like key leakage or bypassing attack. The translation of instructions also brings the loss of performance. Some designs randomize the instruction set based on hardware, but using weak approaches which can be easily bypassed. In this paper, we propose a hybrid instruction set randomization with both compiler support and hardware extension on a RISC-V processor. We adopt AES-128 to randomize RISC-V instruction set with little performance loss. The design has been implemented on Xilinx AV7K325 FPGA board, the results shows that RISC-V instruction set is randomized with no changes in clock frequency, 1377 LUTs increase in resources and 0.38% performance overhead.
{"title":"Hardware Based RISC-V Instruction Set Randomization","authors":"Sheng Zuo, Junjie Zhuang, Yao Liu, Mingyu Wang, Zhiyi Yu","doi":"10.1109/ICTA56932.2022.9963094","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963094","url":null,"abstract":"Instruction set randomization has been proposed for many years as a strategy against code injection. However, most of the methods are based entirely on software, which is vulnerable to possible threats like key leakage or bypassing attack. The translation of instructions also brings the loss of performance. Some designs randomize the instruction set based on hardware, but using weak approaches which can be easily bypassed. In this paper, we propose a hybrid instruction set randomization with both compiler support and hardware extension on a RISC-V processor. We adopt AES-128 to randomize RISC-V instruction set with little performance loss. The design has been implemented on Xilinx AV7K325 FPGA board, the results shows that RISC-V instruction set is randomized with no changes in clock frequency, 1377 LUTs increase in resources and 0.38% performance overhead.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115077854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963077
Hengzhi Wan, Dixian Zhao
This paper presents a V-band power amplifier (PA) with two stages. Each stage consists of a neutralized common-source amplifier pair, coupled with each other using a transformer. Implemented in 40-nm CMOS technology, the proposed two-stage PA achieves a measured small-signal gain of 16.8 dB at 47 GHz with a 3-dB bandwidth more than 6.5 GHz. The maximum 1-dB compressed output power (P1dB) is 12.2 dBm with a power-added efficiency at P1dB (PAE1dB) of 18% measured at 47 GHz; from 45 to 51 GHz, the measured P1dBis above 10 dBm under a 1.1-V supply voltage.
{"title":"A V-band Power Amplifier for Satellite Communications in 40-nm CMOS","authors":"Hengzhi Wan, Dixian Zhao","doi":"10.1109/ICTA56932.2022.9963077","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963077","url":null,"abstract":"This paper presents a V-band power amplifier (PA) with two stages. Each stage consists of a neutralized common-source amplifier pair, coupled with each other using a transformer. Implemented in 40-nm CMOS technology, the proposed two-stage PA achieves a measured small-signal gain of 16.8 dB at 47 GHz with a 3-dB bandwidth more than 6.5 GHz. The maximum 1-dB compressed output power (P1dB) is 12.2 dBm with a power-added efficiency at P1dB (PAE1dB) of 18% measured at 47 GHz; from 45 to 51 GHz, the measured P1dBis above 10 dBm under a 1.1-V supply voltage.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130097307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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