Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9962981
Yu Wang, Yi Liu, Jiayu Bao, Yu Yan, Ertao Hu, Xiang Wan, R. Xu, Haotong Zhang, Yi Tong
Memristors have sparked substantial interest in the hardware implementation of brain-inspired neuromorphic devices and systems. In this work, we propose a digital circuit to emulate the Pavlov's associative memory experiments based on fabricated Ag/TiO2/Pt memristors. Memristors operate as a logical signal processing unit in conjunction with the register to implement the emulation. The design of digital circuitry substantially increases the frequency of the system and reduces its power consumption and cost.
{"title":"Memristor-based Digital Circuits for Realizing the Pavlov's Associative Neural Network","authors":"Yu Wang, Yi Liu, Jiayu Bao, Yu Yan, Ertao Hu, Xiang Wan, R. Xu, Haotong Zhang, Yi Tong","doi":"10.1109/ICTA56932.2022.9962981","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962981","url":null,"abstract":"Memristors have sparked substantial interest in the hardware implementation of brain-inspired neuromorphic devices and systems. In this work, we propose a digital circuit to emulate the Pavlov's associative memory experiments based on fabricated Ag/TiO2/Pt memristors. Memristors operate as a logical signal processing unit in conjunction with the register to implement the emulation. The design of digital circuitry substantially increases the frequency of the system and reduces its power consumption and cost.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132197766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963027
Ying Yu, Xufeng Liao, Lianxi Liu
This paper presents a fast sampling open-circuit voltage algorithm for piezoelectric energy harvesting, which directly samples the output of the piezoelectric transducer and limits the sampling time to one piezoelectric vibration period. Therefore, it greatly reduces the power loss caused by the open-circuit sampling and improves the efficiency of the piezoelectric energy harvesting. The proposed circuit is implemented in 0.18 µm standard CMOS process, and the core circuit area is 670×536 µm2. The circuit can sample the open-circuit voltage in less than one piezoelectric vibration cycle and output the maximum power point voltage, and the power loss rate is less than 0.79%.
{"title":"A Fast Sampling Open-circuit Voltage Algorithm for Piezoelectric Energy Harvesting","authors":"Ying Yu, Xufeng Liao, Lianxi Liu","doi":"10.1109/ICTA56932.2022.9963027","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963027","url":null,"abstract":"This paper presents a fast sampling open-circuit voltage algorithm for piezoelectric energy harvesting, which directly samples the output of the piezoelectric transducer and limits the sampling time to one piezoelectric vibration period. Therefore, it greatly reduces the power loss caused by the open-circuit sampling and improves the efficiency of the piezoelectric energy harvesting. The proposed circuit is implemented in 0.18 µm standard CMOS process, and the core circuit area is 670×536 µm2. The circuit can sample the open-circuit voltage in less than one piezoelectric vibration cycle and output the maximum power point voltage, and the power loss rate is less than 0.79%.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134605161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a low noise and low power circuit for neural recording. A Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) with embedded DC feedback is proposed to reduce the noise of system. Implemented a continuous-time low-pass filter (LPF) at the output of the system and utilized bulk-feedback techniques to increase its output swing. Furthermore, the DC-block and Chopper-Capacitor-Chopper Integrator Based DC Servo Loop (C3IB-DSL) are combined to reduce the interferences. According to experiment, the circuit consumes only 0.3 µW at 1.2 V. In addition, the input-referred noise reached 2.1 µVrms and the noise efficiency factor (NEF) 3.6 at the same time. The proposed CCIA was simulated in a 180n CMOS process.
{"title":"A 0.3-µW,2.1-µVrms Neural Recording Chopper Amplifier with Low Noise DC-Servo-Loop","authors":"Yuchen Bao, Weijian Chen, Zhixian Li, Yongsen Chen, Yanhan Zeng","doi":"10.1109/ICTA56932.2022.9963006","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963006","url":null,"abstract":"This paper presents a low noise and low power circuit for neural recording. A Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) with embedded DC feedback is proposed to reduce the noise of system. Implemented a continuous-time low-pass filter (LPF) at the output of the system and utilized bulk-feedback techniques to increase its output swing. Furthermore, the DC-block and Chopper-Capacitor-Chopper Integrator Based DC Servo Loop (C3IB-DSL) are combined to reduce the interferences. According to experiment, the circuit consumes only 0.3 µW at 1.2 V. In addition, the input-referred noise reached 2.1 µVrms and the noise efficiency factor (NEF) 3.6 at the same time. The proposed CCIA was simulated in a 180n CMOS process.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131194274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963126
Yifa Wang, Tong Wu, Jianping Guo
This paper presents a low dropout regulator (LDO) with ampere-level loading capability and wide input range. The NMOS power transistor with built-in charge pump was adopted to reduce the dropout voltage thus increase the power efficiency effectively. To realize a wide input voltage range, the fully-integrated charge pump can be configured adaptively for different input voltage. The proposed LDO has been designed and implemented in a 180nm CMOS technology. Experimental results show that the LDO has a wide input voltage range of 1.0~6.5 V, a wide output voltage range of 0.8~5.5 V, and a maximum output current of 1.5 A. In addition, the dropout voltage is only 110 mV under 1.5 A loading condition.
{"title":"A Charge Pump Based 1.5A NMOS LDO with 1.0~6.5V Input Range and 110mV Dropout Voltage","authors":"Yifa Wang, Tong Wu, Jianping Guo","doi":"10.1109/ICTA56932.2022.9963126","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963126","url":null,"abstract":"This paper presents a low dropout regulator (LDO) with ampere-level loading capability and wide input range. The NMOS power transistor with built-in charge pump was adopted to reduce the dropout voltage thus increase the power efficiency effectively. To realize a wide input voltage range, the fully-integrated charge pump can be configured adaptively for different input voltage. The proposed LDO has been designed and implemented in a 180nm CMOS technology. Experimental results show that the LDO has a wide input voltage range of 1.0~6.5 V, a wide output voltage range of 0.8~5.5 V, and a maximum output current of 1.5 A. In addition, the dropout voltage is only 110 mV under 1.5 A loading condition.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131543316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9962968
Chi Zhang, Lei Kang, Xu Yang, Guanghao Guo, P. Feng, Shuangming Yu, Liyuan Liu
Dynamic vision sensor (DVS), an event-based camera, has attracted significant attention due to its unique characteristics. Unlike frame-based cameras, the data format of DVS makes it difficult for traditional algorithms to process it directly. On the other hand, as a new type of brain-like neural network, the spiking neural network is specially used to process spiking data, and it is well suited for this type of event-based camera. In addition, because of the rapid development of neuromorphic hardware in recent years, it is possible to deploy SNN applications on edge-side system-on-chip. Therefore, based on the characteristics of dynamic vision sensors, this paper designs a spike encoding module and an SNN for processing sensor information. We use selective search to accomplish object tracking by classifying targets and backgrounds. The SNN can achieve 98.66% classification accuracy on our synthetic test dataset, and the tracking algorithm can achieve over 1000 fps after quantizing and compiling the network to the hardware simulator.
{"title":"A 1000 fps Spiking Neural Network Tracking Algorithm for On-Chip Processing of Dynamic Vision Sensor Data","authors":"Chi Zhang, Lei Kang, Xu Yang, Guanghao Guo, P. Feng, Shuangming Yu, Liyuan Liu","doi":"10.1109/ICTA56932.2022.9962968","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962968","url":null,"abstract":"Dynamic vision sensor (DVS), an event-based camera, has attracted significant attention due to its unique characteristics. Unlike frame-based cameras, the data format of DVS makes it difficult for traditional algorithms to process it directly. On the other hand, as a new type of brain-like neural network, the spiking neural network is specially used to process spiking data, and it is well suited for this type of event-based camera. In addition, because of the rapid development of neuromorphic hardware in recent years, it is possible to deploy SNN applications on edge-side system-on-chip. Therefore, based on the characteristics of dynamic vision sensors, this paper designs a spike encoding module and an SNN for processing sensor information. We use selective search to accomplish object tracking by classifying targets and backgrounds. The SNN can achieve 98.66% classification accuracy on our synthetic test dataset, and the tracking algorithm can achieve over 1000 fps after quantizing and compiling the network to the hardware simulator.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114576086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The conventional GaN channel HEMT will suffer the significant short channel effect and high-temperature degradation due to its weak channel confinement. Although the InGaN channel double-heterostructure HEMT (DH-HEMT) has been reported to address this issue well due to the strong quantum confinement, the efficiency of the InGaN channel lacks investigation. In this work, a high PAE performance of the InGaN channel heterostructure has been reported for the first time. The fabricated InGaN channel device with a gate length of 200-nm achieved a high fT/fmaxof 36.7 and 97 GHz, respectively. 3.6 GHz continuous-wave load-pull measurements gain a high power-added efficiency (PAE) of 59.4 %, and an associated output power density (Pout) of 2.14 W/mm at VDS= 20 V. It is the first time for the InGaN channel achieved so high PAE performance, the results presented here are benchmarked against the state-of-the-art (SOA) InGaN channel. This work illustrated that the InGaN channel with reasonable design can boost the 5G base-station applications.
{"title":"First Demonstration of High PAE Performance Using InGaN Channel HEMT for 5G RF Applications","authors":"Hao Lu, Likun Zhou, Longge Deng, Ling Yang, Bin Hou, Xiao-hua Ma, Yue Hao","doi":"10.1109/ICTA56932.2022.9962999","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962999","url":null,"abstract":"The conventional GaN channel HEMT will suffer the significant short channel effect and high-temperature degradation due to its weak channel confinement. Although the InGaN channel double-heterostructure HEMT (DH-HEMT) has been reported to address this issue well due to the strong quantum confinement, the efficiency of the InGaN channel lacks investigation. In this work, a high PAE performance of the InGaN channel heterostructure has been reported for the first time. The fabricated InGaN channel device with a gate length of 200-nm achieved a high fT/fmaxof 36.7 and 97 GHz, respectively. 3.6 GHz continuous-wave load-pull measurements gain a high power-added efficiency (PAE) of 59.4 %, and an associated output power density (Pout) of 2.14 W/mm at VDS= 20 V. It is the first time for the InGaN channel achieved so high PAE performance, the results presented here are benchmarked against the state-of-the-art (SOA) InGaN channel. This work illustrated that the InGaN channel with reasonable design can boost the 5G base-station applications.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115442738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963112
Weiyi Zhang, Liting Niu, Chaoyang Ding, Yiyang Wang, F. Farrukh, Chun Zhang
Simultaneous localization and mapping (SLAM) is an emerging robotic technology enabling autonomous robots to self-localize and map the surrounding environments. However, SLAM system is time and resource consuming, making it hard to implement on mobile devices. In this work, ROPY-SLAM, a novel heterogeneous framework for SLAM is proposed to take advantage of various devices such as personal computer and FPGA. The proposed system reduces the execution time by 28.6% and resource utilization by at most 71.2%. Moreover, ROPY-SLAM supports more flexible hardware and software implementations, providing a solution for distributed calculation of robotic applications.
{"title":"ROPY-SLAM: a Heterogeneous CPU-FPGA System for Simultaneous Localization and Mapping","authors":"Weiyi Zhang, Liting Niu, Chaoyang Ding, Yiyang Wang, F. Farrukh, Chun Zhang","doi":"10.1109/ICTA56932.2022.9963112","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963112","url":null,"abstract":"Simultaneous localization and mapping (SLAM) is an emerging robotic technology enabling autonomous robots to self-localize and map the surrounding environments. However, SLAM system is time and resource consuming, making it hard to implement on mobile devices. In this work, ROPY-SLAM, a novel heterogeneous framework for SLAM is proposed to take advantage of various devices such as personal computer and FPGA. The proposed system reduces the execution time by 28.6% and resource utilization by at most 71.2%. Moreover, ROPY-SLAM supports more flexible hardware and software implementations, providing a solution for distributed calculation of robotic applications.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129514940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963040
Haitao He, Changhao Luo, Junchen Dong, Yudi Zhao, Min Miao, Kai Zhao
The S parameter amplitude, latency, resistance, and inductance of TSV-RDL structures with the presence of five kinds of defects are simulated as feature vectors for defect detection and classification. Three nondestructive defect classification schemes for the TSV-RDL structure in advanced packaging are evaluated. Feedforward neural network with rectified linear unit activation function for the backpropagation algorithm is superior for defect classification and may play an important role in design for test and build-in self-repair circuit design.
{"title":"TSV Defects Classification with Machine Learning Approaches","authors":"Haitao He, Changhao Luo, Junchen Dong, Yudi Zhao, Min Miao, Kai Zhao","doi":"10.1109/ICTA56932.2022.9963040","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963040","url":null,"abstract":"The S parameter amplitude, latency, resistance, and inductance of TSV-RDL structures with the presence of five kinds of defects are simulated as feature vectors for defect detection and classification. Three nondestructive defect classification schemes for the TSV-RDL structure in advanced packaging are evaluated. Feedforward neural network with rectified linear unit activation function for the backpropagation algorithm is superior for defect classification and may play an important role in design for test and build-in self-repair circuit design.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129436401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963034
Kaikai Wu, Hongyi Wang, Shucai Wang
For reducing the impact of large voltage difference between batteries in battery packs, a battery cell balancing algorithm is proposed in this paper. Based on the 0.18 µm process, the algorithm has been integrated into a 7-cell lithium battery charge and discharge protection chip. The test results show that the algorithm can reliably reduce the voltage difference between batteries and help to prolong the service life of battery packs.
{"title":"A passive balancing algorithm for multi-cells","authors":"Kaikai Wu, Hongyi Wang, Shucai Wang","doi":"10.1109/ICTA56932.2022.9963034","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963034","url":null,"abstract":"For reducing the impact of large voltage difference between batteries in battery packs, a battery cell balancing algorithm is proposed in this paper. Based on the 0.18 µm process, the algorithm has been integrated into a 7-cell lithium battery charge and discharge protection chip. The test results show that the algorithm can reliably reduce the voltage difference between batteries and help to prolong the service life of battery packs.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122334480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-28DOI: 10.1109/ICTA56932.2022.9963066
Binwei Yang, Renwei Chen, Chenchang Zhan
This paper presents an ultra-low quiescent current bandgap reference (BGR) with current loading capability. Based on sharing an error amplifier (EA) between the BGR core and the power transistor driving circuit, the maximum load current of the BGR is extended to 5mA without relying on an output buffer. The BGR uses a dual-clamping structure to achieve low temperature coefficient (TC) and improved DC regulation. The proposed BGR is designed in a standard 0.18-µm CMOS process. Measurement results show that the input voltage range is 1.68V -2V while the output voltage is 1.19V. The quiescent current is 210nA with a maximum load current of 5mA. In the temperature range of - 40°C to 125°C, the TC of the output voltage is 9.7ppm/ °C and 30. 76ppm/ °C at the light and heavy loads, respectively. Good line and load regulations are also achieved.
{"title":"A 210nA Quiescent Current Bandgap Reference with 5mA Load Capability Using Shared Error Amplifier","authors":"Binwei Yang, Renwei Chen, Chenchang Zhan","doi":"10.1109/ICTA56932.2022.9963066","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963066","url":null,"abstract":"This paper presents an ultra-low quiescent current bandgap reference (BGR) with current loading capability. Based on sharing an error amplifier (EA) between the BGR core and the power transistor driving circuit, the maximum load current of the BGR is extended to 5mA without relying on an output buffer. The BGR uses a dual-clamping structure to achieve low temperature coefficient (TC) and improved DC regulation. The proposed BGR is designed in a standard 0.18-µm CMOS process. Measurement results show that the input voltage range is 1.68V -2V while the output voltage is 1.19V. The quiescent current is 210nA with a maximum load current of 5mA. In the temperature range of - 40°C to 125°C, the TC of the output voltage is 9.7ppm/ °C and 30. 76ppm/ °C at the light and heavy loads, respectively. Good line and load regulations are also achieved.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122671594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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