In this work, the performance of polysilicon TFTs has been improved for the first time by introduction of a thin polycrystalline silicon-germanium alloy layer sandwiched between thin polysilicon films in the channel of the TFTs. The bandgap discontinuity in the valence band between polysilicon and SiGe confines holes in the middle of the channel away from the high defect-density polysilicon-oxide interface. From the process point of view, it is better to have a sandwich layer than having SiGe along the entire depth of the channel because oxides on SiGe are known to be of bad quality.
{"title":"A novel Si/SiGe sandwich polysilicon TFT for SRAM applications","authors":"I. Manna, L. Jung, S. Banerjee","doi":"10.1109/DRC.1995.496309","DOIUrl":"https://doi.org/10.1109/DRC.1995.496309","url":null,"abstract":"In this work, the performance of polysilicon TFTs has been improved for the first time by introduction of a thin polycrystalline silicon-germanium alloy layer sandwiched between thin polysilicon films in the channel of the TFTs. The bandgap discontinuity in the valence band between polysilicon and SiGe confines holes in the middle of the channel away from the high defect-density polysilicon-oxide interface. From the process point of view, it is better to have a sandwich layer than having SiGe along the entire depth of the channel because oxides on SiGe are known to be of bad quality.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114580837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Simulates silicon-based FETs having a radically new architecture, one which could eventually permit scaling of overall device dimensions to 500A or less while simultaneously eliminating the large-area contacts and isolation required in conventional MOSFETs. This approach assumes that it will be possible to selectively pattern epitaxial films into the silicon substrate at nanometer resolution, and to subsequently overgrow these patterns with heterolayer structures. Selective epitaxial metallization of this type can potentially provide the basis for a wide variety of nanoscale devices in which transport occurs through appropriately designed heterolayers in the vertical (growth) direction under control of a gate electrode.
{"title":"A nanoscale vertical-tunneling FET","authors":"J. Tucker, C. Wang, T. Shen","doi":"10.1109/DRC.1995.496234","DOIUrl":"https://doi.org/10.1109/DRC.1995.496234","url":null,"abstract":"Simulates silicon-based FETs having a radically new architecture, one which could eventually permit scaling of overall device dimensions to 500A or less while simultaneously eliminating the large-area contacts and isolation required in conventional MOSFETs. This approach assumes that it will be possible to selectively pattern epitaxial films into the silicon substrate at nanometer resolution, and to subsequently overgrow these patterns with heterolayer structures. Selective epitaxial metallization of this type can potentially provide the basis for a wide variety of nanoscale devices in which transport occurs through appropriately designed heterolayers in the vertical (growth) direction under control of a gate electrode.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123017413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present experimental results of a threshold-shifting nano-memory. The observations are consistent with single electron storage in nano-crystals and offer possible evidence of Coulomb blockade at 77 K. The nano-memory consists of a silicon field-effect transistor with nano-crystals of silicon placed in the gate oxide in close proximity of the inversion surface. Electron charge is stored in these isolated 5-10 nm size nano-crystals which are separated from each other by >5 nm of SiO/sub 2/ and from the inversion layer on the substrate surface by sub-2 nm of SiO/sub 2/. Charge is injected from the inversion layer and its storage in the nano-crystals causes a shift in the threshold voltage which is sensed via current. The magnitude of this threshold shift is relatable to the charge in the nano-crystals, oxide thicknesses, and other device parameters. The uniqueness of this work is that this is the first memory utilizing single electron storage in a mainstream silicon technology which operates at low powers and yet does not sacrifice the drive current, reproducibility, and noise margin needs of a practical memory technology. It should also be possible to extend the concept to room temperature by utilizing the suspected Coulomb blockade behavior in nanocrystals of 3 nm size.
{"title":"A low power 77 K nano-memory with single electron nano-crystal storage","authors":"S. Tiwari, F. Rana, Wei Chen, K. Chan, H. Hanafi","doi":"10.1109/DRC.1995.496266","DOIUrl":"https://doi.org/10.1109/DRC.1995.496266","url":null,"abstract":"We present experimental results of a threshold-shifting nano-memory. The observations are consistent with single electron storage in nano-crystals and offer possible evidence of Coulomb blockade at 77 K. The nano-memory consists of a silicon field-effect transistor with nano-crystals of silicon placed in the gate oxide in close proximity of the inversion surface. Electron charge is stored in these isolated 5-10 nm size nano-crystals which are separated from each other by >5 nm of SiO/sub 2/ and from the inversion layer on the substrate surface by sub-2 nm of SiO/sub 2/. Charge is injected from the inversion layer and its storage in the nano-crystals causes a shift in the threshold voltage which is sensed via current. The magnitude of this threshold shift is relatable to the charge in the nano-crystals, oxide thicknesses, and other device parameters. The uniqueness of this work is that this is the first memory utilizing single electron storage in a mainstream silicon technology which operates at low powers and yet does not sacrifice the drive current, reproducibility, and noise margin needs of a practical memory technology. It should also be possible to extend the concept to room temperature by utilizing the suspected Coulomb blockade behavior in nanocrystals of 3 nm size.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130782245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. de la Houssaye, C.E. Chang, B. Offord, R. Johnson, P. Asbeck, G. Garcia, I. Lagnado
Reports MOSFETs with noise figures as low as 0.9 dB at 2 GHz, the lowest achieved to date with Si FETs. The devices were fabricated in thin-film silicon-on-sapphire, with gate lengths (defined by optical lithography) drawn at 0.5 /spl mu/m. The devices employed T-gate structures, with extra added aluminum to minimize gate resistance. The microwave gain was high: f/sub max/ values were as high as 52 GHz (near record performance) for nMOS and 32 GHz far pMOS transistors; f/sub t/ values were 17 GHz and 13 GHz for nMOS and pMOS respectively.
{"title":"Silicon MOSFETs with very low microwave noise","authors":"P. de la Houssaye, C.E. Chang, B. Offord, R. Johnson, P. Asbeck, G. Garcia, I. Lagnado","doi":"10.1109/DRC.1995.496231","DOIUrl":"https://doi.org/10.1109/DRC.1995.496231","url":null,"abstract":"Reports MOSFETs with noise figures as low as 0.9 dB at 2 GHz, the lowest achieved to date with Si FETs. The devices were fabricated in thin-film silicon-on-sapphire, with gate lengths (defined by optical lithography) drawn at 0.5 /spl mu/m. The devices employed T-gate structures, with extra added aluminum to minimize gate resistance. The microwave gain was high: f/sub max/ values were as high as 52 GHz (near record performance) for nMOS and 32 GHz far pMOS transistors; f/sub t/ values were 17 GHz and 13 GHz for nMOS and pMOS respectively.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115267708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Ida, S. Yamahata, K. Kurishima, H. Ito, T. Kobayashi, Y. Matsuoka
Summary form only given. A selectively-grown heavily-doped extrinsic-base structure is very effective for reducing the base resistance of heterojunction bipolar transistors (HBTs), and has been applied to AlGaAs/lnGaAs(GaAs) HBTs with GaAs extrinsic-base layers. For InGaAs layers, low growth temperatures (T/spl les/450/spl deg/C) are necessary for achieving a heavy p-type doping. However, low-temperature selective MOCVD of InGaAs was difficult, so good selectivity had been reported only at relatively high growth temperatures (T /spl ges/600/spl deg/C). We have demonstrated perfect selective growth of InGaAs layers at 400/spl deg/C with a high-speed rotation susceptor. In this paper, we report the first successful fabrication of an InP/InGaAs HBT with a selectively grown extrinsic base layer using this technique.
{"title":"High-f/sub max/ InP/InGaAs HBTs with extrinsic base layers selectively grown by MOCVD","authors":"M. Ida, S. Yamahata, K. Kurishima, H. Ito, T. Kobayashi, Y. Matsuoka","doi":"10.1109/DRC.1995.496278","DOIUrl":"https://doi.org/10.1109/DRC.1995.496278","url":null,"abstract":"Summary form only given. A selectively-grown heavily-doped extrinsic-base structure is very effective for reducing the base resistance of heterojunction bipolar transistors (HBTs), and has been applied to AlGaAs/lnGaAs(GaAs) HBTs with GaAs extrinsic-base layers. For InGaAs layers, low growth temperatures (T/spl les/450/spl deg/C) are necessary for achieving a heavy p-type doping. However, low-temperature selective MOCVD of InGaAs was difficult, so good selectivity had been reported only at relatively high growth temperatures (T /spl ges/600/spl deg/C). We have demonstrated perfect selective growth of InGaAs layers at 400/spl deg/C with a high-speed rotation susceptor. In this paper, we report the first successful fabrication of an InP/InGaAs HBT with a selectively grown extrinsic base layer using this technique.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116008728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Unlu, B. Goldberg, W. Herzog, H. Ghaemi, E. Towe
Reports mode structure and layer composition analysis of high power strained (In,Ga)As lasers using the super-resolution capabilities of near field scanning optical microscopy (NSOM). The lasers are designed to pump erbium doped fiber amplifiers in a configuration optimized for a single transverse laser mode. At high current levels, coupling efficiency decreases due to broadening of the spot size and the onset of multiple transverse modes. Sub-micron collection mode imaging and spectroscopic mapping of the emission mode structure as a function of laser pulse length and current easily identify a regime of operation where multiple transverse modes are observed. The evolution of multiple transverse modes coincides with a kink observed in the L-I curve. Near field microscopy enables the mode profile and spectral image to be correlated with the layer structure of the device with 100 nm resolution.
{"title":"Layer composition and mode structure analysis of heterojunction laser diodes by near field scanning optical microscopy","authors":"M. Unlu, B. Goldberg, W. Herzog, H. Ghaemi, E. Towe","doi":"10.1109/DRC.1995.496306","DOIUrl":"https://doi.org/10.1109/DRC.1995.496306","url":null,"abstract":"Reports mode structure and layer composition analysis of high power strained (In,Ga)As lasers using the super-resolution capabilities of near field scanning optical microscopy (NSOM). The lasers are designed to pump erbium doped fiber amplifiers in a configuration optimized for a single transverse laser mode. At high current levels, coupling efficiency decreases due to broadening of the spot size and the onset of multiple transverse modes. Sub-micron collection mode imaging and spectroscopic mapping of the emission mode structure as a function of laser pulse length and current easily identify a regime of operation where multiple transverse modes are observed. The evolution of multiple transverse modes coincides with a kink observed in the L-I curve. Near field microscopy enables the mode profile and spectral image to be correlated with the layer structure of the device with 100 nm resolution.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130817307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This abstract reports the latest results of our ongoing effort on GaAs/AlGaAs traveling wave Mach-Zehnder electrooptic modulators. Previously we reported >40 GHz electrical bandwidths but with rather large on/off voltage V/sub /spl pi//. By introducing a completely different electrode design we have reduced the V/sub /spl pi// from 28 V to 10 V while keeping the measured bandwidth >40 GHz. Furthermore the new design reduces the microwave loss, which determines the bandwidth, from 4.6 to 3.2 dB/cm at 35 GHz. Additionally, this new electrode geometry has the potential for further V/sub /spl pi// reduction while maintaining low loss.
{"title":"GaAs/AlGaAs electrooptic modulator with novel electrodes and bandwidth in excess of 40 GHz","authors":"R. Spickermann, S. Sakamoto, M. Peters, N. Dagli","doi":"10.1109/DRC.1995.496276","DOIUrl":"https://doi.org/10.1109/DRC.1995.496276","url":null,"abstract":"This abstract reports the latest results of our ongoing effort on GaAs/AlGaAs traveling wave Mach-Zehnder electrooptic modulators. Previously we reported >40 GHz electrical bandwidths but with rather large on/off voltage V/sub /spl pi//. By introducing a completely different electrode design we have reduced the V/sub /spl pi// from 28 V to 10 V while keeping the measured bandwidth >40 GHz. Furthermore the new design reduces the microwave loss, which determines the bandwidth, from 4.6 to 3.2 dB/cm at 35 GHz. Additionally, this new electrode geometry has the potential for further V/sub /spl pi// reduction while maintaining low loss.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129764989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Integrated silicon sensors have emerged over the past few years to extend microelectronics into important new areas, including health care, automotive systems, industrial process control (including semiconductor manufacturing), and environmental monitoring. Increasingly, such devices combine sensors, actuators, and microelectronics on single chips to form integrated microsystems, and the resulting devices are beginning to show the steady improvements in performance that have characterized integrated circuits in the past. The present and future device and technology challenges offered by integrated sensors are highlighted in this paper.
{"title":"Device and technology challenges for integrated sensors","authors":"K. Wise","doi":"10.1109/DRC.1995.496225","DOIUrl":"https://doi.org/10.1109/DRC.1995.496225","url":null,"abstract":"Integrated silicon sensors have emerged over the past few years to extend microelectronics into important new areas, including health care, automotive systems, industrial process control (including semiconductor manufacturing), and environmental monitoring. Increasingly, such devices combine sensors, actuators, and microelectronics on single chips to form integrated microsystems, and the resulting devices are beginning to show the steady improvements in performance that have characterized integrated circuits in the past. The present and future device and technology challenges offered by integrated sensors are highlighted in this paper.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123403971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We report the integration of an AlGaAs/GaAs two dimensional electron gas (2DEG) bolometric mixer and a quartz based microstrip circuit using the epitaxial lift-off (ELO) technique. The predicted potential performance of the 2DEG mixer at about 1 THz is T/sub M,DSB//spl ap/2,000K, which is competitive with the best data for Schottky diode mixers. The 2DEG mixer fabrication procedure demonstrated here is advantageous for its simplicity and uncritical choice of substrate. The active area dimensions are large (tens of pm) and uncritical, while integrated Schottky fabrication requires much more stringent consideration of size and parasitic effects.
{"title":"Monolithic integration of a 94 GHz AlGaAs/GaAs 2DEG mixer on quartz substrate by epitaxial lift-off","authors":"R. Basco, A. Prabhu, S. Yngvesson, K. Lau","doi":"10.1109/DRC.1995.496240","DOIUrl":"https://doi.org/10.1109/DRC.1995.496240","url":null,"abstract":"We report the integration of an AlGaAs/GaAs two dimensional electron gas (2DEG) bolometric mixer and a quartz based microstrip circuit using the epitaxial lift-off (ELO) technique. The predicted potential performance of the 2DEG mixer at about 1 THz is T/sub M,DSB//spl ap/2,000K, which is competitive with the best data for Schottky diode mixers. The 2DEG mixer fabrication procedure demonstrated here is advantageous for its simplicity and uncritical choice of substrate. The active area dimensions are large (tens of pm) and uncritical, while integrated Schottky fabrication requires much more stringent consideration of size and parasitic effects.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114406561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Matsumoto, M. Ishii, K. Segawa, Y. Oka, B. J. Vartanian, J. Harris
A single electron transistor (SET) operating at room temperature was fabricated for the first time using a scanning tunneling microscope (STM) nano-oxidation process. A clear Coulomb staircase with an /spl sim/140 mV period and Coulomb oscillation period of /spl sim/460 mV were observed at 300K.
{"title":"Room temperature operation of single electron transistor made by STM nano-oxidation process","authors":"K. Matsumoto, M. Ishii, K. Segawa, Y. Oka, B. J. Vartanian, J. Harris","doi":"10.1109/DRC.1995.496264","DOIUrl":"https://doi.org/10.1109/DRC.1995.496264","url":null,"abstract":"A single electron transistor (SET) operating at room temperature was fabricated for the first time using a scanning tunneling microscope (STM) nano-oxidation process. A clear Coulomb staircase with an /spl sim/140 mV period and Coulomb oscillation period of /spl sim/460 mV were observed at 300K.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132165625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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