Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269360
B. Doris, M. Ieong, T. Zhu, Y. Zhang, M. Steen, W. Natzle, S. Callegari, V. Narayanan, J. Cai, S. Ku, P. Jamison, Y. Li, Z. Ren, V. Ku, T. Boyd, T. Kanarsky, C. D'Emic, M. Newport, D. Dobuzinsky, S. Deshpande, J. Petrus, R. Jammy, W. Haensch
The ultra-thin SOI (UTSOI) device is an attractive choice for sub-10 nm gate-length scaling. In this work the major issues for UTSOI are addressed. External resistance is minimized by using the raised extension (REX) process flow which features an offset spacer to minimize the region of UTSOI outside the channel. The REX process scheme is used to demonstrate improved pFET performance and also to demonstrate the first planar single gate nFET with 8 nm gate-length. High temperature mobility measurements show that the channel thickness can be scaled further than previously predicted. UTSOI devices with tungsten gates and HfO/sub 2/ gate dielectrics having appropriate threshold voltages are presented for the first time.
{"title":"Device design considerations for ultra-thin SOI MOSFETs","authors":"B. Doris, M. Ieong, T. Zhu, Y. Zhang, M. Steen, W. Natzle, S. Callegari, V. Narayanan, J. Cai, S. Ku, P. Jamison, Y. Li, Z. Ren, V. Ku, T. Boyd, T. Kanarsky, C. D'Emic, M. Newport, D. Dobuzinsky, S. Deshpande, J. Petrus, R. Jammy, W. Haensch","doi":"10.1109/IEDM.2003.1269360","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269360","url":null,"abstract":"The ultra-thin SOI (UTSOI) device is an attractive choice for sub-10 nm gate-length scaling. In this work the major issues for UTSOI are addressed. External resistance is minimized by using the raised extension (REX) process flow which features an offset spacer to minimize the region of UTSOI outside the channel. The REX process scheme is used to demonstrate improved pFET performance and also to demonstrate the first planar single gate nFET with 8 nm gate-length. High temperature mobility measurements show that the channel thickness can be scaled further than previously predicted. UTSOI devices with tungsten gates and HfO/sub 2/ gate dielectrics having appropriate threshold voltages are presented for the first time.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123796318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269309
D. Lee, B. Lee, I.S. Jung, T. Kim, Y. Son, Sun-Ghil Lee, Young-pil Kim, Siyoung Choi, U. Chung, J. Moon
For the first time, a highly manufacturable fin-channel array transistor (FCAT) on a bulk Si substrate has been successfully integrated in a 512 M density DRAM with sub-70nm technology. The FCAT shows an excellent short channel behavior, such as extremely low subthreshold swing (SS) (/spl sim/75mV/dec) and DIBL (/spl sim/13mV/V), and a high cell transistor drive current with remarkably low subthreshold leakage current (/spl sim/0.2fA/cell).
{"title":"Fin-channel-array transistor (FCAT) featuring sub-70nm low power and high performance DRAM","authors":"D. Lee, B. Lee, I.S. Jung, T. Kim, Y. Son, Sun-Ghil Lee, Young-pil Kim, Siyoung Choi, U. Chung, J. Moon","doi":"10.1109/IEDM.2003.1269309","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269309","url":null,"abstract":"For the first time, a highly manufacturable fin-channel array transistor (FCAT) on a bulk Si substrate has been successfully integrated in a 512 M density DRAM with sub-70nm technology. The FCAT shows an excellent short channel behavior, such as extremely low subthreshold swing (SS) (/spl sim/75mV/dec) and DIBL (/spl sim/13mV/V), and a high cell transistor drive current with remarkably low subthreshold leakage current (/spl sim/0.2fA/cell).","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"5 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114093500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269201
L. Larcher, P. Pavan
A new statistical model of stress-induced leakage current (SILC) is implemented and used to predict data retention and program disturbs of state-of-the-art flash memories, and to correlate oxide characterization outputs (density, cross section, energy level of defects) to flash memory reliability. Physical mechanisms inducing the largest threshold voltage (V/sub T/) degradation are explained, and tunnel oxide scaling effects on flash reliability are predicted.
{"title":"Statistical simulations to inspect and predict data retention and program disturbs in flash memories","authors":"L. Larcher, P. Pavan","doi":"10.1109/IEDM.2003.1269201","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269201","url":null,"abstract":"A new statistical model of stress-induced leakage current (SILC) is implemented and used to predict data retention and program disturbs of state-of-the-art flash memories, and to correlate oxide characterization outputs (density, cross section, energy level of defects) to flash memory reliability. Physical mechanisms inducing the largest threshold voltage (V/sub T/) degradation are explained, and tunnel oxide scaling effects on flash reliability are predicted.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"481 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114016176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269329
A. Shima, H. Ashihara, T. Mine, Y. Goto, M. Horiuchi, Y. Wang, S. Talwar, A. Hiraiwa
We have developed a novel LTP (laser thermal process) that dramatically enhances the laser exposure window by controlling the heating process in a self-limiting way (SL-LTP). The Vth roll-offs of MOSFETs formed by this method were remarkably improved compared to those by RTA when offset-spacer and halo-implantation processes were not applied. Its effectiveness was also verified in 50-nm gate CMOS devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit.
{"title":"Self-limiting laser thermal process for ultra-shallow junction formation of 50-nm gate CMOS","authors":"A. Shima, H. Ashihara, T. Mine, Y. Goto, M. Horiuchi, Y. Wang, S. Talwar, A. Hiraiwa","doi":"10.1109/IEDM.2003.1269329","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269329","url":null,"abstract":"We have developed a novel LTP (laser thermal process) that dramatically enhances the laser exposure window by controlling the heating process in a self-limiting way (SL-LTP). The Vth roll-offs of MOSFETs formed by this method were remarkably improved compared to those by RTA when offset-spacer and halo-implantation processes were not applied. Its effectiveness was also verified in 50-nm gate CMOS devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128100523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269436
Yuan Xie, Sheng-Shian Li, Yu-Wei Lin, Z. Ren, C. Nguyen
Vibrating polysilicon micromechanical ring resonators, utilizing a unique extensional wine-glass mode shape to achieve lower impedance than previous UHF resonators, have been demonstrated at frequencies as high as 1.2-GHz with a Q of 3,700, and 1.47-GHz (highest to date) with a Q of 2,300. The 1.2-GHz resonator exhibits a measured motional resistance of 560 k/spl Omega/ with a dc-bias voltage of 20 V, which is 6/spl times/ lower than measured on radial contour mode disk counterparts at the same frequency, and which can be driven down as low as 2 k/spl Omega/ when a dc-bias voltage of 100 V and electrode-to-resonator gap spacing of 460 /spl Aring/ are used. The above high Q and low impedance advantages, together with the multiple frequency, on-chip integration advantages afforded by electrostatically-transduced /spl mu/mechanical resonators, make this device an attractive candidate for use in the front-end RF filtering and oscillator functions needed by wireless communication devices.
{"title":"UHF micromechanical extensional wine-glass mode ring resonators","authors":"Yuan Xie, Sheng-Shian Li, Yu-Wei Lin, Z. Ren, C. Nguyen","doi":"10.1109/IEDM.2003.1269436","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269436","url":null,"abstract":"Vibrating polysilicon micromechanical ring resonators, utilizing a unique extensional wine-glass mode shape to achieve lower impedance than previous UHF resonators, have been demonstrated at frequencies as high as 1.2-GHz with a Q of 3,700, and 1.47-GHz (highest to date) with a Q of 2,300. The 1.2-GHz resonator exhibits a measured motional resistance of 560 k/spl Omega/ with a dc-bias voltage of 20 V, which is 6/spl times/ lower than measured on radial contour mode disk counterparts at the same frequency, and which can be driven down as low as 2 k/spl Omega/ when a dc-bias voltage of 100 V and electrode-to-resonator gap spacing of 460 /spl Aring/ are used. The above high Q and low impedance advantages, together with the multiple frequency, on-chip integration advantages afforded by electrostatically-transduced /spl mu/mechanical resonators, make this device an attractive candidate for use in the front-end RF filtering and oscillator functions needed by wireless communication devices.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134371908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269169
C. Ge, C.C. Lin, C. Ko, C.C. Huang, Y. Huang, B. Chan, B.-C. Perng, C. Sheu, Pang-Yen Tsai, L. Yao, C.-L. Wu, T. Lee, C. Chen, C. Wang, S.C. Lin, Y. Yeo, C. Hu
We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, silicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.
{"title":"Process-strained Si (PSS) CMOS technology featuring 3D strain engineering","authors":"C. Ge, C.C. Lin, C. Ko, C.C. Huang, Y. Huang, B. Chan, B.-C. Perng, C. Sheu, Pang-Yen Tsai, L. Yao, C.-L. Wu, T. Lee, C. Chen, C. Wang, S.C. Lin, Y. Yeo, C. Hu","doi":"10.1109/IEDM.2003.1269169","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269169","url":null,"abstract":"We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, silicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131574640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269377
S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. Tringe, Y. Leblebici, M. Declercq, K. Banerjee, A. Ionescu
We have proposed and validated a true hybrid SET/CMOS device, called SETMOS, that is able to extend the Coulomb blockade oscillations of a SET transistor into the /spl mu/A current range, corresponding to near sub-threshold operation region of a nanometer-scale MOSFET. New nano-scale analog applications, working at sub-ambient temperatures (-150/spl deg/C up to 100/spl deg/C), including a novel NDR circuit, amplifiers, and even NEMS-SETMOS circuit cells are uniquely supported by SETMOS.
{"title":"SETMOS: a novel true hybrid SET-CMOS high current Coulomb blockade oscillation cell for future nano-scale analog ICs","authors":"S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. Tringe, Y. Leblebici, M. Declercq, K. Banerjee, A. Ionescu","doi":"10.1109/IEDM.2003.1269377","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269377","url":null,"abstract":"We have proposed and validated a true hybrid SET/CMOS device, called SETMOS, that is able to extend the Coulomb blockade oscillations of a SET transistor into the /spl mu/A current range, corresponding to near sub-threshold operation region of a nanometer-scale MOSFET. New nano-scale analog applications, working at sub-ambient temperatures (-150/spl deg/C up to 100/spl deg/C), including a novel NDR circuit, amplifiers, and even NEMS-SETMOS circuit cells are uniquely supported by SETMOS.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"87 26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131226917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269209
Chendong Zhu, Q. Liang, R. Al-Huq, J. Cressler, A. Joseph, J. Johansen, Tianbing Chen, G. Niu, G. Freeman, J. Rieh, D. Ahlgren
A robust, time-dependent stress methodology for investigating "mixed-mode" (simultaneous high J/sub C/ and high V/sub CB/) reliability degradation in advanced SiGe HBTs is introduced. We present comprehensive stress data on scaled 120 GHz SiGe HBTs, and use specially designed test structures with variable emitter-to-shallow trench spacing to shed light on the resultant damage mechanisms. We also employ calibrated MEDICI simulations using the hot carrier injection current technique to better understand the damage mechanisms, and conclude by assessing the impact of mixed-mode stress in aggressively scaled 200 GHz SiGe HBTs.
{"title":"An investigation of the damage mechanisms in impact ionization-induced \"mixed-mode\" reliability stressing of scaled SiGe HBTs","authors":"Chendong Zhu, Q. Liang, R. Al-Huq, J. Cressler, A. Joseph, J. Johansen, Tianbing Chen, G. Niu, G. Freeman, J. Rieh, D. Ahlgren","doi":"10.1109/IEDM.2003.1269209","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269209","url":null,"abstract":"A robust, time-dependent stress methodology for investigating \"mixed-mode\" (simultaneous high J/sub C/ and high V/sub CB/) reliability degradation in advanced SiGe HBTs is introduced. We present comprehensive stress data on scaled 120 GHz SiGe HBTs, and use specially designed test structures with variable emitter-to-shallow trench spacing to shed light on the resultant damage mechanisms. We also employ calibrated MEDICI simulations using the hot carrier injection current technique to better understand the damage mechanisms, and conclude by assessing the impact of mixed-mode stress in aggressively scaled 200 GHz SiGe HBTs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133049281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269395
G. Upadhya, P. Zhou, K. Goodson, M. Munch, T. Kenny
Recent trends for next generation microprocessors clearly point to significant increase in power consumption, heat density, and to corresponding challenges in thermal management. In desktop systems, the trend is to minimize system enclosure size while maximizing performance, which in turn leads to high power densities. The thermal management technologies used today consist of advanced heat sink designs and heat pipe designs with forced air cooling. However, these techniques are approaching fundamental limits for high heat flux, and there is a growing need for development of more efficient and scalable cooling systems. To this end, a new closed loop liquid cooling system has been developed to handle heat fluxes greater than 500 W/sq cm. The cooling system comprises a micro channel heat exchanger for high heat flux removal, an electro-kinetic pump for delivering fluid with required flow rate and pressure, and a counterflow heat rejector to dissipate heat to the ambient. The thermal performance of such a system was analyzed with ICEPAK. Experimental work was carried out to validate the modeling results and evaluate performance for a high end computer system cooling application.
{"title":"Closed-loop cooling technologies for microprocessors","authors":"G. Upadhya, P. Zhou, K. Goodson, M. Munch, T. Kenny","doi":"10.1109/IEDM.2003.1269395","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269395","url":null,"abstract":"Recent trends for next generation microprocessors clearly point to significant increase in power consumption, heat density, and to corresponding challenges in thermal management. In desktop systems, the trend is to minimize system enclosure size while maximizing performance, which in turn leads to high power densities. The thermal management technologies used today consist of advanced heat sink designs and heat pipe designs with forced air cooling. However, these techniques are approaching fundamental limits for high heat flux, and there is a growing need for development of more efficient and scalable cooling systems. To this end, a new closed loop liquid cooling system has been developed to handle heat fluxes greater than 500 W/sq cm. The cooling system comprises a micro channel heat exchanger for high heat flux removal, an electro-kinetic pump for delivering fluid with required flow rate and pressure, and a counterflow heat rejector to dissipate heat to the ambient. The thermal performance of such a system was analyzed with ICEPAK. Experimental work was carried out to validate the modeling results and evaluate performance for a high end computer system cooling application.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124240352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269430
W. Loh, B. Cho, M. Joo, M. Li, D. Chan, S. Mathew, D. Kwong
Using the carrier separation measurement technique, we are able to distinguish two different breakdown mechanisms: a high-k bulk initiated, and an interfacial layer initiated. The results correlate with the statistical Weibull distribution showing a polarity dependent breakdown in high-k stacks. A model of charge trapping at different spatial locations in HfAlO/sub x/ with a TaN gate structure is proposed to explain the polarity dependence of charge trapping characteristics and breakdown mechanisms.
{"title":"Analysis of charge trapping and breakdown mechanism in high-k dielectrics with metal gate electrode using carrier separation","authors":"W. Loh, B. Cho, M. Joo, M. Li, D. Chan, S. Mathew, D. Kwong","doi":"10.1109/IEDM.2003.1269430","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269430","url":null,"abstract":"Using the carrier separation measurement technique, we are able to distinguish two different breakdown mechanisms: a high-k bulk initiated, and an interfacial layer initiated. The results correlate with the statistical Weibull distribution showing a polarity dependent breakdown in high-k stacks. A model of charge trapping at different spatial locations in HfAlO/sub x/ with a TaN gate structure is proposed to explain the polarity dependence of charge trapping characteristics and breakdown mechanisms.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124350926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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