Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269154
W. Weber, C. Braun, R. Glaser, Y. Gsottberger, M. Halik, S. Jung, H. Klauk, C. Lauterbach, G. Schmid, X. Shi, T. Sturm, G. Stromberg, U. Zschieschang
In this paper, applications are discussed that describe achievements along the road towards 'Ambient Intelligence'. Appliances and devices disappear into the environment of the individual; instead services come into focus. Key to this development are system solutions that lead to a significant improvement of the human-machine interface. Along this line, we present important technologies and key system components ranging from low-cost electronic technologies and systems, to ubiquitous sensor networks and electronics in smart textiles. In conclusion, this presentation relates the semiconductor technology roadmap to a future world in which electronics meets human needs in a pervasive, intuitive and beneficial way.
{"title":"Ambient intelligence - key technologies in the information age","authors":"W. Weber, C. Braun, R. Glaser, Y. Gsottberger, M. Halik, S. Jung, H. Klauk, C. Lauterbach, G. Schmid, X. Shi, T. Sturm, G. Stromberg, U. Zschieschang","doi":"10.1109/IEDM.2003.1269154","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269154","url":null,"abstract":"In this paper, applications are discussed that describe achievements along the road towards 'Ambient Intelligence'. Appliances and devices disappear into the environment of the individual; instead services come into focus. Key to this development are system solutions that lead to a significant improvement of the human-machine interface. Along this line, we present important technologies and key system components ranging from low-cost electronic technologies and systems, to ubiquitous sensor networks and electronics in smart textiles. In conclusion, this presentation relates the semiconductor technology roadmap to a future world in which electronics meets human needs in a pervasive, intuitive and beneficial way.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128539420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269392
P. Vettiger, T. Albrecht, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, D. Jubin, W. Haberle, M. Lantz, H. Rothuizen, R. Stutz, D. Wiesmann, G. Binnig, P. Bachtold, G. Cherubini, C. Hagleitner, T. Loeliger, A. Pantazi, H. Pozidis, E. Eleftheriou
Ultrahigh storage densities of up to 1 Tb/in./sup 2/ or more can be achieved by using local-probe techniques to write, read back, and erase data in very thin polymer films. The thermomechanical scanning-probe-based data-storage concept, internally dubbed "millipede", combines ultrahigh density, small form factor, and high data rates. High data rates are achieved by parallel operation of large 2D arrays with thousands micro/nanomechanical cantilevers/tips that can be batch-fabricated by silicon surface-micromachining techniques. The inherent parallelism, the ultrahigh areal densities and the small form factor may open up new perspectives and opportunities for application in areas beyond those envisaged today.
{"title":"Thousands of microcantilevers for highly parallel and ultra-dense data storage","authors":"P. Vettiger, T. Albrecht, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, D. Jubin, W. Haberle, M. Lantz, H. Rothuizen, R. Stutz, D. Wiesmann, G. Binnig, P. Bachtold, G. Cherubini, C. Hagleitner, T. Loeliger, A. Pantazi, H. Pozidis, E. Eleftheriou","doi":"10.1109/IEDM.2003.1269392","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269392","url":null,"abstract":"Ultrahigh storage densities of up to 1 Tb/in./sup 2/ or more can be achieved by using local-probe techniques to write, read back, and erase data in very thin polymer films. The thermomechanical scanning-probe-based data-storage concept, internally dubbed \"millipede\", combines ultrahigh density, small form factor, and high data rates. High data rates are achieved by parallel operation of large 2D arrays with thousands micro/nanomechanical cantilevers/tips that can be batch-fabricated by silicon surface-micromachining techniques. The inherent parallelism, the ultrahigh areal densities and the small form factor may open up new perspectives and opportunities for application in areas beyond those envisaged today.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117034433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269441
A. Vandooren, Aaron Thean, Y. Du, I. To, J. Hughes, Tab A. Stephens, M. Huang, S. Egley, M. Zavala, K. Sphabmixay, A. Barr, T. White, S. Samavedam, Leo Mathew, J. Schaeffer, D. Triyoso, M. Rossow, D. Roan, Daniel T. Pham, Raj Rai, Bich-Yen Nguyen, B. E. White, Marius K. Orlowski, A. Duvallet, Thuy B. Dao, J. Mogab
We report for the first time, the digital and analog performance of sub-100nm Fully-Depleted Silicon-On-Insulator (SOI) n and p-MOSFETs using TaSiN gate and HfO/sub 2/ dielectric with elevated Source/Drain (SD) extensions. As CMOS technology continues to scale down, the FDSOI technology offers a potential solution to control short channel effects by reducing the silicon film thickness and a concurrent scaling of the buried oxide thickness. The use of metal gate and thin undoped body offer the additional advantages of 1) suppression of polysilicon depletion effects, 2) elimination of boron penetration, 3) minimizing S/D junction capacitance (Cj), and 4) enhancing transistor matching performance for mixed signal application. High k dielectric is necessary to reduce gate leakage for EOT below 15 to 20/spl Aring/. The intrinsic low-leakage nature of the FDSOI device and it's immunity to floating body effect provides much opportunity for ultra-low power digital and analog applications. Physical and electrical analyses of the devices are presented to provide an assessment of the metal gates on high K gate dielectric in combination with fully-depleted device operation in the context of digital and analog circuits.
{"title":"Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions","authors":"A. Vandooren, Aaron Thean, Y. Du, I. To, J. Hughes, Tab A. Stephens, M. Huang, S. Egley, M. Zavala, K. Sphabmixay, A. Barr, T. White, S. Samavedam, Leo Mathew, J. Schaeffer, D. Triyoso, M. Rossow, D. Roan, Daniel T. Pham, Raj Rai, Bich-Yen Nguyen, B. E. White, Marius K. Orlowski, A. Duvallet, Thuy B. Dao, J. Mogab","doi":"10.1109/IEDM.2003.1269441","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269441","url":null,"abstract":"We report for the first time, the digital and analog performance of sub-100nm Fully-Depleted Silicon-On-Insulator (SOI) n and p-MOSFETs using TaSiN gate and HfO/sub 2/ dielectric with elevated Source/Drain (SD) extensions. As CMOS technology continues to scale down, the FDSOI technology offers a potential solution to control short channel effects by reducing the silicon film thickness and a concurrent scaling of the buried oxide thickness. The use of metal gate and thin undoped body offer the additional advantages of 1) suppression of polysilicon depletion effects, 2) elimination of boron penetration, 3) minimizing S/D junction capacitance (Cj), and 4) enhancing transistor matching performance for mixed signal application. High k dielectric is necessary to reduce gate leakage for EOT below 15 to 20/spl Aring/. The intrinsic low-leakage nature of the FDSOI device and it's immunity to floating body effect provides much opportunity for ultra-low power digital and analog applications. Physical and electrical analyses of the devices are presented to provide an assessment of the metal gates on high K gate dielectric in combination with fully-depleted device operation in the context of digital and analog circuits.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115388061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269294
S. Rangan, N. Mielke, E.C.C. Yeh
PMOSFETs experiencing negative bias temperature instability (NBTI) recover after stress is removed. We show for the first time that: (1) the recovery can reach 100% at 25/spl deg/C; (2) recovery has a universal behavior independent of stress voltage, stress time and temperature (below 25/spl deg/C); and (3) the recovered devices degrade at the same rate when re-stressed, indicating that recovery resets the degraded device to its original state. We propose a three step model to describe this mechanism: (i) voltage accelerated degradation, (ii) bias and degradation independent recovery and (iii) temperature driven "lock-in" step. We believe that the competing effects of these three steps corrupt common field/temperature acceleration models for NBTI.
{"title":"Universal recovery behavior of negative bias temperature instability [PMOSFETs]","authors":"S. Rangan, N. Mielke, E.C.C. Yeh","doi":"10.1109/IEDM.2003.1269294","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269294","url":null,"abstract":"PMOSFETs experiencing negative bias temperature instability (NBTI) recover after stress is removed. We show for the first time that: (1) the recovery can reach 100% at 25/spl deg/C; (2) recovery has a universal behavior independent of stress voltage, stress time and temperature (below 25/spl deg/C); and (3) the recovered devices degrade at the same rate when re-stressed, indicating that recovery resets the degraded device to its original state. We propose a three step model to describe this mechanism: (i) voltage accelerated degradation, (ii) bias and degradation independent recovery and (iii) temperature driven \"lock-in\" step. We believe that the competing effects of these three steps corrupt common field/temperature acceleration models for NBTI.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115497367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269298
H. Brech, W. Brakensiek, D. Burdeaux, W. Burger, C. Dragon, G. Formicone, B. Pryor, D. Rice
Improved RF performance of Motorola's next generation HV6 high power RF-LDMOS transistor is demonstrated. In the 2.1 GHz band, with a two-carrier WCDMA signal, a 29% drain efficiency is achieved at -37 dBc IM3 and 20 W of output power, along with a high power gain of over 16.5 dB. To our knowledge, this is the highest combination of efficiency and linearity ever reported on a high power part of any technology or material system in that frequency band. A PAE of 62% at 100 W (P/sub 3dB/) is also achieved.
演示了摩托罗拉下一代HV6大功率RF- ldmos晶体管的射频性能改进。在2.1 GHz频段，使用双载波WCDMA信号，在-37 dBc IM3和20 W输出功率下实现29%的漏极效率，以及超过16.5 dB的高功率增益。据我们所知，这是在该频段内任何技术或材料系统的高功率部分报道的效率和线性度的最高组合。在100 W (P/sub 3dB/)下，PAE也达到62%。
{"title":"Record efficiency and gain at 2.1 GHz of high power RF transistors for cellular and 3G base stations","authors":"H. Brech, W. Brakensiek, D. Burdeaux, W. Burger, C. Dragon, G. Formicone, B. Pryor, D. Rice","doi":"10.1109/IEDM.2003.1269298","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269298","url":null,"abstract":"Improved RF performance of Motorola's next generation HV6 high power RF-LDMOS transistor is demonstrated. In the 2.1 GHz band, with a two-carrier WCDMA signal, a 29% drain efficiency is achieved at -37 dBc IM3 and 20 W of output power, along with a high power gain of over 16.5 dB. To our knowledge, this is the highest combination of efficiency and linearity ever reported on a high power part of any technology or material system in that frequency band. A PAE of 62% at 100 W (P/sub 3dB/) is also achieved.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114678256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269328
V. Venezia, R. Duffy, L. Pelaz, M. Aboy, A. Heringa, P. Griffin, C. Wang, M. Hopstaken, Y. Tamminga, T. Dao, B. Pawlak, F. Roozeboom
The time evolution of B, As, and In doping profiles during and after solid phase epitaxial regrowth (SPER) was monitored for conditions applicable to sub-65 nm CMOS technologies. As and In segregate during SPER by a sweep of the regrowing interface. In the case of B, significant B diffusion in a-Si occurs during SPER, while afterwards B uphill diffusion dominates. With the aid of atomistic simulation we have identified a temperature dependent time to maximum uphill B diffusion.
{"title":"Dopant redistribution effects in preamorphized silicon during low temperature annealing","authors":"V. Venezia, R. Duffy, L. Pelaz, M. Aboy, A. Heringa, P. Griffin, C. Wang, M. Hopstaken, Y. Tamminga, T. Dao, B. Pawlak, F. Roozeboom","doi":"10.1109/IEDM.2003.1269328","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269328","url":null,"abstract":"The time evolution of B, As, and In doping profiles during and after solid phase epitaxial regrowth (SPER) was monitored for conditions applicable to sub-65 nm CMOS technologies. As and In segregate during SPER by a sweep of the regrowing interface. In the case of B, significant B diffusion in a-Si occurs during SPER, while afterwards B uphill diffusion dominates. With the aid of atomistic simulation we have identified a temperature dependent time to maximum uphill B diffusion.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127560663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269446
H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M. Narihiro, K. Arai, Y. Ochiai, K. Takeuchi, Toyoji Yamamoto, T. Mogami
Sub-10-nm planar-bulk-CMOS devices were clearly demonstrated by a lateral source/drain (S/D) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SDE) and steep halo. Good cut-off characteristics were observed for n/pMOSFETs with the gate length of 5 nm at 0.4 V for the first time.
{"title":"Sub-10-nm planar-bulk-CMOS devices using lateral junction control","authors":"H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M. Narihiro, K. Arai, Y. Ochiai, K. Takeuchi, Toyoji Yamamoto, T. Mogami","doi":"10.1109/IEDM.2003.1269446","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269446","url":null,"abstract":"Sub-10-nm planar-bulk-CMOS devices were clearly demonstrated by a lateral source/drain (S/D) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SDE) and steep halo. Good cut-off characteristics were observed for n/pMOSFETs with the gate length of 5 nm at 0.4 V for the first time.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126909453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269421
K. Banerjee, Sheng-Chih Lin, A. Keshavarzi, S. Narendra, V. De
Accurate estimation of the silicon junction (or die) temperature in high-end microprocessors is crucial for various performance analyses and also for chip-level thermal management. This work introduces for the first time, the notion of self-consistency in estimating the die temperature for sub-100 nm CMOS technologies by taking into account various electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature. It also comprehends chip-level reliability constraints and the impact of employing various packaging and cooling solutions in an integrated manner. The self-consistent solutions of die temperature are shown to have significant implications for evaluating various power-performance-reliability-cooling cost tradeoffs and can be used to optimize the performance of nanoscale ICs.
{"title":"A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management","authors":"K. Banerjee, Sheng-Chih Lin, A. Keshavarzi, S. Narendra, V. De","doi":"10.1109/IEDM.2003.1269421","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269421","url":null,"abstract":"Accurate estimation of the silicon junction (or die) temperature in high-end microprocessors is crucial for various performance analyses and also for chip-level thermal management. This work introduces for the first time, the notion of self-consistency in estimating the die temperature for sub-100 nm CMOS technologies by taking into account various electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature. It also comprehends chip-level reliability constraints and the impact of employing various packaging and cooling solutions in an integrated manner. The self-consistent solutions of die temperature are shown to have significant implications for evaluating various power-performance-reliability-cooling cost tradeoffs and can be used to optimize the performance of nanoscale ICs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122017034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269284
C. Lieber
First, a general framework for the growth of single crystal nanowire building blocks is reviewed, with an emphasis on illustrating the level of control possible in defining composition, diameter, and electronic properties. Second, investigations of electrical transport properties of individual nanowires and nanowire heterostructures are discussed. Third, and as an example of a nanotechnology enabled application, we describe the use of nanowire field-effect devices as ultra-sensitive chemical and biological sensors. Finally, we describe studies of the fundamental optical and opto-electronic properties of compound semiconductor nanowires and nanowire heterostructures. In summary, challenges and goals for realizing nanotechnologies in the future are discussed, including schemes and progress towards highly integrated electronic and photonic systems.
{"title":"Nanowires as building blocks for nanoelectronics and nanophotonics","authors":"C. Lieber","doi":"10.1109/IEDM.2003.1269284","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269284","url":null,"abstract":"First, a general framework for the growth of single crystal nanowire building blocks is reviewed, with an emphasis on illustrating the level of control possible in defining composition, diameter, and electronic properties. Second, investigations of electrical transport properties of individual nanowires and nanowire heterostructures are discussed. Third, and as an example of a nanotechnology enabled application, we describe the use of nanowire field-effect devices as ultra-sensitive chemical and biological sensors. Finally, we describe studies of the fundamental optical and opto-electronic properties of compound semiconductor nanowires and nanowire heterostructures. In summary, challenges and goals for realizing nanotechnologies in the future are discussed, including schemes and progress towards highly integrated electronic and photonic systems.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121570693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269206
Yang-Kyu Choi, Daewon Ha, E. Snow, J. Bokor, T. King
Hot-carrier and oxide reliability of CMOS FinFETs with 2.1 nm-thick gate-SiO/sub 2/ were investigated. It was found that hot-carrier immunity improves as the fin width (body thickness) decreases, which facilitates gate-length scaling, while it is degraded at elevated temperature due to the self-heating effect. High values of Q/sub BD/ are achieved for devices with very small gate area. A post-fin-etch hydrogen anneal is helpful for improving hot-carrier immunity and Q/sub BD/.
{"title":"Reliability study of CMOS FinFETs","authors":"Yang-Kyu Choi, Daewon Ha, E. Snow, J. Bokor, T. King","doi":"10.1109/IEDM.2003.1269206","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269206","url":null,"abstract":"Hot-carrier and oxide reliability of CMOS FinFETs with 2.1 nm-thick gate-SiO/sub 2/ were investigated. It was found that hot-carrier immunity improves as the fin width (body thickness) decreases, which facilitates gate-length scaling, while it is degraded at elevated temperature due to the self-heating effect. High values of Q/sub BD/ are achieved for devices with very small gate area. A post-fin-etch hydrogen anneal is helpful for improving hot-carrier immunity and Q/sub BD/.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122620569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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