Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269414
N. Ohashi, K. Misawa, S. Sone, H.J. Shin, K. Inukai, E. Soda, S. Kondo, A. Furuya, H. Okamura, S. Ogawa, N. Kobayashi
Towards the 65 nm technology node, Cu interconnects using a high-modulus and low-temperature porous MSQ (methyl silsesquioxane, k=2.3) process has been developed. With an advantage of a lower k value, this process is fairly compatible with the 90 nm-node technology in terms of mechanical strength of low-k film, low thermal budget to suppress SIV (stress induced void) failures, and a use of conventional ArF resist mask process. Good electrical results were obtained for 300-mm-wafer Cu dual damascene interconnects using low-pressure CMP and advanced Cu-electroplating/barrier metal processes.
{"title":"Robust porous MSQ (k=2.3, e=12 GPa) for low-temperature (<350/spl deg/C) Cu/low-k integration using ArF resist mask process","authors":"N. Ohashi, K. Misawa, S. Sone, H.J. Shin, K. Inukai, E. Soda, S. Kondo, A. Furuya, H. Okamura, S. Ogawa, N. Kobayashi","doi":"10.1109/IEDM.2003.1269414","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269414","url":null,"abstract":"Towards the 65 nm technology node, Cu interconnects using a high-modulus and low-temperature porous MSQ (methyl silsesquioxane, k=2.3) process has been developed. With an advantage of a lower k value, this process is fairly compatible with the 90 nm-node technology in terms of mechanical strength of low-k film, low thermal budget to suppress SIV (stress induced void) failures, and a use of conventional ArF resist mask process. Good electrical results were obtained for 300-mm-wafer Cu dual damascene interconnects using low-pressure CMP and advanced Cu-electroplating/barrier metal processes.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114506035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269415
G. Gildenblat, X. Cai, T. Chen, X. Gu, H. Wang
This paper addresses current issues in compact MOSFET modeling, provides an overview and some essential details of SP (a new compact MOSFET model developed at Penn State), and presents original results concerning new applications of the symmetric linearization method and streamlined surface potential (/spl phi//sub s/) approximation.
{"title":"Reemergence of the surface-potential-based compact MOSFET models","authors":"G. Gildenblat, X. Cai, T. Chen, X. Gu, H. Wang","doi":"10.1109/IEDM.2003.1269415","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269415","url":null,"abstract":"This paper addresses current issues in compact MOSFET modeling, provides an overview and some essential details of SP (a new compact MOSFET model developed at Penn State), and presents original results concerning new applications of the symmetric linearization method and streamlined surface potential (/spl phi//sub s/) approximation.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114722964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269183
C. Anghel, N. Hefyene, Renaud Gillon, M. Tack, Michel Declercq, Adrian M. Ionescu
This work reports on the self-heating-effect (SHE) characterization of high-voltage (HV) DMOSFETs and a simple yet accurate extraction methodology of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/). Systematic pulsed-gate experiments are used to study the influence of pulse duration and duty factor on device SHE and optimal extraction conditions. It is found that in 100 V DMOSFETs, the SHE is cancelled by using pulses with duration shorter than 2 /spl mu/s and duty factors lower than 1:100. The new extraction method uses dedicated extraction plots exploiting the gradual canceling of SHE with pulse duration and a new analytical modeling including the temperature dependence of RTH, is validated. For the first time, we report on the temperature dependence of RTH, from 25/spl deg/C up to 150/spl deg/C, in both saturation and quasi-saturation regions of DMOS, which is shown to be a quasi-linear yet significant function of the device internal temperature. Moreover, another new result is a power low-dependent thermal capacitance, as suggested by our experiments. Finally, SPICE simulations are used to validate the proposed method, and, demonstrate that a thermal-dependent thermal resistance model is highly critical for accurate advanced simulation of HV DMOS ICs.
这项工作报告了高压(HV) dmosfet的自热效应(SHE)特性，以及该器件等效热阻抗(热阻R/sub TH/和电容C/sub TH/)的简单而准确的提取方法。通过系统的脉冲门实验，研究了脉冲持续时间和占空因子对器件SHE的影响以及最佳提取条件。研究发现，在100 V dmosfet中，使用持续时间小于2 /spl mu/s且占空比小于1:100的脉冲可以抵消SHE。新的提取方法利用了SHE随脉冲持续时间逐渐抵消的专用提取图，并验证了包含RTH温度依赖性的新的分析模型。我们首次报道了RTH的温度依赖性，从25/spl°C到150/spl°C，在DMOS的饱和和准饱和区域，这被证明是器件内部温度的准线性但重要的函数。此外，另一个新的结果是功率低依赖的热电容，正如我们的实验所表明的那样。最后，SPICE仿真验证了所提出的方法，并证明了热相关的热阻模型对于HV DMOS集成电路的精确高级仿真至关重要。
{"title":"New method for temperature-dependent thermal resistance and capacitance accurate extraction in high-voltage DMOS transistors","authors":"C. Anghel, N. Hefyene, Renaud Gillon, M. Tack, Michel Declercq, Adrian M. Ionescu","doi":"10.1109/IEDM.2003.1269183","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269183","url":null,"abstract":"This work reports on the self-heating-effect (SHE) characterization of high-voltage (HV) DMOSFETs and a simple yet accurate extraction methodology of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/). Systematic pulsed-gate experiments are used to study the influence of pulse duration and duty factor on device SHE and optimal extraction conditions. It is found that in 100 V DMOSFETs, the SHE is cancelled by using pulses with duration shorter than 2 /spl mu/s and duty factors lower than 1:100. The new extraction method uses dedicated extraction plots exploiting the gradual canceling of SHE with pulse duration and a new analytical modeling including the temperature dependence of RTH, is validated. For the first time, we report on the temperature dependence of RTH, from 25/spl deg/C up to 150/spl deg/C, in both saturation and quasi-saturation regions of DMOS, which is shown to be a quasi-linear yet significant function of the device internal temperature. Moreover, another new result is a power low-dependent thermal capacitance, as suggested by our experiments. Finally, SPICE simulations are used to validate the proposed method, and, demonstrate that a thermal-dependent thermal resistance model is highly critical for accurate advanced simulation of HV DMOS ICs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116869368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269171
H. Tseng, M. Ramón, L. Hebert, P. Tobin, D. Triyoso, J. Grant, Z.X. Jiang, D. Roan, S. Samavedam, D. Gilmer, S. Kalpat, C. Hobbs, W. Taylor, O. Adetutu, B. White
Device instability is one of the most challenging issues to implement high-k gate dielectrics. Incorporation of deuterium during the ALD (atomic layer deposition) process effectively improves the interface quality that enhances high-k device stability and reliability. Compared to H/sub 2/O processed HfO/sub 2/ devices, devices with D/sub 2/O processing result in a significantly smaller Vt shift after constant voltage stressing at room temperature and at 125/spl deg/C under NBTI/PBTI conditions, as well as a longer CHCI lifetime. This process is independent of transistor process integration and is relatively low cost. It has the potential to become an industry standard if ALD high-k gate dielectric processing is the final choice.
{"title":"ALD HfO/sub 2/ using heavy water (D/sub 2/O) for improved MOSFET stability","authors":"H. Tseng, M. Ramón, L. Hebert, P. Tobin, D. Triyoso, J. Grant, Z.X. Jiang, D. Roan, S. Samavedam, D. Gilmer, S. Kalpat, C. Hobbs, W. Taylor, O. Adetutu, B. White","doi":"10.1109/IEDM.2003.1269171","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269171","url":null,"abstract":"Device instability is one of the most challenging issues to implement high-k gate dielectrics. Incorporation of deuterium during the ALD (atomic layer deposition) process effectively improves the interface quality that enhances high-k device stability and reliability. Compared to H/sub 2/O processed HfO/sub 2/ devices, devices with D/sub 2/O processing result in a significantly smaller Vt shift after constant voltage stressing at room temperature and at 125/spl deg/C under NBTI/PBTI conditions, as well as a longer CHCI lifetime. This process is independent of transistor process integration and is relatively low cost. It has the potential to become an industry standard if ALD high-k gate dielectric processing is the final choice.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"37 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124849665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269408
I. Baek, J. Lee, H. Kim, Y. Ha, J. Bae, S.C. Oh, S.O. Park, U. Chung, N. Lee, H. Kang, J. Moon
The key factors to improve the switching characteristics are systematically analyzed to develop high density MRAM with a reliable operating margin. We demonstrated that roughness control of MTJ films, choice of free layer materials with small Ms, and optimized cell shape can effectively suppress the switching distribution. As a novel free layer scheme, a lamellar structure is proposed and found to improve the switching characteristics by suppressing the grain growth in the ferromagnetic layer.
{"title":"MRAM with lamellar structure as free layer","authors":"I. Baek, J. Lee, H. Kim, Y. Ha, J. Bae, S.C. Oh, S.O. Park, U. Chung, N. Lee, H. Kang, J. Moon","doi":"10.1109/IEDM.2003.1269408","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269408","url":null,"abstract":"The key factors to improve the switching characteristics are systematically analyzed to develop high density MRAM with a reliable operating margin. We demonstrated that roughness control of MTJ films, choice of free layer materials with small Ms, and optimized cell shape can effectively suppress the switching distribution. As a novel free layer scheme, a lamellar structure is proposed and found to improve the switching characteristics by suppressing the grain growth in the ferromagnetic layer.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129525568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269341
Seungjae Baik, Siyoung Choi, U. Chung, J. Moon
For the first time, a nitride/oxide/nitride stacked tunnel structure is adopted as highly field-sensitive tunnel barrier to improve both program/erase speed and data retention of nanocrystal memory. Product-adaptive nonvolatility (>10 years at 85/spl deg/C) and cycling endurance (>10/sup 6/) were obtained with the program time of 10 /spl mu/s at V/sub G/=8 V and the erase time of 100 /spl mu/s at V/sub G/=-8 V with 0.84 V threshold window. The program speed was 100 times faster and the voltage was about 10 V smaller than those of a conventional NAND type flash memory cell. These results strongly suggest that nanocrystal floating gate memory becomes a promising solution to overcome the scaling limitation of the conventional floating gate memory cell.
{"title":"High speed and nonvolatile Si nanocrystal memory for scaled flash technology using highly field-sensitive tunnel barrier","authors":"Seungjae Baik, Siyoung Choi, U. Chung, J. Moon","doi":"10.1109/IEDM.2003.1269341","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269341","url":null,"abstract":"For the first time, a nitride/oxide/nitride stacked tunnel structure is adopted as highly field-sensitive tunnel barrier to improve both program/erase speed and data retention of nanocrystal memory. Product-adaptive nonvolatility (>10 years at 85/spl deg/C) and cycling endurance (>10/sup 6/) were obtained with the program time of 10 /spl mu/s at V/sub G/=8 V and the erase time of 100 /spl mu/s at V/sub G/=-8 V with 0.84 V threshold window. The program speed was 100 times faster and the voltage was about 10 V smaller than those of a conventional NAND type flash memory cell. These results strongly suggest that nanocrystal floating gate memory becomes a promising solution to overcome the scaling limitation of the conventional floating gate memory cell.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128417103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269426
M. Fukuda, T. Nakanishi, Y. Nara
We demonstrate and experimentally investigate the scalability of a new 2bit/cell SONOS type nonvolatile memory cell. This memory has single layer of gate oxide and SiN sidewalls at both sides of the gate to store the charge. We have found the sidewall trapping structure is much more scalable than conventional planar SONOS structures by the precise control of alignment between the pn junction edge and the SiN sidewall. The proposed device with gate length down to 60 nm was successfully operated with the Vth window, which is the Vth difference between forward and reverse operation, of 0.6 V. Also, by employing a 2D device simulator, we found that the degradation mechanism after cycled endurance testing is the negative charge accumulation near the SiO/sub 2//Si interface on the source/drain region.
{"title":"Scaled 2bit/cell SONOS type nonvolatile memory technology for sub-90nm embedded application using SiN sidewall trapping structure","authors":"M. Fukuda, T. Nakanishi, Y. Nara","doi":"10.1109/IEDM.2003.1269426","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269426","url":null,"abstract":"We demonstrate and experimentally investigate the scalability of a new 2bit/cell SONOS type nonvolatile memory cell. This memory has single layer of gate oxide and SiN sidewalls at both sides of the gate to store the charge. We have found the sidewall trapping structure is much more scalable than conventional planar SONOS structures by the precise control of alignment between the pn junction edge and the SiN sidewall. The proposed device with gate length down to 60 nm was successfully operated with the Vth window, which is the Vth difference between forward and reverse operation, of 0.6 V. Also, by employing a 2D device simulator, we found that the degradation mechanism after cycled endurance testing is the negative charge accumulation near the SiO/sub 2//Si interface on the source/drain region.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"82 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128164041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269289
C. Huang, D. S. Yu, A. Chin, C. Wu, W. Chen, Chunxiang Zhu, M. Li, B. Cho, D. Kwong
We demonstrate for the first time fully silicided NiSi (4.55 eV) and germanided NiGe (5.2 eV) dual gates on 1.9 nm-SiO/sub 2//Si and Al/sub 2/O/sub 3//Ge-on-insulator (GOI) MOSFETs (EOT= 1.7 nm). In additional to the comparable gate current and time-to-breakdown with Al gate C-MOSFETs, the fully NiSi and NiGe gates on SiO/sub 2//Si show mobility close to universal mobility while on Al/sub 2/O/sub 3//GOI show /spl sim/2.0/spl times/ higher peak electron and hole mobility than Al on Al/sub 2/O/sub 3//Si, with the special advantage of NiSi and NiGe being compatible to current VLSI process lines.
{"title":"Fully silicided NiSi and germanided NiGe dual gates on SiO/sub 2//Si and Al/sub 2/O/sub 3//Ge-on-insulator MOSFETs","authors":"C. Huang, D. S. Yu, A. Chin, C. Wu, W. Chen, Chunxiang Zhu, M. Li, B. Cho, D. Kwong","doi":"10.1109/IEDM.2003.1269289","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269289","url":null,"abstract":"We demonstrate for the first time fully silicided NiSi (4.55 eV) and germanided NiGe (5.2 eV) dual gates on 1.9 nm-SiO/sub 2//Si and Al/sub 2/O/sub 3//Ge-on-insulator (GOI) MOSFETs (EOT= 1.7 nm). In additional to the comparable gate current and time-to-breakdown with Al gate C-MOSFETs, the fully NiSi and NiGe gates on SiO/sub 2//Si show mobility close to universal mobility while on Al/sub 2/O/sub 3//GOI show /spl sim/2.0/spl times/ higher peak electron and hole mobility than Al on Al/sub 2/O/sub 3//Si, with the special advantage of NiSi and NiGe being compatible to current VLSI process lines.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129364949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269325
H. Nayfeh, J. Hoyt, D. Antoniadis
The performance, calculated in terms of on-current I/sub on/ vs. off-current I/sub off/, of strained Si n-MOSFETs is compared to bulk (unstrained) Si devices with gate lengths down to 22 nm using hydrodynamic simulations with calibrated strained Si transport models. Strain results in I/sub on/ enhancement for given I/sub off/, but increased Coulomb scattering in strained Si super-halo n-MOSFETs with gate lengths approaching 25 nm and surface doping near 6/spl times/10/sup 18/ cm/sup -3/, results in reduction of I/sub on/ enhancement by approximately 10%. Simulations also indicate that the use of a gate electrode material with workfunction larger than n/sup +/ polysilicon is an attractive approach to achieve the desired off-current for strained devices scaled below 25 nm gate length, and for devices with increased strain in the channel (i.e. substrate Ge contents >20% Ge).
{"title":"Investigation of scaling methodology for strained Si n-MOSFETs using a calibrated transport model","authors":"H. Nayfeh, J. Hoyt, D. Antoniadis","doi":"10.1109/IEDM.2003.1269325","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269325","url":null,"abstract":"The performance, calculated in terms of on-current I/sub on/ vs. off-current I/sub off/, of strained Si n-MOSFETs is compared to bulk (unstrained) Si devices with gate lengths down to 22 nm using hydrodynamic simulations with calibrated strained Si transport models. Strain results in I/sub on/ enhancement for given I/sub off/, but increased Coulomb scattering in strained Si super-halo n-MOSFETs with gate lengths approaching 25 nm and surface doping near 6/spl times/10/sup 18/ cm/sup -3/, results in reduction of I/sub on/ enhancement by approximately 10%. Simulations also indicate that the use of a gate electrode material with workfunction larger than n/sup +/ polysilicon is an attractive approach to achieve the desired off-current for strained devices scaled below 25 nm gate length, and for devices with increased strain in the channel (i.e. substrate Ge contents >20% Ge).","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129793277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269162
C. H. Diaz, K. Fung, S.M. Cheng, K. Cheng, S.W. Wang, H. Huang, Y. Leung, M. Tsai, C.C. Wu, C.C. Lin, Mi-Chang Chang, D. Tang
To reconcile scaling-driven fundamental material limitations with industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize Systems on a Chip (SoC). This paper discusses issues associated with power supply scaling, performance-leakage power optimization, gate dielectric scaling, strain-Si enhancement and I/O support.
{"title":"Device properties in 90 nm and beyond and implications on circuit design","authors":"C. H. Diaz, K. Fung, S.M. Cheng, K. Cheng, S.W. Wang, H. Huang, Y. Leung, M. Tsai, C.C. Wu, C.C. Lin, Mi-Chang Chang, D. Tang","doi":"10.1109/IEDM.2003.1269162","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269162","url":null,"abstract":"To reconcile scaling-driven fundamental material limitations with industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize Systems on a Chip (SoC). This paper discusses issues associated with power supply scaling, performance-leakage power optimization, gate dielectric scaling, strain-Si enhancement and I/O support.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129840404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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