Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269420
E. Pop, R. Dutton, K. Goodson
This paper explores the effect of confined dimensions and complicated geometries on the self-heating of ultra-thin body SOI and FinFET devices. A compact thermal model is introduced, incorporating the most advanced understanding of nanoscale heat conduction available. Novel device scaling is analyzed from a thermal point of view. We show device temperatures are very sensitive to the choice of drain and channel extension dimensions, and suggest a parameter design space which can help alleviate thermal problems. ITRS power guidelines below the 25 nm technology node should be revised if isothermal scaling of thin-body devices is desired.
{"title":"Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices]","authors":"E. Pop, R. Dutton, K. Goodson","doi":"10.1109/IEDM.2003.1269420","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269420","url":null,"abstract":"This paper explores the effect of confined dimensions and complicated geometries on the self-heating of ultra-thin body SOI and FinFET devices. A compact thermal model is introduced, incorporating the most advanced understanding of nanoscale heat conduction available. Novel device scaling is analyzed from a thermal point of view. We show device temperatures are very sensitive to the choice of drain and channel extension dimensions, and suggest a parameter design space which can help alleviate thermal problems. ITRS power guidelines below the 25 nm technology node should be revised if isothermal scaling of thin-body devices is desired.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127973586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269166
H. Wang, Y.P. Wang, S.-J. Chen, C. Ge, S. Ting, J. Kung, R. Hwang, H.-K. Chiu, L. Sheu, Pang-Yen Tsai, L. Yao, S.C. Chen, H. Tao, Y. Yeo, W. Lee, C. Hu
We demonstrate a 60 nm gate length substrate-strained Si CMOS technology and the fastest reported ring oscillator speed of 6.5 ps at 1.2 V operation. The largest enhancement (15%) in I/sub on/-I/sub off/ characteristics without correction for self-heating effects is also reported. The substrate-strained Si process is optimized to enhance manufacturability and circumvent difficulties associated with the integration of the strained Si/SiGe heterostructure. We also report a phenomenon responsible for increased the off state leakage in strained Si devices and a way to suppress it. Surmounting key integration challenges faced by the Si/SiGe heterostructure is critical for its introduction as a manufacturable process.
{"title":"Substrate-strained silicon technology: process integration [CMOS technology]","authors":"H. Wang, Y.P. Wang, S.-J. Chen, C. Ge, S. Ting, J. Kung, R. Hwang, H.-K. Chiu, L. Sheu, Pang-Yen Tsai, L. Yao, S.C. Chen, H. Tao, Y. Yeo, W. Lee, C. Hu","doi":"10.1109/IEDM.2003.1269166","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269166","url":null,"abstract":"We demonstrate a 60 nm gate length substrate-strained Si CMOS technology and the fastest reported ring oscillator speed of 6.5 ps at 1.2 V operation. The largest enhancement (15%) in I/sub on/-I/sub off/ characteristics without correction for self-heating effects is also reported. The substrate-strained Si process is optimized to enhance manufacturability and circumvent difficulties associated with the integration of the strained Si/SiGe heterostructure. We also report a phenomenon responsible for increased the off state leakage in strained Si devices and a way to suppress it. Surmounting key integration challenges faced by the Si/SiGe heterostructure is critical for its introduction as a manufacturable process.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130140762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269170
V. Chan, R. Rengarajan, N. Rovedo, W. Jin, T. Hook, P. Nguyen, Jia Chen, E. Nowak, Xiang-Dong Chen, D. Lea, A. Chakravarti, V. Ku, S. Yang, A. Steegen, C. Baiocco, P. Shafer, H. Ng, Shih-Fen Huang, C. Wann
A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described in this paper. Gate length and dielectric scaling, along with optimized strain engineering, enable high performance devices, which are amongst the best reported to date. Short channel effect control down to 35 nm is demonstrated. Both NMOS and PMOS performance are improved through careful optimization of stress effects from both trench isolation and contact etch stop nitride film. Furthermore, analysis of the channel mobility and current enhancement is used to gain understanding of the stress mechanisms, and hence layout design practice should be optimized for performance.
{"title":"High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering","authors":"V. Chan, R. Rengarajan, N. Rovedo, W. Jin, T. Hook, P. Nguyen, Jia Chen, E. Nowak, Xiang-Dong Chen, D. Lea, A. Chakravarti, V. Ku, S. Yang, A. Steegen, C. Baiocco, P. Shafer, H. Ng, Shih-Fen Huang, C. Wann","doi":"10.1109/IEDM.2003.1269170","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269170","url":null,"abstract":"A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described in this paper. Gate length and dielectric scaling, along with optimized strain engineering, enable high performance devices, which are amongst the best reported to date. Short channel effect control down to 35 nm is demonstrated. Both NMOS and PMOS performance are improved through careful optimization of stress effects from both trench isolation and contact etch stop nitride film. Furthermore, analysis of the channel mobility and current enhancement is used to gain understanding of the stress mechanisms, and hence layout design practice should be optimized for performance.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130445564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269185
J. Kawahara, A. Nakano, N. Kunimi, K. Kinoshita, Y. Hayashi, A. Ishikawa, Y. Seino, T. Ogata, H. Takahashi, Y. Sonoda, T. Yoshino, T. Goto, S. Takada, R. Ichikawa, H. Miyoshi, H. Matsuo, S. Adachi, T. Kikkawa
A new plasma-enhanced co-polymerization (PCP) technology is developed for low-k/Cu damascene integration on 300 mm wafers. The concept of the PCP technology is to introduce monomers, which have different functions such as matrix formation, deposition acceleration, or reinforcement, into a reactor exited with a He-plasma. It is shown that the low-k film growth rate from the matrix monomer such as divinyl siloxane-benzocyclobutene (DVS-BCB) and the elastic modulus of the deposited films are enhanced by adding a deposition acceleration monomer and a reinforcement monomer, respectively, without increasing the k-value. Combining the PCP technology with an ultra-low-pressure CMP technique, the Cu damascene interconnects were successfully fabricated on 300 mm wafers.
{"title":"A new plasma-enhanced co-polymerization (PCP) technology for reinforcing mechanical properties of organic silica low-k/Cu interconnects on 300 mm wafers","authors":"J. Kawahara, A. Nakano, N. Kunimi, K. Kinoshita, Y. Hayashi, A. Ishikawa, Y. Seino, T. Ogata, H. Takahashi, Y. Sonoda, T. Yoshino, T. Goto, S. Takada, R. Ichikawa, H. Miyoshi, H. Matsuo, S. Adachi, T. Kikkawa","doi":"10.1109/IEDM.2003.1269185","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269185","url":null,"abstract":"A new plasma-enhanced co-polymerization (PCP) technology is developed for low-k/Cu damascene integration on 300 mm wafers. The concept of the PCP technology is to introduce monomers, which have different functions such as matrix formation, deposition acceleration, or reinforcement, into a reactor exited with a He-plasma. It is shown that the low-k film growth rate from the matrix monomer such as divinyl siloxane-benzocyclobutene (DVS-BCB) and the elastic modulus of the deposited films are enhanced by adding a deposition acceleration monomer and a reinforcement monomer, respectively, without increasing the k-value. Combining the PCP technology with an ultra-low-pressure CMP technique, the Cu damascene interconnects were successfully fabricated on 300 mm wafers.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129692316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269262
D. Villanueva, A. Pouydebasque, E. Robilliart, T. Skotnicki, E. Fuchs, H. Jaouen
The impact of the lateral doping abruptness (LA) of the source/drain extension still remains a polemic issue in CMOS transistor engineering. Based on dedicated simulations, it is shown that the maximum gain in on current achieved with steep profiles does not exceed 3%. Moreover, a suited analytical modeling indicates that the influence of the LA mostly resides in changing the effective channel length (Leff). Subsequently, the impact of the gate overlap is critically reviewed and actually appears to be mostly related to the analytical definition of the simulated device. Eventually, relying on a clear physical background, the analysis is carried out further to investigate the modulation of source injection properties in the framework of the backscattering theory and Monte Carlo (MC) simulations. We propose an additional injection effect that emerges at the source end potential barrier when the junction becomes very abrupt. This effect incorporated within the theory of Lundstrom enables further interpretation and understanding of the MC on-state current calculations.
{"title":"Impact of the lateral source/drain abruptness on MOSFET characteristics and transport properties","authors":"D. Villanueva, A. Pouydebasque, E. Robilliart, T. Skotnicki, E. Fuchs, H. Jaouen","doi":"10.1109/IEDM.2003.1269262","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269262","url":null,"abstract":"The impact of the lateral doping abruptness (LA) of the source/drain extension still remains a polemic issue in CMOS transistor engineering. Based on dedicated simulations, it is shown that the maximum gain in on current achieved with steep profiles does not exceed 3%. Moreover, a suited analytical modeling indicates that the influence of the LA mostly resides in changing the effective channel length (Leff). Subsequently, the impact of the gate overlap is critically reviewed and actually appears to be mostly related to the analytical definition of the simulated device. Eventually, relying on a clear physical background, the analysis is carried out further to investigate the modulation of source injection properties in the framework of the backscattering theory and Monte Carlo (MC) simulations. We propose an additional injection effect that emerges at the source end potential barrier when the junction becomes very abrupt. This effect incorporated within the theory of Lundstrom enables further interpretation and understanding of the MC on-state current calculations.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"51 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121194460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269438
Yu-Wei Lin, Seungbae Lee, Z. Ren, C. Nguyen
A 10-MHz series resonant micromechanical resonator oscillator has been demonstrated using a custom-designed, single-stage, zero-phase-shift sustaining amplifier together with a clamped-clamped beam micromechanical resonator, designed with a relatively large width of 40 /spl mu/m to achieve substantially lower series motional resistance R/sub x/ and higher power handling than previous such devices. Using automatic level control (ALC) circuitry to remove an unexpected 1/f/sup 3/ close-to-carrier phase noise component, this oscillator achieves a phase noise density of -95 dBc/Hz at 1 kHz offset from the carrier, while consuming only 820 /spl mu/W of power.
{"title":"Series-resonant micromechanical resonator oscillator","authors":"Yu-Wei Lin, Seungbae Lee, Z. Ren, C. Nguyen","doi":"10.1109/IEDM.2003.1269438","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269438","url":null,"abstract":"A 10-MHz series resonant micromechanical resonator oscillator has been demonstrated using a custom-designed, single-stage, zero-phase-shift sustaining amplifier together with a clamped-clamped beam micromechanical resonator, designed with a relatively large width of 40 /spl mu/m to achieve substantially lower series motional resistance R/sub x/ and higher power handling than previous such devices. Using automatic level control (ALC) circuitry to remove an unexpected 1/f/sup 3/ close-to-carrier phase noise component, this oscillator achieves a phase noise density of -95 dBc/Hz at 1 kHz offset from the carrier, while consuming only 820 /spl mu/W of power.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121371997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269338
Y. Wee, Soo-Geun Lee, Won-sang Song, Kyoung-Woo Lee, N. Lee, J.E. Ku, Ki-kwan Park, Seung Jin Lee, Jae Hak Kim, J. Chung, Hong-jae Shin, S. Hah, Ho-Kyu Kang, G. Suh
Despite the initial success in integrating a 90 nm Cu/SiOC (k=2.9) device using the HSQ via-filler scheme, the reliability issues remain. By correlating electromigration (EM) with the moisture blocking capability of the dielectric-diffusion-barrier, we target the factors contributing to the moisture blockage, namely, the N and H-content within SiC. Consequently, increasing the N/H ratio in the SiCN film, we demonstrated a significant enhancement in EM reliability.
{"title":"Alleviating electromigration through re-engineering the interface between Cu & dielectric-diffusion-barrier in 90 nm Cu/SiOC (k=2.9) device","authors":"Y. Wee, Soo-Geun Lee, Won-sang Song, Kyoung-Woo Lee, N. Lee, J.E. Ku, Ki-kwan Park, Seung Jin Lee, Jae Hak Kim, J. Chung, Hong-jae Shin, S. Hah, Ho-Kyu Kang, G. Suh","doi":"10.1109/IEDM.2003.1269338","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269338","url":null,"abstract":"Despite the initial success in integrating a 90 nm Cu/SiOC (k=2.9) device using the HSQ via-filler scheme, the reliability issues remain. By correlating electromigration (EM) with the moisture blocking capability of the dielectric-diffusion-barrier, we target the factors contributing to the moisture blockage, namely, the N and H-content within SiC. Consequently, increasing the N/H ratio in the SiCN film, we demonstrated a significant enhancement in EM reliability.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"431 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116005808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269297
Yung-Huei Lee, N. Mielke, B. Sabi, S. Stadler, R. Nachman, S. Hu
This work investigated the impact of pMOST bias-temperature (BT) degradation on logic product speed (F/sub max/) and minimum allowed operating voltage (V/sub ccmin/). Fluorine implants after poly etch and before hard-mask removal are utilized to separate out the BT instability effects from other reliability degradations. Physical mechanisms and models are proposed to explain the interaction of fluorine with device and circuit reliability. A reliability guardband in F/sub max/ and V/sub ccmin/ is recommended as part of the production testing to ensure reliable logic product performance and functionality during the product's lifetime.
{"title":"Effect of pMOST bias-temperature instability on circuit reliability performance","authors":"Yung-Huei Lee, N. Mielke, B. Sabi, S. Stadler, R. Nachman, S. Hu","doi":"10.1109/IEDM.2003.1269297","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269297","url":null,"abstract":"This work investigated the impact of pMOST bias-temperature (BT) degradation on logic product speed (F/sub max/) and minimum allowed operating voltage (V/sub ccmin/). Fluorine implants after poly etch and before hard-mask removal are utilized to separate out the BT instability effects from other reliability degradations. Physical mechanisms and models are proposed to explain the interaction of fluorine with device and circuit reliability. A reliability guardband in F/sub max/ and V/sub ccmin/ is recommended as part of the production testing to ensure reliable logic product performance and functionality during the product's lifetime.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131200303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269240
H. Klauk, M. Halik, U. Zschieschang, G. Schmid, C. Dehm, R. Brederlow, S. Briole
We have developed a molecular thin film transistor concept based on a high-mobility organic semiconductor (pentacene) and an ultra-thin, molecular self-assembling monolayer (SAM) gate dielectric. These transistors operate at voltages between 1 and 3 V, with a subthreshold swing as low as 100 mV/decade. For a transistor with a channel length of 5 /spl mu/m, we have measured a transconductance of 0.01 /spl mu/S//spl mu/m, to our knowledge the largest transconductance reported for an organic semiconductor device.
{"title":"Molecular thin film transistors with a subthreshold swing of 100 mV/decade","authors":"H. Klauk, M. Halik, U. Zschieschang, G. Schmid, C. Dehm, R. Brederlow, S. Briole","doi":"10.1109/IEDM.2003.1269240","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269240","url":null,"abstract":"We have developed a molecular thin film transistor concept based on a high-mobility organic semiconductor (pentacene) and an ultra-thin, molecular self-assembling monolayer (SAM) gate dielectric. These transistors operate at voltages between 1 and 3 V, with a subthreshold swing as low as 100 mV/decade. For a transistor with a channel length of 5 /spl mu/m, we have measured a transconductance of 0.01 /spl mu/S//spl mu/m, to our knowledge the largest transconductance reported for an organic semiconductor device.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116923693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269416
R. Van Langevelde, J. Paasschens, A. Scholten, R. Havens, L. Tiemeijer, D. Klaassen
Accurate compact modeling of induced gate noise is a prerequisite for RF CMOS circuit design. Existing models underestimate the induced gate noise for short-channel devices. In this paper, a new model is introduced, based on an improved Klaassen-Prins approach, which accurately accounts for velocity saturation. The model accurately describes noise without fitting any additional parameters.
{"title":"New compact model for induced gate current noise [MOSFET]","authors":"R. Van Langevelde, J. Paasschens, A. Scholten, R. Havens, L. Tiemeijer, D. Klaassen","doi":"10.1109/IEDM.2003.1269416","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269416","url":null,"abstract":"Accurate compact modeling of induced gate noise is a prerequisite for RF CMOS circuit design. Existing models underestimate the induced gate noise for short-channel devices. In this paper, a new model is introduced, based on an improved Klaassen-Prins approach, which accurately accounts for velocity saturation. The model accurately describes noise without fitting any additional parameters.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123819130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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