Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269303
Hang Hu, S. Ding, H.F. Lim, Chunxiang Zhu, M. Li, S.J. Kim, X.F. Yu, J.H. Chen, Y. F. Yong, B. Cho, D. Chan, S. Rustagi, M. Yu, C. Tung, A. Du, D. My, P.D. Foot, A. Chin, D. Kwong
In this paper, a high performance ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate metal-insulator-metal (MIM) capacitor is demonstrated for the first time with high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz to 20 GHz, low leakage current of 7.45/spl times/10/sup -9/ A/cm/sup 2/ at 2 V, low VCC (voltage coefficients of capacitance), and excellent reliability. The superior electrical properties and reliability suggest that the ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising material for MIM capacitors for Si RF and mixed signal IC applications.
{"title":"High performance ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors for RF and mixed signal IC applications","authors":"Hang Hu, S. Ding, H.F. Lim, Chunxiang Zhu, M. Li, S.J. Kim, X.F. Yu, J.H. Chen, Y. F. Yong, B. Cho, D. Chan, S. Rustagi, M. Yu, C. Tung, A. Du, D. My, P.D. Foot, A. Chin, D. Kwong","doi":"10.1109/IEDM.2003.1269303","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269303","url":null,"abstract":"In this paper, a high performance ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate metal-insulator-metal (MIM) capacitor is demonstrated for the first time with high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz to 20 GHz, low leakage current of 7.45/spl times/10/sup -9/ A/cm/sup 2/ at 2 V, low VCC (voltage coefficients of capacitance), and excellent reliability. The superior electrical properties and reliability suggest that the ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising material for MIM capacitors for Si RF and mixed signal IC applications.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116448422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269304
S. Denbaars, T. Katona, P. Cantu, A. Hanlon, S. Keller, M. Schmidt, T. Margalith, M. Pattisson, C. Moe, J. Speck, S. Nakamura
This talk summarizes the important materials and device results in gallium nitride based light emitter technology. GaN has emerged as the most promising material for high brightness LEDs with colors ranging from UV to blue, green, and white. Recent progress on ultra-violet (UV) emitting LEDs using AlGaN single quantum wells indicates wavelengths as short as 292 nm are achievable. UV LEDs are of great interest for solid state white lighting due to the high conversion efficiencies of typical phosphors in the UV spectrum. This paper focuses on recent progress in improving the properties of UV LEDs.
{"title":"GaN based high brightness LEDs and UV LEDs","authors":"S. Denbaars, T. Katona, P. Cantu, A. Hanlon, S. Keller, M. Schmidt, T. Margalith, M. Pattisson, C. Moe, J. Speck, S. Nakamura","doi":"10.1109/IEDM.2003.1269304","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269304","url":null,"abstract":"This talk summarizes the important materials and device results in gallium nitride based light emitter technology. GaN has emerged as the most promising material for high brightness LEDs with colors ranging from UV to blue, green, and white. Recent progress on ultra-violet (UV) emitting LEDs using AlGaN single quantum wells indicates wavelengths as short as 292 nm are achievable. UV LEDs are of great interest for solid state white lighting due to the high conversion efficiencies of typical phosphors in the UV spectrum. This paper focuses on recent progress in improving the properties of UV LEDs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126828280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269286
S. Samavedam, L. La, P. Tobin, B. White, C. Hobbs, L. Fonseca, A. Demkov, J. Schaeffer, E. Luckowski, A. Martínez, M. Raymond, D. Triyoso, D. Roan, V. Dhandapani, R. García, S. Anderson, K. Moore, H. Tseng, C. Capasso, O. Adetutu, D. Gilmer, W. Taylor, R. Hegde, J. Grant
We have examined the impact of small and systematic changes at the metal/dielectric interface on metal work-function and report on Fermi level pinning of TaN, TaSiN and TiN gates on SiO/sub 2/, Al/sub 2/O/sub 3/ and HfO/sub 2/ for the first time. The shifts in work-function agree in most cases with the MIGS theory if accurate theoretical parameters are used.
{"title":"Fermi level pinning with sub-monolayer MeOx and metal gates [MOSFETs]","authors":"S. Samavedam, L. La, P. Tobin, B. White, C. Hobbs, L. Fonseca, A. Demkov, J. Schaeffer, E. Luckowski, A. Martínez, M. Raymond, D. Triyoso, D. Roan, V. Dhandapani, R. García, S. Anderson, K. Moore, H. Tseng, C. Capasso, O. Adetutu, D. Gilmer, W. Taylor, R. Hegde, J. Grant","doi":"10.1109/IEDM.2003.1269286","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269286","url":null,"abstract":"We have examined the impact of small and systematic changes at the metal/dielectric interface on metal work-function and report on Fermi level pinning of TaN, TaSiN and TiN gates on SiO/sub 2/, Al/sub 2/O/sub 3/ and HfO/sub 2/ for the first time. The shifts in work-function agree in most cases with the MIGS theory if accurate theoretical parameters are used.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124391897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269340
K. Guarini, C. T. Black, Y. Zhang, I. Babich, E. Sikorski, L. Gignac
We introduce a new method for building nanocrystal flash memory devices that achieves precise control of nanocrystal size and position. Nanocrystal dimensions are defined via polymer self assembly, facilitating device scaling. Devices exhibit low voltage memory operation with promising retention and endurance properties.
{"title":"Low voltage, scalable nanocrystal flash memory fabricated by templated self assembly","authors":"K. Guarini, C. T. Black, Y. Zhang, I. Babich, E. Sikorski, L. Gignac","doi":"10.1109/IEDM.2003.1269340","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269340","url":null,"abstract":"We introduce a new method for building nanocrystal flash memory devices that achieves precise control of nanocrystal size and position. Nanocrystal dimensions are defined via polymer self assembly, facilitating device scaling. Devices exhibit low voltage memory operation with promising retention and endurance properties.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127304352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269180
H. Rucker, B. Heinemann, R. Barth, D. Bolze, J. Drews, U. Haak, W. Hoppner, D. Knoll, K. Kopke, S. Marschmeyer, H. Richter, P. Schley, D. Schmidt, R. Scholz, B. Tillack, W. Winkler, H. Wulf, Y. Yamamoto
A high-speed SiGe:C HBT technology is presented that combines a new extrinsic base construction with a low-resistance collector design to simultaneously minimize base and collector resistances and base-collector capacitance. A ring oscillator delay of 3.6 ps per stage was achieved. To our knowledge, this is the shortest gate delay reported to date for a SiGe technology. The HBTs demonstrate an f/sub T/ of 190 GHz, an f/sub max/ of 243 GHz, and a BV/sub CEO/ of 1.9 V at an drawn emitter size of 0.175/spl times/0.84 /spl mu/m/sup 2/. The high-speed HBT module has been integrated in a 0.25 /spl mu/m CMOS platform.
{"title":"SiGe:C BiCMOS technology with 3.6 ps gate delay","authors":"H. Rucker, B. Heinemann, R. Barth, D. Bolze, J. Drews, U. Haak, W. Hoppner, D. Knoll, K. Kopke, S. Marschmeyer, H. Richter, P. Schley, D. Schmidt, R. Scholz, B. Tillack, W. Winkler, H. Wulf, Y. Yamamoto","doi":"10.1109/IEDM.2003.1269180","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269180","url":null,"abstract":"A high-speed SiGe:C HBT technology is presented that combines a new extrinsic base construction with a low-resistance collector design to simultaneously minimize base and collector resistances and base-collector capacitance. A ring oscillator delay of 3.6 ps per stage was achieved. To our knowledge, this is the shortest gate delay reported to date for a SiGe technology. The HBTs demonstrate an f/sub T/ of 190 GHz, an f/sub max/ of 243 GHz, and a BV/sub CEO/ of 1.9 V at an drawn emitter size of 0.175/spl times/0.84 /spl mu/m/sup 2/. The high-speed HBT module has been integrated in a 0.25 /spl mu/m CMOS platform.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130758529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269384
K. Makiyama, T. Takahashi, T. Suzuki, K. Sawada, T. Ohki, M. Nishi, N. Hara, M. Takikawa
We developed a novel process technology to removes the dielectric substance around gate electrodes to decrease parasitic capacitance. The process enabled us to increase the operating speed of the integrated circuit without causing any process damage. As a result, we achieved 90 GHz operation of a static T-FF circuit using InP-HEMT technology. This is the fastest T-FF, consisting of a FET, reported to date. We also showed the excellent potential of this technology for fabricating ultra-high speed ICs.
{"title":"Improvement of circuit-speed of HEMTs IC by reducing the parasitic capacitance","authors":"K. Makiyama, T. Takahashi, T. Suzuki, K. Sawada, T. Ohki, M. Nishi, N. Hara, M. Takikawa","doi":"10.1109/IEDM.2003.1269384","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269384","url":null,"abstract":"We developed a novel process technology to removes the dielectric substance around gate electrodes to decrease parasitic capacitance. The process enabled us to increase the operating speed of the integrated circuit without causing any process damage. As a result, we achieved 90 GHz operation of a static T-FF circuit using InP-HEMT technology. This is the fastest T-FF, consisting of a FET, reported to date. We also showed the excellent potential of this technology for fabricating ultra-high speed ICs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131444084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269373
T. Krishnamohan, C. Jungemann, K. Saraswat
A novel, high performance sub-20 nm DMDG Si/Si/sub x/Ge/sub (1-x)//Si channel PMOSFET is proposed. Full-band Monte Carlo and 1D Poisson-Schrodinger simulations show a 43% increase in I/sub on/ and /spl sim/2/spl times/ increase in switching speeds at 35% lower power dissipation compared to conventional Si DGFETs. The cut-off frequencies are in excess of 1000 GHz making the device also very suitable for analog applications.
{"title":"A novel, very high performance, sub-20nm depletion-mode double-gate (DMDG) Si/Si/sub x/Ge/sub (1-x)//Si channel PMOSFET","authors":"T. Krishnamohan, C. Jungemann, K. Saraswat","doi":"10.1109/IEDM.2003.1269373","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269373","url":null,"abstract":"A novel, high performance sub-20 nm DMDG Si/Si/sub x/Ge/sub (1-x)//Si channel PMOSFET is proposed. Full-band Monte Carlo and 1D Poisson-Schrodinger simulations show a 43% increase in I/sub on/ and /spl sim/2/spl times/ increase in switching speeds at 35% lower power dissipation compared to conventional Si DGFETs. The cut-off frequencies are in excess of 1000 GHz making the device also very suitable for analog applications.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134119621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269279
Y. Nakahara, T. Fukai, M. Togo, S. Koyama, H. Morikuni, T. Matsuda, K. Sakamoto, A. Mineji, S. Fujiwara, Y. Kunimune, M. Nagase, T. Tamura, N. Onoda, S. Miyake, Y. Yama, T. Kudoh, M. Ikeda, Y. Yamagata, T. Yamamoto, K. Imai
We have developed a highly reliable 65 nm node CMOS technology, enabling a wide-range of Vdd operation, including overdrive mode. Process conditions are carefully optimized from the various aspects of device reliability and performance. We have utilized an oxynitride gate, arsenic-assisted phosphorus S/D ion-implantation, Ni-silicidation, stress controlled SiN layer process, and an offset-spacer process in order to improve the drive-current at low voltage operation and reliability at high voltage operation. The obtained drive-currents are 730/310 /spl mu/A//spl mu/m with an off-current of 80 nA//spl mu/m at a standard supply voltage of 0.9 V, and 1150/550 /spl mu/A//spl mu/m with an off-current of 180 nA//spl mu/m at an overdrive voltage of 1.2 V, while satisfying strict criteria for transistor reliability.
{"title":"A robust 65-nm node CMOS technology for wide-range Vdd operation","authors":"Y. Nakahara, T. Fukai, M. Togo, S. Koyama, H. Morikuni, T. Matsuda, K. Sakamoto, A. Mineji, S. Fujiwara, Y. Kunimune, M. Nagase, T. Tamura, N. Onoda, S. Miyake, Y. Yama, T. Kudoh, M. Ikeda, Y. Yamagata, T. Yamamoto, K. Imai","doi":"10.1109/IEDM.2003.1269279","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269279","url":null,"abstract":"We have developed a highly reliable 65 nm node CMOS technology, enabling a wide-range of Vdd operation, including overdrive mode. Process conditions are carefully optimized from the various aspects of device reliability and performance. We have utilized an oxynitride gate, arsenic-assisted phosphorus S/D ion-implantation, Ni-silicidation, stress controlled SiN layer process, and an offset-spacer process in order to improve the drive-current at low voltage operation and reliability at high voltage operation. The obtained drive-currents are 730/310 /spl mu/A//spl mu/m with an off-current of 80 nA//spl mu/m at a standard supply voltage of 0.9 V, and 1150/550 /spl mu/A//spl mu/m with an off-current of 180 nA//spl mu/m at an overdrive voltage of 1.2 V, while satisfying strict criteria for transistor reliability.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"327 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133104285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269398
M. Lundstrom
This paper reviews our efforts to use theory and simulation to understand the device physics of nanoscale MOSFETs. The essential physics of MOSFETs at the scaling limit are discussed, and unresolved theoretical issues and technological ones that limit device performance and ultimate scaling are identified.
{"title":"Device physics at the scaling limit: what matters? [MOSFETs]","authors":"M. Lundstrom","doi":"10.1109/IEDM.2003.1269398","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269398","url":null,"abstract":"This paper reviews our efforts to use theory and simulation to understand the device physics of nanoscale MOSFETs. The essential physics of MOSFETs at the scaling limit are discussed, and unresolved theoretical issues and technological ones that limit device performance and ultimate scaling are identified.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"402 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124301146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269364
F. Ootsuka, H. Ozaki, T. Sasaki, K. Yamashita, H. Takada, N. Izumi, Y. Nakagawa, M. Hayashi, K. Kiyono, M. Yasuhira, T. Arikado
This paper describes the fabrication process and the performance of 65 nm-node CMOS transistors which have ultra-shallow junctions. Flash lamp annealing enhances the drivability of pFETs with a solid phase epitaxial extension junction. The increase in the junction leakage of the extension junction is less than 1 order of magnitude as compared with that for the conventional spike RTA on a 300 mm/spl phi/ wafer. Excellent Vth control at 35 nm gate length without halo implantation and a high switching speed at 0.9 V power supply are demonstrated for 65 nm-node LOP (low operation power) applications.
{"title":"Ultra-low thermal budget CMOS process for 65nm-node low-operation-power applications","authors":"F. Ootsuka, H. Ozaki, T. Sasaki, K. Yamashita, H. Takada, N. Izumi, Y. Nakagawa, M. Hayashi, K. Kiyono, M. Yasuhira, T. Arikado","doi":"10.1109/IEDM.2003.1269364","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269364","url":null,"abstract":"This paper describes the fabrication process and the performance of 65 nm-node CMOS transistors which have ultra-shallow junctions. Flash lamp annealing enhances the drivability of pFETs with a solid phase epitaxial extension junction. The increase in the junction leakage of the extension junction is less than 1 order of magnitude as compared with that for the conventional spike RTA on a 300 mm/spl phi/ wafer. Excellent Vth control at 35 nm gate length without halo implantation and a high switching speed at 0.9 V power supply are demonstrated for 65 nm-node LOP (low operation power) applications.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"515 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123076467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：