Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269180
H. Rucker, B. Heinemann, R. Barth, D. Bolze, J. Drews, U. Haak, W. Hoppner, D. Knoll, K. Kopke, S. Marschmeyer, H. Richter, P. Schley, D. Schmidt, R. Scholz, B. Tillack, W. Winkler, H. Wulf, Y. Yamamoto
A high-speed SiGe:C HBT technology is presented that combines a new extrinsic base construction with a low-resistance collector design to simultaneously minimize base and collector resistances and base-collector capacitance. A ring oscillator delay of 3.6 ps per stage was achieved. To our knowledge, this is the shortest gate delay reported to date for a SiGe technology. The HBTs demonstrate an f/sub T/ of 190 GHz, an f/sub max/ of 243 GHz, and a BV/sub CEO/ of 1.9 V at an drawn emitter size of 0.175/spl times/0.84 /spl mu/m/sup 2/. The high-speed HBT module has been integrated in a 0.25 /spl mu/m CMOS platform.
{"title":"SiGe:C BiCMOS technology with 3.6 ps gate delay","authors":"H. Rucker, B. Heinemann, R. Barth, D. Bolze, J. Drews, U. Haak, W. Hoppner, D. Knoll, K. Kopke, S. Marschmeyer, H. Richter, P. Schley, D. Schmidt, R. Scholz, B. Tillack, W. Winkler, H. Wulf, Y. Yamamoto","doi":"10.1109/IEDM.2003.1269180","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269180","url":null,"abstract":"A high-speed SiGe:C HBT technology is presented that combines a new extrinsic base construction with a low-resistance collector design to simultaneously minimize base and collector resistances and base-collector capacitance. A ring oscillator delay of 3.6 ps per stage was achieved. To our knowledge, this is the shortest gate delay reported to date for a SiGe technology. The HBTs demonstrate an f/sub T/ of 190 GHz, an f/sub max/ of 243 GHz, and a BV/sub CEO/ of 1.9 V at an drawn emitter size of 0.175/spl times/0.84 /spl mu/m/sup 2/. The high-speed HBT module has been integrated in a 0.25 /spl mu/m CMOS platform.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130758529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269165
S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, N. Hirashita, T. Maeda
This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.
{"title":"Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs","authors":"S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, N. Hirashita, T. Maeda","doi":"10.1109/IEDM.2003.1269165","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269165","url":null,"abstract":"This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130277886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269394
N. Sato, S. Shigematsu, H. Morimura, M. Yano, K. Kudou, T. Kamei, K. Machida
This paper describes a novel structure of MEMS (microelectromechanical systems) and its fabrication process on the surface of the MEMS fingerprint sensor that works as an interface between a finger and the sensor. In order to detect fingerprints, whether a finger is soft or hard, novel T-shaped protrusions are proposed. The structure was fabricated by etching a sacrificial layer on the cavity structure that has a pair of electrodes. Structural calculations and experimental measurements showed that the proposed sensor bends the electrode most efficiently. This enables fingerprint detection regardless of finger elasticity, and enhances sensitivity for various finger surface conditions.
{"title":"High sensitive structure and its fabrication process for MEMS fingerprint sensor to various fingers","authors":"N. Sato, S. Shigematsu, H. Morimura, M. Yano, K. Kudou, T. Kamei, K. Machida","doi":"10.1109/IEDM.2003.1269394","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269394","url":null,"abstract":"This paper describes a novel structure of MEMS (microelectromechanical systems) and its fabrication process on the surface of the MEMS fingerprint sensor that works as an interface between a finger and the sensor. In order to detect fingerprints, whether a finger is soft or hard, novel T-shaped protrusions are proposed. The structure was fabricated by etching a sacrificial layer on the cavity structure that has a pair of electrodes. Structural calculations and experimental measurements showed that the proposed sensor bends the electrode most efficiently. This enables fingerprint detection regardless of finger elasticity, and enhances sensitivity for various finger surface conditions.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128696299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269317
J. Kedzierski, D. Boyd, Ying Zhang, M. Steen, F. Jamin, J. Benedict, M. Ieong, W. Haensch
Thin-body fully depleted silicon on insulator (FDSOI) devices with NiSi metal gates were fabricated with gate lengths down to 20 nm. Specific issues in the integration of the NiSi-gated FDSOI devices were investigated, in particular: gate CMP, the phase stability of the nickel silicide, and parasitic resistance.
{"title":"Issues in NiSi-gated FDSOI device integration","authors":"J. Kedzierski, D. Boyd, Ying Zhang, M. Steen, F. Jamin, J. Benedict, M. Ieong, W. Haensch","doi":"10.1109/IEDM.2003.1269317","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269317","url":null,"abstract":"Thin-body fully depleted silicon on insulator (FDSOI) devices with NiSi metal gates were fabricated with gate lengths down to 20 nm. Specific issues in the integration of the NiSi-gated FDSOI devices were investigated, in particular: gate CMP, the phase stability of the nickel silicide, and parasitic resistance.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125714927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269340
K. Guarini, C. T. Black, Y. Zhang, I. Babich, E. Sikorski, L. Gignac
We introduce a new method for building nanocrystal flash memory devices that achieves precise control of nanocrystal size and position. Nanocrystal dimensions are defined via polymer self assembly, facilitating device scaling. Devices exhibit low voltage memory operation with promising retention and endurance properties.
{"title":"Low voltage, scalable nanocrystal flash memory fabricated by templated self assembly","authors":"K. Guarini, C. T. Black, Y. Zhang, I. Babich, E. Sikorski, L. Gignac","doi":"10.1109/IEDM.2003.1269340","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269340","url":null,"abstract":"We introduce a new method for building nanocrystal flash memory devices that achieves precise control of nanocrystal size and position. Nanocrystal dimensions are defined via polymer self assembly, facilitating device scaling. Devices exhibit low voltage memory operation with promising retention and endurance properties.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127304352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269353
R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White
The first functional 6 V, 4 Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90 nm and 0.25 /spl mu/m process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded flash at the 90 nm node and beyond.
{"title":"A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory","authors":"R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White","doi":"10.1109/IEDM.2003.1269353","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269353","url":null,"abstract":"The first functional 6 V, 4 Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90 nm and 0.25 /spl mu/m process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded flash at the 90 nm node and beyond.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122659234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269304
S. Denbaars, T. Katona, P. Cantu, A. Hanlon, S. Keller, M. Schmidt, T. Margalith, M. Pattisson, C. Moe, J. Speck, S. Nakamura
This talk summarizes the important materials and device results in gallium nitride based light emitter technology. GaN has emerged as the most promising material for high brightness LEDs with colors ranging from UV to blue, green, and white. Recent progress on ultra-violet (UV) emitting LEDs using AlGaN single quantum wells indicates wavelengths as short as 292 nm are achievable. UV LEDs are of great interest for solid state white lighting due to the high conversion efficiencies of typical phosphors in the UV spectrum. This paper focuses on recent progress in improving the properties of UV LEDs.
{"title":"GaN based high brightness LEDs and UV LEDs","authors":"S. Denbaars, T. Katona, P. Cantu, A. Hanlon, S. Keller, M. Schmidt, T. Margalith, M. Pattisson, C. Moe, J. Speck, S. Nakamura","doi":"10.1109/IEDM.2003.1269304","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269304","url":null,"abstract":"This talk summarizes the important materials and device results in gallium nitride based light emitter technology. GaN has emerged as the most promising material for high brightness LEDs with colors ranging from UV to blue, green, and white. Recent progress on ultra-violet (UV) emitting LEDs using AlGaN single quantum wells indicates wavelengths as short as 292 nm are achievable. UV LEDs are of great interest for solid state white lighting due to the high conversion efficiencies of typical phosphors in the UV spectrum. This paper focuses on recent progress in improving the properties of UV LEDs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126828280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269345
Y. Ando, Y. Okamoto, K. Hataya, T. Nakayama, H. Miyamoto, T. Inoue, M. Kuzuhara
A recessed-gate structure was introduced to improve transconductance (gm) and gain characteristics in AlGaN/GaN field-plate (FP) FETs. A maximum gm was improved from 130 to 200 mS/mm by introducing gate recess. Recessed FP-FETs exhibited 3-7 dB higher linear gain as compared with planar FP-FETs. A 1 mm-wide recessed FP-FET biased at a drain voltage of 66 V demonstrated 12.0 W output power, 21.2 dB linear gain, and 48.8 % power added efficiency at 2 GHz. To our knowledge, the power density of 12.0 W/mm is the highest ever achieved for GaN-based FETs.
{"title":"12 W/mm recessed-gate AlGaN/GaN heterojunction field-plate FET","authors":"Y. Ando, Y. Okamoto, K. Hataya, T. Nakayama, H. Miyamoto, T. Inoue, M. Kuzuhara","doi":"10.1109/IEDM.2003.1269345","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269345","url":null,"abstract":"A recessed-gate structure was introduced to improve transconductance (gm) and gain characteristics in AlGaN/GaN field-plate (FP) FETs. A maximum gm was improved from 130 to 200 mS/mm by introducing gate recess. Recessed FP-FETs exhibited 3-7 dB higher linear gain as compared with planar FP-FETs. A 1 mm-wide recessed FP-FET biased at a drain voltage of 66 V demonstrated 12.0 W output power, 21.2 dB linear gain, and 48.8 % power added efficiency at 2 GHz. To our knowledge, the power density of 12.0 W/mm is the highest ever achieved for GaN-based FETs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126454190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269384
K. Makiyama, T. Takahashi, T. Suzuki, K. Sawada, T. Ohki, M. Nishi, N. Hara, M. Takikawa
We developed a novel process technology to removes the dielectric substance around gate electrodes to decrease parasitic capacitance. The process enabled us to increase the operating speed of the integrated circuit without causing any process damage. As a result, we achieved 90 GHz operation of a static T-FF circuit using InP-HEMT technology. This is the fastest T-FF, consisting of a FET, reported to date. We also showed the excellent potential of this technology for fabricating ultra-high speed ICs.
{"title":"Improvement of circuit-speed of HEMTs IC by reducing the parasitic capacitance","authors":"K. Makiyama, T. Takahashi, T. Suzuki, K. Sawada, T. Ohki, M. Nishi, N. Hara, M. Takikawa","doi":"10.1109/IEDM.2003.1269384","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269384","url":null,"abstract":"We developed a novel process technology to removes the dielectric substance around gate electrodes to decrease parasitic capacitance. The process enabled us to increase the operating speed of the integrated circuit without causing any process damage. As a result, we achieved 90 GHz operation of a static T-FF circuit using InP-HEMT technology. This is the fastest T-FF, consisting of a FET, reported to date. We also showed the excellent potential of this technology for fabricating ultra-high speed ICs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131444084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269364
F. Ootsuka, H. Ozaki, T. Sasaki, K. Yamashita, H. Takada, N. Izumi, Y. Nakagawa, M. Hayashi, K. Kiyono, M. Yasuhira, T. Arikado
This paper describes the fabrication process and the performance of 65 nm-node CMOS transistors which have ultra-shallow junctions. Flash lamp annealing enhances the drivability of pFETs with a solid phase epitaxial extension junction. The increase in the junction leakage of the extension junction is less than 1 order of magnitude as compared with that for the conventional spike RTA on a 300 mm/spl phi/ wafer. Excellent Vth control at 35 nm gate length without halo implantation and a high switching speed at 0.9 V power supply are demonstrated for 65 nm-node LOP (low operation power) applications.
{"title":"Ultra-low thermal budget CMOS process for 65nm-node low-operation-power applications","authors":"F. Ootsuka, H. Ozaki, T. Sasaki, K. Yamashita, H. Takada, N. Izumi, Y. Nakagawa, M. Hayashi, K. Kiyono, M. Yasuhira, T. Arikado","doi":"10.1109/IEDM.2003.1269364","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269364","url":null,"abstract":"This paper describes the fabrication process and the performance of 65 nm-node CMOS transistors which have ultra-shallow junctions. Flash lamp annealing enhances the drivability of pFETs with a solid phase epitaxial extension junction. The increase in the junction leakage of the extension junction is less than 1 order of magnitude as compared with that for the conventional spike RTA on a 300 mm/spl phi/ wafer. Excellent Vth control at 35 nm gate length without halo implantation and a high switching speed at 0.9 V power supply are demonstrated for 65 nm-node LOP (low operation power) applications.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"515 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123076467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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