Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269278
D. Greenlaw, G. Burbach, T. Feudel, F. Feustel, K. Frohberg, F. Graetsch, G. Grasshoff, C. Hartig, T. Heller, K. Hempel, M. Horstmann, P. Huebler, R. Kirsch, S. Kruegel, E. Langer, A. Pawlowitsch, H. Ruelke, H. Schuehrer, R. Stephan, A. Wei, T. Werner, K. Wieczorek, M. Raab
SOI and low-k technologies are rapidly approaching production maturity. This paper highlights several challenges found when moving them from development to high-volume manufacturing. In overcoming these challenges in wafer processing and transistor development, we have achieved yield learning and performance enhancement rates equivalent to or better than conventional technologies.
{"title":"Taking SOI substrates and low-k dielectrics into high-volume microprocessor production","authors":"D. Greenlaw, G. Burbach, T. Feudel, F. Feustel, K. Frohberg, F. Graetsch, G. Grasshoff, C. Hartig, T. Heller, K. Hempel, M. Horstmann, P. Huebler, R. Kirsch, S. Kruegel, E. Langer, A. Pawlowitsch, H. Ruelke, H. Schuehrer, R. Stephan, A. Wei, T. Werner, K. Wieczorek, M. Raab","doi":"10.1109/IEDM.2003.1269278","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269278","url":null,"abstract":"SOI and low-k technologies are rapidly approaching production maturity. This paper highlights several challenges found when moving them from development to high-volume manufacturing. In overcoming these challenges in wafer processing and transistor development, we have achieved yield learning and performance enhancement rates equivalent to or better than conventional technologies.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121871106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269182
T. Hashimoto, Y. Nonaka, T. Tominari, H. Fujiwara, K. Tokunaga, M. Arai, S. Wada, T. Udo, M. Seto, M. Miura, H. Shimamoto, K. Washio, H. Tomioka
200 GHz f/sub T/ SiGe HBTs and 80 nm gate CMOS were successfully integrated using the LP-CVD technique for selective SiGe epitaxial growth. Suppressing base resistance enabled us to achieve f/sub MAX/ of 227 GHz, corresponding to f/sub T/ of 201 GHz. Shrunk HBTs of A/sub E/=0.15/spl times/0.7 /spl mu/m/sup 2/ achieved ECL ring oscillator gate delay of 5.3 ps at Ics=1.2 mA. Self-heating effects on junction temperature and device performance were investigated with an emitter-width scaling effect. A low thermal budget HBT process sustains full compatibility with 0.13 /spl mu/m platforms for large scaled RF ICs.
{"title":"Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS","authors":"T. Hashimoto, Y. Nonaka, T. Tominari, H. Fujiwara, K. Tokunaga, M. Arai, S. Wada, T. Udo, M. Seto, M. Miura, H. Shimamoto, K. Washio, H. Tomioka","doi":"10.1109/IEDM.2003.1269182","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269182","url":null,"abstract":"200 GHz f/sub T/ SiGe HBTs and 80 nm gate CMOS were successfully integrated using the LP-CVD technique for selective SiGe epitaxial growth. Suppressing base resistance enabled us to achieve f/sub MAX/ of 227 GHz, corresponding to f/sub T/ of 201 GHz. Shrunk HBTs of A/sub E/=0.15/spl times/0.7 /spl mu/m/sup 2/ achieved ECL ring oscillator gate delay of 5.3 ps at Ics=1.2 mA. Self-heating effects on junction temperature and device performance were investigated with an emitter-width scaling effect. A low thermal budget HBT process sustains full compatibility with 0.13 /spl mu/m platforms for large scaled RF ICs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133456247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269363
B. Tavel, M. Bidaud, N. Emonet, D. Barge, N. Planes, H. Brut, D. Roy, J. Vildeuil, R. Difrenza, K. Rochereau, M. Denais, V. Huard, P. Llinares, S. Bruyère, C. Parthasarthy, N. Revil, R. Pantel, F. Guyader, L. Vishnubotla, K. Barla, F. Arnaud, P. Stolk, M. Woo
This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing with Ioff at 3nA/um, Vdd=0.9 V for 65 nm general purpose requirements. Extensive device characterization of the plasma nitride process is presented where the reduction in gate leakage offers benefits in terms of a 4/spl times/ reduction in static power, a 6% reduction in dynamic power consumption, comparative analog performance and improved reliability.
{"title":"Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform","authors":"B. Tavel, M. Bidaud, N. Emonet, D. Barge, N. Planes, H. Brut, D. Roy, J. Vildeuil, R. Difrenza, K. Rochereau, M. Denais, V. Huard, P. Llinares, S. Bruyère, C. Parthasarthy, N. Revil, R. Pantel, F. Guyader, L. Vishnubotla, K. Barla, F. Arnaud, P. Stolk, M. Woo","doi":"10.1109/IEDM.2003.1269363","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269363","url":null,"abstract":"This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing with Ioff at 3nA/um, Vdd=0.9 V for 65 nm general purpose requirements. Extensive device characterization of the plasma nitride process is presented where the reduction in gate leakage offers benefits in terms of a 4/spl times/ reduction in static power, a 6% reduction in dynamic power consumption, comparative analog performance and improved reliability.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133958800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269373
T. Krishnamohan, C. Jungemann, K. Saraswat
A novel, high performance sub-20 nm DMDG Si/Si/sub x/Ge/sub (1-x)//Si channel PMOSFET is proposed. Full-band Monte Carlo and 1D Poisson-Schrodinger simulations show a 43% increase in I/sub on/ and /spl sim/2/spl times/ increase in switching speeds at 35% lower power dissipation compared to conventional Si DGFETs. The cut-off frequencies are in excess of 1000 GHz making the device also very suitable for analog applications.
{"title":"A novel, very high performance, sub-20nm depletion-mode double-gate (DMDG) Si/Si/sub x/Ge/sub (1-x)//Si channel PMOSFET","authors":"T. Krishnamohan, C. Jungemann, K. Saraswat","doi":"10.1109/IEDM.2003.1269373","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269373","url":null,"abstract":"A novel, high performance sub-20 nm DMDG Si/Si/sub x/Ge/sub (1-x)//Si channel PMOSFET is proposed. Full-band Monte Carlo and 1D Poisson-Schrodinger simulations show a 43% increase in I/sub on/ and /spl sim/2/spl times/ increase in switching speeds at 35% lower power dissipation compared to conventional Si DGFETs. The cut-off frequencies are in excess of 1000 GHz making the device also very suitable for analog applications.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134119621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269279
Y. Nakahara, T. Fukai, M. Togo, S. Koyama, H. Morikuni, T. Matsuda, K. Sakamoto, A. Mineji, S. Fujiwara, Y. Kunimune, M. Nagase, T. Tamura, N. Onoda, S. Miyake, Y. Yama, T. Kudoh, M. Ikeda, Y. Yamagata, T. Yamamoto, K. Imai
We have developed a highly reliable 65 nm node CMOS technology, enabling a wide-range of Vdd operation, including overdrive mode. Process conditions are carefully optimized from the various aspects of device reliability and performance. We have utilized an oxynitride gate, arsenic-assisted phosphorus S/D ion-implantation, Ni-silicidation, stress controlled SiN layer process, and an offset-spacer process in order to improve the drive-current at low voltage operation and reliability at high voltage operation. The obtained drive-currents are 730/310 /spl mu/A//spl mu/m with an off-current of 80 nA//spl mu/m at a standard supply voltage of 0.9 V, and 1150/550 /spl mu/A//spl mu/m with an off-current of 180 nA//spl mu/m at an overdrive voltage of 1.2 V, while satisfying strict criteria for transistor reliability.
{"title":"A robust 65-nm node CMOS technology for wide-range Vdd operation","authors":"Y. Nakahara, T. Fukai, M. Togo, S. Koyama, H. Morikuni, T. Matsuda, K. Sakamoto, A. Mineji, S. Fujiwara, Y. Kunimune, M. Nagase, T. Tamura, N. Onoda, S. Miyake, Y. Yama, T. Kudoh, M. Ikeda, Y. Yamagata, T. Yamamoto, K. Imai","doi":"10.1109/IEDM.2003.1269279","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269279","url":null,"abstract":"We have developed a highly reliable 65 nm node CMOS technology, enabling a wide-range of Vdd operation, including overdrive mode. Process conditions are carefully optimized from the various aspects of device reliability and performance. We have utilized an oxynitride gate, arsenic-assisted phosphorus S/D ion-implantation, Ni-silicidation, stress controlled SiN layer process, and an offset-spacer process in order to improve the drive-current at low voltage operation and reliability at high voltage operation. The obtained drive-currents are 730/310 /spl mu/A//spl mu/m with an off-current of 80 nA//spl mu/m at a standard supply voltage of 0.9 V, and 1150/550 /spl mu/A//spl mu/m with an off-current of 180 nA//spl mu/m at an overdrive voltage of 1.2 V, while satisfying strict criteria for transistor reliability.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"327 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133104285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269303
Hang Hu, S. Ding, H.F. Lim, Chunxiang Zhu, M. Li, S.J. Kim, X.F. Yu, J.H. Chen, Y. F. Yong, B. Cho, D. Chan, S. Rustagi, M. Yu, C. Tung, A. Du, D. My, P.D. Foot, A. Chin, D. Kwong
In this paper, a high performance ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate metal-insulator-metal (MIM) capacitor is demonstrated for the first time with high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz to 20 GHz, low leakage current of 7.45/spl times/10/sup -9/ A/cm/sup 2/ at 2 V, low VCC (voltage coefficients of capacitance), and excellent reliability. The superior electrical properties and reliability suggest that the ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising material for MIM capacitors for Si RF and mixed signal IC applications.
{"title":"High performance ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors for RF and mixed signal IC applications","authors":"Hang Hu, S. Ding, H.F. Lim, Chunxiang Zhu, M. Li, S.J. Kim, X.F. Yu, J.H. Chen, Y. F. Yong, B. Cho, D. Chan, S. Rustagi, M. Yu, C. Tung, A. Du, D. My, P.D. Foot, A. Chin, D. Kwong","doi":"10.1109/IEDM.2003.1269303","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269303","url":null,"abstract":"In this paper, a high performance ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate metal-insulator-metal (MIM) capacitor is demonstrated for the first time with high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz to 20 GHz, low leakage current of 7.45/spl times/10/sup -9/ A/cm/sup 2/ at 2 V, low VCC (voltage coefficients of capacitance), and excellent reliability. The superior electrical properties and reliability suggest that the ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising material for MIM capacitors for Si RF and mixed signal IC applications.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116448422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269378
J. Zolper
The development of InP heterojunction bipolar transistors (HBTs) with the emitter feature size less than 0.25 /spl mu/m is described. The key technical challenges in scaling to this dimension are reviewed and the technology approaches are enumerated. The development of these super-scaled InP HBTs is expected to enable mixed signal circuits with clock speeds in excess of 100 GHz.
{"title":"Super-scaled InP HBTs for 150 GHz circuits","authors":"J. Zolper","doi":"10.1109/IEDM.2003.1269378","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269378","url":null,"abstract":"The development of InP heterojunction bipolar transistors (HBTs) with the emitter feature size less than 0.25 /spl mu/m is described. The key technical challenges in scaling to this dimension are reviewed and the technology approaches are enumerated. The development of these super-scaled InP HBTs is expected to enable mixed signal circuits with clock speeds in excess of 100 GHz.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115258142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269437
S. Humad, R. Abdolvand, G. K. Ho, Gianluca Piazza, Farrokh Ayazi
This paper reports on the design, implementation and characterization of high-frequency single crystal silicon (SCS) block resonators with piezoelectric electromechanical transducers. The resonators are fabricated on 4/spl mu/m thick SOI substrates and use sputtered ZnO as the piezo material. The centrally-supported blocks can operate in their first and higher order length extensional bulk modes with high quality factor (Q). The highest measured frequency is currently at 210 MHz with a Q of 4100 under vacuum, and the highest Q measured is 11,600 at 17 MHz. The uncompensated temperature coefficient of frequency (TCF) was measured to be -40ppm//spl deg/C and linear over the temperature range of 20-100/spl deg/C.
{"title":"High frequency micromechanical piezo-on-silicon block resonators","authors":"S. Humad, R. Abdolvand, G. K. Ho, Gianluca Piazza, Farrokh Ayazi","doi":"10.1109/IEDM.2003.1269437","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269437","url":null,"abstract":"This paper reports on the design, implementation and characterization of high-frequency single crystal silicon (SCS) block resonators with piezoelectric electromechanical transducers. The resonators are fabricated on 4/spl mu/m thick SOI substrates and use sputtered ZnO as the piezo material. The centrally-supported blocks can operate in their first and higher order length extensional bulk modes with high quality factor (Q). The highest measured frequency is currently at 210 MHz with a Q of 4100 under vacuum, and the highest Q measured is 11,600 at 17 MHz. The uncompensated temperature coefficient of frequency (TCF) was measured to be -40ppm//spl deg/C and linear over the temperature range of 20-100/spl deg/C.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115027468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269398
M. Lundstrom
This paper reviews our efforts to use theory and simulation to understand the device physics of nanoscale MOSFETs. The essential physics of MOSFETs at the scaling limit are discussed, and unresolved theoretical issues and technological ones that limit device performance and ultimate scaling are identified.
{"title":"Device physics at the scaling limit: what matters? [MOSFETs]","authors":"M. Lundstrom","doi":"10.1109/IEDM.2003.1269398","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269398","url":null,"abstract":"This paper reviews our efforts to use theory and simulation to understand the device physics of nanoscale MOSFETs. The essential physics of MOSFETs at the scaling limit are discussed, and unresolved theoretical issues and technological ones that limit device performance and ultimate scaling are identified.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"402 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124301146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269286
S. Samavedam, L. La, P. Tobin, B. White, C. Hobbs, L. Fonseca, A. Demkov, J. Schaeffer, E. Luckowski, A. Martínez, M. Raymond, D. Triyoso, D. Roan, V. Dhandapani, R. García, S. Anderson, K. Moore, H. Tseng, C. Capasso, O. Adetutu, D. Gilmer, W. Taylor, R. Hegde, J. Grant
We have examined the impact of small and systematic changes at the metal/dielectric interface on metal work-function and report on Fermi level pinning of TaN, TaSiN and TiN gates on SiO/sub 2/, Al/sub 2/O/sub 3/ and HfO/sub 2/ for the first time. The shifts in work-function agree in most cases with the MIGS theory if accurate theoretical parameters are used.
{"title":"Fermi level pinning with sub-monolayer MeOx and metal gates [MOSFETs]","authors":"S. Samavedam, L. La, P. Tobin, B. White, C. Hobbs, L. Fonseca, A. Demkov, J. Schaeffer, E. Luckowski, A. Martínez, M. Raymond, D. Triyoso, D. Roan, V. Dhandapani, R. García, S. Anderson, K. Moore, H. Tseng, C. Capasso, O. Adetutu, D. Gilmer, W. Taylor, R. Hegde, J. Grant","doi":"10.1109/IEDM.2003.1269286","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269286","url":null,"abstract":"We have examined the impact of small and systematic changes at the metal/dielectric interface on metal work-function and report on Fermi level pinning of TaN, TaSiN and TiN gates on SiO/sub 2/, Al/sub 2/O/sub 3/ and HfO/sub 2/ for the first time. The shifts in work-function agree in most cases with the MIGS theory if accurate theoretical parameters are used.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124391897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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