Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269278
D. Greenlaw, G. Burbach, T. Feudel, F. Feustel, K. Frohberg, F. Graetsch, G. Grasshoff, C. Hartig, T. Heller, K. Hempel, M. Horstmann, P. Huebler, R. Kirsch, S. Kruegel, E. Langer, A. Pawlowitsch, H. Ruelke, H. Schuehrer, R. Stephan, A. Wei, T. Werner, K. Wieczorek, M. Raab
SOI and low-k technologies are rapidly approaching production maturity. This paper highlights several challenges found when moving them from development to high-volume manufacturing. In overcoming these challenges in wafer processing and transistor development, we have achieved yield learning and performance enhancement rates equivalent to or better than conventional technologies.
{"title":"Taking SOI substrates and low-k dielectrics into high-volume microprocessor production","authors":"D. Greenlaw, G. Burbach, T. Feudel, F. Feustel, K. Frohberg, F. Graetsch, G. Grasshoff, C. Hartig, T. Heller, K. Hempel, M. Horstmann, P. Huebler, R. Kirsch, S. Kruegel, E. Langer, A. Pawlowitsch, H. Ruelke, H. Schuehrer, R. Stephan, A. Wei, T. Werner, K. Wieczorek, M. Raab","doi":"10.1109/IEDM.2003.1269278","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269278","url":null,"abstract":"SOI and low-k technologies are rapidly approaching production maturity. This paper highlights several challenges found when moving them from development to high-volume manufacturing. In overcoming these challenges in wafer processing and transistor development, we have achieved yield learning and performance enhancement rates equivalent to or better than conventional technologies.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121871106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269182
T. Hashimoto, Y. Nonaka, T. Tominari, H. Fujiwara, K. Tokunaga, M. Arai, S. Wada, T. Udo, M. Seto, M. Miura, H. Shimamoto, K. Washio, H. Tomioka
200 GHz f/sub T/ SiGe HBTs and 80 nm gate CMOS were successfully integrated using the LP-CVD technique for selective SiGe epitaxial growth. Suppressing base resistance enabled us to achieve f/sub MAX/ of 227 GHz, corresponding to f/sub T/ of 201 GHz. Shrunk HBTs of A/sub E/=0.15/spl times/0.7 /spl mu/m/sup 2/ achieved ECL ring oscillator gate delay of 5.3 ps at Ics=1.2 mA. Self-heating effects on junction temperature and device performance were investigated with an emitter-width scaling effect. A low thermal budget HBT process sustains full compatibility with 0.13 /spl mu/m platforms for large scaled RF ICs.
{"title":"Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS","authors":"T. Hashimoto, Y. Nonaka, T. Tominari, H. Fujiwara, K. Tokunaga, M. Arai, S. Wada, T. Udo, M. Seto, M. Miura, H. Shimamoto, K. Washio, H. Tomioka","doi":"10.1109/IEDM.2003.1269182","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269182","url":null,"abstract":"200 GHz f/sub T/ SiGe HBTs and 80 nm gate CMOS were successfully integrated using the LP-CVD technique for selective SiGe epitaxial growth. Suppressing base resistance enabled us to achieve f/sub MAX/ of 227 GHz, corresponding to f/sub T/ of 201 GHz. Shrunk HBTs of A/sub E/=0.15/spl times/0.7 /spl mu/m/sup 2/ achieved ECL ring oscillator gate delay of 5.3 ps at Ics=1.2 mA. Self-heating effects on junction temperature and device performance were investigated with an emitter-width scaling effect. A low thermal budget HBT process sustains full compatibility with 0.13 /spl mu/m platforms for large scaled RF ICs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133456247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269363
B. Tavel, M. Bidaud, N. Emonet, D. Barge, N. Planes, H. Brut, D. Roy, J. Vildeuil, R. Difrenza, K. Rochereau, M. Denais, V. Huard, P. Llinares, S. Bruyère, C. Parthasarthy, N. Revil, R. Pantel, F. Guyader, L. Vishnubotla, K. Barla, F. Arnaud, P. Stolk, M. Woo
This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing with Ioff at 3nA/um, Vdd=0.9 V for 65 nm general purpose requirements. Extensive device characterization of the plasma nitride process is presented where the reduction in gate leakage offers benefits in terms of a 4/spl times/ reduction in static power, a 6% reduction in dynamic power consumption, comparative analog performance and improved reliability.
{"title":"Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform","authors":"B. Tavel, M. Bidaud, N. Emonet, D. Barge, N. Planes, H. Brut, D. Roy, J. Vildeuil, R. Difrenza, K. Rochereau, M. Denais, V. Huard, P. Llinares, S. Bruyère, C. Parthasarthy, N. Revil, R. Pantel, F. Guyader, L. Vishnubotla, K. Barla, F. Arnaud, P. Stolk, M. Woo","doi":"10.1109/IEDM.2003.1269363","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269363","url":null,"abstract":"This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing with Ioff at 3nA/um, Vdd=0.9 V for 65 nm general purpose requirements. Extensive device characterization of the plasma nitride process is presented where the reduction in gate leakage offers benefits in terms of a 4/spl times/ reduction in static power, a 6% reduction in dynamic power consumption, comparative analog performance and improved reliability.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133958800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269437
S. Humad, R. Abdolvand, G. K. Ho, Gianluca Piazza, Farrokh Ayazi
This paper reports on the design, implementation and characterization of high-frequency single crystal silicon (SCS) block resonators with piezoelectric electromechanical transducers. The resonators are fabricated on 4/spl mu/m thick SOI substrates and use sputtered ZnO as the piezo material. The centrally-supported blocks can operate in their first and higher order length extensional bulk modes with high quality factor (Q). The highest measured frequency is currently at 210 MHz with a Q of 4100 under vacuum, and the highest Q measured is 11,600 at 17 MHz. The uncompensated temperature coefficient of frequency (TCF) was measured to be -40ppm//spl deg/C and linear over the temperature range of 20-100/spl deg/C.
{"title":"High frequency micromechanical piezo-on-silicon block resonators","authors":"S. Humad, R. Abdolvand, G. K. Ho, Gianluca Piazza, Farrokh Ayazi","doi":"10.1109/IEDM.2003.1269437","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269437","url":null,"abstract":"This paper reports on the design, implementation and characterization of high-frequency single crystal silicon (SCS) block resonators with piezoelectric electromechanical transducers. The resonators are fabricated on 4/spl mu/m thick SOI substrates and use sputtered ZnO as the piezo material. The centrally-supported blocks can operate in their first and higher order length extensional bulk modes with high quality factor (Q). The highest measured frequency is currently at 210 MHz with a Q of 4100 under vacuum, and the highest Q measured is 11,600 at 17 MHz. The uncompensated temperature coefficient of frequency (TCF) was measured to be -40ppm//spl deg/C and linear over the temperature range of 20-100/spl deg/C.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115027468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269378
J. Zolper
The development of InP heterojunction bipolar transistors (HBTs) with the emitter feature size less than 0.25 /spl mu/m is described. The key technical challenges in scaling to this dimension are reviewed and the technology approaches are enumerated. The development of these super-scaled InP HBTs is expected to enable mixed signal circuits with clock speeds in excess of 100 GHz.
{"title":"Super-scaled InP HBTs for 150 GHz circuits","authors":"J. Zolper","doi":"10.1109/IEDM.2003.1269378","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269378","url":null,"abstract":"The development of InP heterojunction bipolar transistors (HBTs) with the emitter feature size less than 0.25 /spl mu/m is described. The key technical challenges in scaling to this dimension are reviewed and the technology approaches are enumerated. The development of these super-scaled InP HBTs is expected to enable mixed signal circuits with clock speeds in excess of 100 GHz.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115258142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269353
R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White
The first functional 6 V, 4 Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90 nm and 0.25 /spl mu/m process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded flash at the 90 nm node and beyond.
{"title":"A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory","authors":"R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White","doi":"10.1109/IEDM.2003.1269353","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269353","url":null,"abstract":"The first functional 6 V, 4 Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90 nm and 0.25 /spl mu/m process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded flash at the 90 nm node and beyond.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122659234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269345
Y. Ando, Y. Okamoto, K. Hataya, T. Nakayama, H. Miyamoto, T. Inoue, M. Kuzuhara
A recessed-gate structure was introduced to improve transconductance (gm) and gain characteristics in AlGaN/GaN field-plate (FP) FETs. A maximum gm was improved from 130 to 200 mS/mm by introducing gate recess. Recessed FP-FETs exhibited 3-7 dB higher linear gain as compared with planar FP-FETs. A 1 mm-wide recessed FP-FET biased at a drain voltage of 66 V demonstrated 12.0 W output power, 21.2 dB linear gain, and 48.8 % power added efficiency at 2 GHz. To our knowledge, the power density of 12.0 W/mm is the highest ever achieved for GaN-based FETs.
{"title":"12 W/mm recessed-gate AlGaN/GaN heterojunction field-plate FET","authors":"Y. Ando, Y. Okamoto, K. Hataya, T. Nakayama, H. Miyamoto, T. Inoue, M. Kuzuhara","doi":"10.1109/IEDM.2003.1269345","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269345","url":null,"abstract":"A recessed-gate structure was introduced to improve transconductance (gm) and gain characteristics in AlGaN/GaN field-plate (FP) FETs. A maximum gm was improved from 130 to 200 mS/mm by introducing gate recess. Recessed FP-FETs exhibited 3-7 dB higher linear gain as compared with planar FP-FETs. A 1 mm-wide recessed FP-FET biased at a drain voltage of 66 V demonstrated 12.0 W output power, 21.2 dB linear gain, and 48.8 % power added efficiency at 2 GHz. To our knowledge, the power density of 12.0 W/mm is the highest ever achieved for GaN-based FETs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126454190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269317
J. Kedzierski, D. Boyd, Ying Zhang, M. Steen, F. Jamin, J. Benedict, M. Ieong, W. Haensch
Thin-body fully depleted silicon on insulator (FDSOI) devices with NiSi metal gates were fabricated with gate lengths down to 20 nm. Specific issues in the integration of the NiSi-gated FDSOI devices were investigated, in particular: gate CMP, the phase stability of the nickel silicide, and parasitic resistance.
{"title":"Issues in NiSi-gated FDSOI device integration","authors":"J. Kedzierski, D. Boyd, Ying Zhang, M. Steen, F. Jamin, J. Benedict, M. Ieong, W. Haensch","doi":"10.1109/IEDM.2003.1269317","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269317","url":null,"abstract":"Thin-body fully depleted silicon on insulator (FDSOI) devices with NiSi metal gates were fabricated with gate lengths down to 20 nm. Specific issues in the integration of the NiSi-gated FDSOI devices were investigated, in particular: gate CMP, the phase stability of the nickel silicide, and parasitic resistance.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125714927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269165
S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, N. Hirashita, T. Maeda
This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.
{"title":"Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs","authors":"S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, N. Hirashita, T. Maeda","doi":"10.1109/IEDM.2003.1269165","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269165","url":null,"abstract":"This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130277886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269394
N. Sato, S. Shigematsu, H. Morimura, M. Yano, K. Kudou, T. Kamei, K. Machida
This paper describes a novel structure of MEMS (microelectromechanical systems) and its fabrication process on the surface of the MEMS fingerprint sensor that works as an interface between a finger and the sensor. In order to detect fingerprints, whether a finger is soft or hard, novel T-shaped protrusions are proposed. The structure was fabricated by etching a sacrificial layer on the cavity structure that has a pair of electrodes. Structural calculations and experimental measurements showed that the proposed sensor bends the electrode most efficiently. This enables fingerprint detection regardless of finger elasticity, and enhances sensitivity for various finger surface conditions.
{"title":"High sensitive structure and its fabrication process for MEMS fingerprint sensor to various fingers","authors":"N. Sato, S. Shigematsu, H. Morimura, M. Yano, K. Kudou, T. Kamei, K. Machida","doi":"10.1109/IEDM.2003.1269394","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269394","url":null,"abstract":"This paper describes a novel structure of MEMS (microelectromechanical systems) and its fabrication process on the surface of the MEMS fingerprint sensor that works as an interface between a finger and the sensor. In order to detect fingerprints, whether a finger is soft or hard, novel T-shaped protrusions are proposed. The structure was fabricated by etching a sacrificial layer on the cavity structure that has a pair of electrodes. Structural calculations and experimental measurements showed that the proposed sensor bends the electrode most efficiently. This enables fingerprint detection regardless of finger elasticity, and enhances sensitivity for various finger surface conditions.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128696299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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