Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269295
Muhammad A. Alam
The physics of frequency-dependent shift in transistor parameters due to negative bias temperature instability (NBTI) is examined using numerical and analytical solutions of the reaction-diffusion model (R-D). We find that the magnitude of NBTI degradation depends on frequency through a complex interplay of reaction- and diffusion-limited trap generation processes, and that the intrinsic symmetry of the stress and relaxation phases can account for the relatively weak frequency dependence of the NBTI phenomenon. We also show that the model is consistent with the broad features of the dynamic NBTI problem and can provide an adequate framework to discuss NBTI issues.
{"title":"A critical examination of the mechanics of dynamic NBTI for PMOSFETs","authors":"Muhammad A. Alam","doi":"10.1109/IEDM.2003.1269295","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269295","url":null,"abstract":"The physics of frequency-dependent shift in transistor parameters due to negative bias temperature instability (NBTI) is examined using numerical and analytical solutions of the reaction-diffusion model (R-D). We find that the magnitude of NBTI degradation depends on frequency through a complex interplay of reaction- and diffusion-limited trap generation processes, and that the intrinsic symmetry of the stress and relaxation phases can account for the relatively weak frequency dependence of the NBTI phenomenon. We also show that the model is consistent with the broad features of the dynamic NBTI problem and can provide an adequate framework to discuss NBTI issues.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127288125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269349
Y. Wu, M. Moore, A. Saxler, P. Smith, P. Chavarkar, P. Parikh
Sub-0.2-/spl mu/m AlGaN/GaN HEMTs were successfully scaled to 1.05 mm gate-width with minor gain reduction. On-chip single-stage amplifiers exhibited gains of 8 dB and 7.5 dB, as well as output powers of 3.6 W and 3.5 W, at 30 GHz and 35 GHz, respectively. This multi-watt output power at millimeter-wave frequencies well exceeded previous state-of-the-art for a GaN HEMT and is comparable to that from 6-7 times larger GaAs-based devices.
{"title":"3.5-watt AlGaN/GaN HEMTs and amplifiers at 35 GHz","authors":"Y. Wu, M. Moore, A. Saxler, P. Smith, P. Chavarkar, P. Parikh","doi":"10.1109/IEDM.2003.1269349","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269349","url":null,"abstract":"Sub-0.2-/spl mu/m AlGaN/GaN HEMTs were successfully scaled to 1.05 mm gate-width with minor gain reduction. On-chip single-stage amplifiers exhibited gains of 8 dB and 7.5 dB, as well as output powers of 3.6 W and 3.5 W, at 30 GHz and 35 GHz, respectively. This multi-watt output power at millimeter-wave frequencies well exceeded previous state-of-the-art for a GaN HEMT and is comparable to that from 6-7 times larger GaAs-based devices.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132169132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269334
M. Mergens, C. Russ, K. Verhaege, J. Armer, P. Jozwiak, R. Mohn, B. Keppens, C. S. Trinh
A novel diode-triggered SCR (DTSCR) ESD protection element is introduced for low-voltage application (signal, supply voltage /spl les/1.8 V) and extremely narrow ESD design margins. Trigger voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultra-sensitive circuit nodes, such as SiGe HBT bases (e.g. f/sub Tmax/=45 GHz in BiCMOS-0.35 /spl mu/m LNA input) and thin gate-oxides (e.g. tox=1.7 nm in CMOS-0.09 /spl mu/m input). SCR integration is possible based on CMOS devices or can alternatively be formed by high-speed SiGe HBTs.
{"title":"Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides","authors":"M. Mergens, C. Russ, K. Verhaege, J. Armer, P. Jozwiak, R. Mohn, B. Keppens, C. S. Trinh","doi":"10.1109/IEDM.2003.1269334","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269334","url":null,"abstract":"A novel diode-triggered SCR (DTSCR) ESD protection element is introduced for low-voltage application (signal, supply voltage /spl les/1.8 V) and extremely narrow ESD design margins. Trigger voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultra-sensitive circuit nodes, such as SiGe HBT bases (e.g. f/sub Tmax/=45 GHz in BiCMOS-0.35 /spl mu/m LNA input) and thin gate-oxides (e.g. tox=1.7 nm in CMOS-0.09 /spl mu/m input). SCR integration is possible based on CMOS devices or can alternatively be formed by high-speed SiGe HBTs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130910109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269305
D. Schmidt, P. Pianetta
We show a novel color filter system that can be implemented in a standard CMOS process without any additional chemicals and processing, using standard CMOS metals like aluminum. The filter uses sub-wavelength aperture and grating arrays allowing some light wavelengths through while blocking others. Furthermore, we show an integrated photo-detector, both as a standard junction diode and an MSM diode which combines the filters and detector into the simplest color imaging system. The experimental data is explained with simulations and electromagnetic theory.
{"title":"Color filtering metallization for optoelectronic 100nm CMOS circuits","authors":"D. Schmidt, P. Pianetta","doi":"10.1109/IEDM.2003.1269305","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269305","url":null,"abstract":"We show a novel color filter system that can be implemented in a standard CMOS process without any additional chemicals and processing, using standard CMOS metals like aluminum. The filter uses sub-wavelength aperture and grating arrays allowing some light wavelengths through while blocking others. Furthermore, we show an integrated photo-detector, both as a standard junction diode and an MSM diode which combines the filters and detector into the simplest color imaging system. The experimental data is explained with simulations and electromagnetic theory.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130997752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269320
M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D'Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, H. Ng
A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy. CMOS devices with physical gate oxide thickness of 1.2 nm have been demonstrated, with substantial enhancement of pFET drive current at L/sub poly//spl les/80 nm.
{"title":"High performance CMOS fabricated on hybrid substrate with different crystal orientations","authors":"M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D'Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, H. Ng","doi":"10.1109/IEDM.2003.1269320","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269320","url":null,"abstract":"A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy. CMOS devices with physical gate oxide thickness of 1.2 nm have been demonstrated, with substantial enhancement of pFET drive current at L/sub poly//spl les/80 nm.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123334888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269316
C. O. Chui, Hyoungsub Kim, P. McIntyre, K. Saraswat
A simple and novel self-aligned gate-last MOS process integrating metal gates and high-k dielectrics on Ge has been demonstrated. Improved surface passivation for excellent gate dielectric and field isolation, and n-type dopant incorporation with high surface concentration and shallow junctions has been developed. Conventional VLSI type Ge n-MOSFETs have been fabricated.
{"title":"A germanium NMOSFET process integrating metal gate and improved hi-/spl kappa/ dielectrics","authors":"C. O. Chui, Hyoungsub Kim, P. McIntyre, K. Saraswat","doi":"10.1109/IEDM.2003.1269316","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269316","url":null,"abstract":"A simple and novel self-aligned gate-last MOS process integrating metal gates and high-k dielectrics on Ge has been demonstrated. Improved surface passivation for excellent gate dielectric and field isolation, and n-type dopant incorporation with high surface concentration and shallow junctions has been developed. Conventional VLSI type Ge n-MOSFETs have been fabricated.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121411218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269418
L. Tiemeijer, R. Havens, R. de Kort, Y. Bouttement, P. Deixler, M. Ryczek
A highly accurate predictive inductor model for integrated symmetric inductors with center tap and patterned ground shield is presented. This model is based on a modified Greenhouse algorithm where current crowding due to skin and proximity effects is included by considering the spread in parallel sub-loop inductances. This scalable symmetrical inductor equivalent circuit model covers all operating conditions, and yet only requires dimensions and back-end layer thicknesses. We have verified this scalable model for a large number of inductors from three industrial IC processes and found excellent agreement with measured inductances, Q-factors, and resonance frequencies.
{"title":"Predictive spiral inductor compact model for frequency and time domain","authors":"L. Tiemeijer, R. Havens, R. de Kort, Y. Bouttement, P. Deixler, M. Ryczek","doi":"10.1109/IEDM.2003.1269418","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269418","url":null,"abstract":"A highly accurate predictive inductor model for integrated symmetric inductors with center tap and patterned ground shield is presented. This model is based on a modified Greenhouse algorithm where current crowding due to skin and proximity effects is included by considering the spread in parallel sub-loop inductances. This scalable symmetrical inductor equivalent circuit model covers all operating conditions, and yet only requires dimensions and back-end layer thicknesses. We have verified this scalable model for a large number of inductors from three industrial IC processes and found excellent agreement with measured inductances, Q-factors, and resonance frequencies.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123133901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269371
J. Fossum, M. Chowdhury, V. Trivedi, T. King, Y. Choi, J. An, B. Yu
An array of measured device data, a numerical device simulator, and a process/physics-based compact model are used to gain new and important physical insights on nanoscale FinFETs with undoped thin-fin bodies. The insights, which include unavoidable/needed gate underlap, bias-dependent effective channel length, and non-ohmic fin-extension voltage drops, reveal the significance of gate positioning on, and source/drain doping profile in, the thin fin, and imply novel compact modeling that will be needed for optimal design of nonclassical CMOS circuits.
{"title":"Physical insights on design and modeling of nanoscale FinFETs","authors":"J. Fossum, M. Chowdhury, V. Trivedi, T. King, Y. Choi, J. An, B. Yu","doi":"10.1109/IEDM.2003.1269371","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269371","url":null,"abstract":"An array of measured device data, a numerical device simulator, and a process/physics-based compact model are used to gain new and important physical insights on nanoscale FinFETs with undoped thin-fin bodies. The insights, which include unavoidable/needed gate underlap, bias-dependent effective channel length, and non-ohmic fin-extension voltage drops, reveal the significance of gate positioning on, and source/drain doping profile in, the thin fin, and imply novel compact modeling that will be needed for optimal design of nonclassical CMOS circuits.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126036925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269369
K. Babich, N. Fukiage, A. Mahorowala, S. Halle, T. Bunner, D. Pfeiffer, H. Mochiki, S. Ashigaki, A. Xia, M. Angelopoulos
Novel silicon carbide (Si:C:H) and silicon oxycarbide (Si:C:O:H) based materials, prepared by plasma-enhanced chemical vapor deposition (PECVD), have been developed with dual anti-reflective (ARC) and hardmask properties thus enabling the use of thin resists for high resolution device pattering. High quality 25 nm polysilicon gates and ultra-high aspect ratio (>65:1) 8 /spl mu/m deep trench (DT) features in Si have been fabricated with this ARC/hardmask technology.
{"title":"A novel graded antireflective coating with built-in hardmask properties enabling 65nm and below CMOS device patterning","authors":"K. Babich, N. Fukiage, A. Mahorowala, S. Halle, T. Bunner, D. Pfeiffer, H. Mochiki, S. Ashigaki, A. Xia, M. Angelopoulos","doi":"10.1109/IEDM.2003.1269369","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269369","url":null,"abstract":"Novel silicon carbide (Si:C:H) and silicon oxycarbide (Si:C:O:H) based materials, prepared by plasma-enhanced chemical vapor deposition (PECVD), have been developed with dual anti-reflective (ARC) and hardmask properties thus enabling the use of thin resists for high resolution device pattering. High quality 25 nm polysilicon gates and ultra-high aspect ratio (>65:1) 8 /spl mu/m deep trench (DT) features in Si have been fabricated with this ARC/hardmask technology.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115261757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269246
A. Hara, M. Takei, K. Yoshino, F. Takeuchi, M. Chida, N. Sasaki
Self-aligned top and bottom metal double gate (SAMDG) low-temperature polycrystalline silicon (poly-Si) thin film transistors (TFTs) were fabricated at 550/spl deg/C using the diode pumped solid state (DPSS) CW laser lateral crystallization (CLC) method, on non-alkali glass. The current drivability of these TFTs is eight or nine times as large as that of conventional excimer laser crystallized (ELC) poly-Si TFTs. It was confirmed that the extreme high performance of SAMDG CLC poly-Si TFT was maintained for gate length of 2.0 /spl mu/m.
{"title":"Self-aligned top and bottom metal double gate low temperature poly-Si TFT fabricated at 550/spl deg/C on non-alkali glass substrate by using DPSS CW laser lateral crystallization method","authors":"A. Hara, M. Takei, K. Yoshino, F. Takeuchi, M. Chida, N. Sasaki","doi":"10.1109/IEDM.2003.1269246","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269246","url":null,"abstract":"Self-aligned top and bottom metal double gate (SAMDG) low-temperature polycrystalline silicon (poly-Si) thin film transistors (TFTs) were fabricated at 550/spl deg/C using the diode pumped solid state (DPSS) CW laser lateral crystallization (CLC) method, on non-alkali glass. The current drivability of these TFTs is eight or nine times as large as that of conventional excimer laser crystallized (ELC) poly-Si TFTs. It was confirmed that the extreme high performance of SAMDG CLC poly-Si TFT was maintained for gate length of 2.0 /spl mu/m.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125169266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：