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15th Annual GaAs IC Symposium最新文献

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Spray etch recess process for high yield analog GaAs MMICs 高成品率模拟GaAs mmic的喷蚀凹槽工艺
Pub Date : 1993-10-10 DOI: 10.1109/GAAS.1993.394443
N. Ebrahimi, Kuorsiung Li, P. Fowler
Gate recess spray etch and bath-immersion etch processes are compared in the manufacturing of high yield analog GaAs MMICs. Detailed experiment work together with statistical analysis have determined the superiority of the spray etch process over the bath-immersion process. Optimization and implementation of the spray etch process in a three-inch GaAs wafer fabrication line are discussed. Improvements in device current uniformity, circuit RF test yield, and overall yield are demonstrated for the spray etch recess process, in the production of GaAs MMICs.<>
比较了栅极凹槽喷蚀和浸蚀两种工艺在制备高良率模拟砷化镓微集成电路中的应用。详细的实验工作和统计分析确定了喷雾蚀刻工艺比浸浴工艺的优越性。讨论了三英寸砷化镓晶圆生产线喷蚀工艺的优化与实现。在器件电流均匀性、电路RF测试良率和总体良率方面的改进,证明了在GaAs mmic生产中采用喷蚀凹槽工艺。
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引用次数: 2
Digital dynamic frequency dividers for broadband application up to 60 GHz 数字动态分频器宽带应用高达60 GHz
Pub Date : 1993-10-10 DOI: 10.1109/GAAS.1993.394492
A. Thiede, M. Berroth, P. Tasker, M. Schlechtweg, J. Seibel, B. Raynor, A. Hulsmann, K. Kohler, W. Bronner
A broadband dynamic frequency divider based on pseudomorphic Al/sub 0.2/Ga/sub 0.8/As/In/sub 0.25/Ga/sub 0.75/As MODFETs and passive loads is presented. Stable operation from 28 GHz up to 51 GHz with a power consumption of 440 mW could be shown. SPICE network simulation predicts operation in the 35 GHz - 60 GHz range for a divider circuit using an advanced E/D AlGaAs/InGaAs MODFET process.<>
提出了一种基于伪晶Al/sub 0.2/Ga/sub 0.8/As/In/sub 0.25/Ga/sub 0.75/As modfet和无源负载的宽带动态分频器。可以显示在28 GHz至51 GHz范围内稳定运行,功耗为440 mW。SPICE网络仿真预测使用先进的E/D AlGaAs/InGaAs MODFET工艺的分频电路在35 GHz - 60 GHz范围内工作。
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引用次数: 4
MMIC 20 GHz low-noise and 44 GHz power amplifiers for phased array communication antennas designed for manufacturability MMIC 20 GHz低噪声和44 GHz功率放大器,用于相控阵通信天线的可制造性设计
Pub Date : 1993-10-10 DOI: 10.1109/GAAS.1993.394432
B. Hughes, J. Orr, G. Martin
20 GHz low-noise and 44 GHz power MMIC amplifiers have been developed that could improve the manufacturability and cost of MILSTAR EHF phased array communication antennas. The six-stage power amplifier has 32.7 dB gain with 16.7 dBm output power and 17% power added efficiency. The chip measures 1.79 mm/sup 2/ and operates off two supplies. The four-stage LNA demonstrates 26 dB gain with 2.2 dB noise figure and 15 dB return loss. The LNA chip measures 1.18 mm/sup 2/ and operates off a single supply.<>
研制了20 GHz低噪声和44 GHz功率MMIC放大器,可提高MILSTAR EHF相控阵通信天线的可制造性和成本。该六级功率放大器的增益为32.7 dB,输出功率为16.7 dBm,功率增加效率为17%。该芯片的尺寸为1.79 mm/sup 2/,使用两个电源。4级LNA的增益为26db,噪声系数为2.2 dB,回波损耗为15db。LNA芯片的尺寸为1.18 mm/sup 2/,采用单电源供电。
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引用次数: 3
A V-band monolithic InP HEMT down converter [for satellite communication] v波段单片InP HEMT下变频器[卫星通信用]
Pub Date : 1993-10-10 DOI: 10.1109/GAAS.1993.394467
K. Chang, H. Wang, R. Lai, D. Lo, J. Berenz
The authors report a monolithic V-band downconverter implemented using 0.1 /spl mu/m InAlAs-InGaAs-InP HEMT technology. The 5.0/spl times/3.0 mm/sup 2/ MMIC contains a V-band three-stage low noise amplifier, a single-balanced diode mixer, and an IF distributed amplifier. The noise figure of the LNA is less than 3 dB with an associated gain of more than 24 dB between 56 and 64 GHz. The complete downconverter demonstrates a conversion gain of more than 21 dB for the same frequency range with an LO drive of 10 dBm at 54 GHz. Total DC power consumption of the downconverter is less than 32 mW.<>
作者报告了一种采用0.1 /spl mu/m InAlAs-InGaAs-InP HEMT技术实现的单片v波段下变频器。5.0/spl倍/3.0 mm/sup 2/ MMIC包含一个v波段三级低噪声放大器,一个单平衡二极管混频器和一个中频分布式放大器。在56 ~ 64 GHz范围内,LNA的噪声系数小于3 dB,相关增益大于24 dB。完整的下变频器在相同的频率范围内具有超过21 dB的转换增益,在54 GHz时具有10 dBm的LO驱动。下变频器直流总功耗小于32mw。
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引用次数: 11
F-RISC/I: A 32 bit RISC processor implemented in GaAs HMESFET SBFL F-RISC/I:在GaAs HMESFET sffl上实现的32位RISC处理器
Pub Date : 1993-10-10 DOI: 10.1109/GAAS.1993.394482
C. K. Tien, K. Lewis, R. Philhower, H.J. Greub, J. McDonald
F-RISC/I, a reduced version of a fast RISC microprocessor, has been designed and fabricated using IBM's SBFL standard cell library and Rockwell International's 0.7 /spl mu/m HMESFET technology. F-RISC/I was designed in six months by two designers using commercial design automation tools. Simulations have shown 400 MHz operation. The chip contains 92,340 transistors on a 7/spl times/7 mm/sup 2/ die and dissipates 3.8 W. The F-RISC/I processor exemplifies the CPU architecture, circuit design, and testing developed to fully take advantage of GaAs technology for high speed computing.<>
F-RISC/I是快速RISC微处理器的简化版本,使用IBM的SBFL标准单元库和罗克韦尔国际公司的0.7 /spl mu/m HMESFET技术设计和制造。F-RISC/I由两名设计师使用商业设计自动化工具在六个月内设计完成。仿真显示了400mhz的工作频率。该芯片在7/spl × 7 mm/sup /芯片上包含92340个晶体管,功耗为3.8 W。F-RISC/I处理器体现了CPU架构,电路设计和测试开发,以充分利用GaAs技术进行高速计算。
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引用次数: 1
A dual-channel Ku-band DBS downconverter 双通道ku波段DBS下变频器
Pub Date : 1993-10-10 DOI: 10.1109/GAAS.1993.394462
P. Bacon, E. Olsen, B. Cole, Y. Tajima, D. Kaczman
A dual-channel downconverter has been developed targeted for the Direct Broadcast Satellite Television market. In the established European and the developing North American DBS markets, the system design utilizes dual-polarized signals for program transmission. To reduce the receiver complexity it is desirable to have a monolithic dual-channel downconverter that minimizes parts count and reduces assembly/manufacturing costs while maintaining, and perhaps improving total system performance. This was the motivation for developing a GaAs MMIC dual-channel downconverter.<>
针对卫星电视直播市场,研制了一种双通道下变频器。在成熟的欧洲和发展中的北美星展市场,系统设计采用双极化信号进行节目传输。为了降低接收机的复杂性,最好采用单片双通道下变频器,以最大限度地减少零件数量,降低组装/制造成本,同时保持并可能提高总体系统性能。这就是开发GaAs MMIC双通道下变频器的动机。
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引用次数: 9
Delay modeling for GaAs DCFL circuits GaAs DCFL电路的延迟建模
Pub Date : 1993-10-10 DOI: 10.1109/GAAS.1993.394498
A. I. Kayssi, K. Sakallah
A timing macromodel for GaAs DCFL logic gates is derived. It circulates the delay of a gate as a function of such parameters as transistor sizes, capacitive loading, fanout, and input transition time. For NOR gates, the simultaneous switching of two inputs is also considered. Calculations based on the derived macromodel show excellent agreement with circuit simulation.<>
推导了砷化镓DCFL逻辑门的时序宏模型。它循环栅极的延迟作为诸如晶体管尺寸、电容负载、风扇输出和输入转换时间等参数的函数。对于NOR门,还考虑了两个输入同时切换。基于所推导的宏模型的计算结果与电路仿真结果非常吻合
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引用次数: 4
GaAs HBT 0.75-5 GHz multifunctional microwave-analog variable gain amplifier GaAs HBT 0.75-5 GHz多功能微波模拟变增益放大器
Pub Date : 1993-10-10 DOI: 10.1109/GAAS.1993.394461
K. Kobayashi, K. Ip, A. Oki, D. Umemoto, Sahimwn Claxton, Matt Pope, Jerry Wiltz
The authors report on a GaAs HBT three-stage variable gain amplifier operating over a 0.75-5 GHz frequency band. The amplifier is broken up into a single-ended HBT LNA pre-amp, an analog current steering differential cascode cell for variable gain control, and a differential amplifier output stage. The pre-amp is required to reduce the inherently noisy differential cascode stage, and an output differential amplifier is used for drive capability and differential to single-ended conversion. The VGA has a maximum gain of 23.8 dB, an IP3 >18 dBm, and a noise figure of 6.5 dB. The variable gain control range is >35 dB. This chip demonstrates the versatility of HBT IC technology which can integrate digital, analog, and microwave circuit functions to achieve high performance in a single monolithic chip.<>
作者报道了一种工作在0.75- 5ghz频段的GaAs HBT三级可变增益放大器。该放大器分为单端HBT LNA前置放大器、用于可变增益控制的模拟电流转向差分级联编码单元和差分放大器输出级。需要前置放大器来降低差分级联的固有噪声,输出差分放大器用于驱动能力和差分到单端转换。VGA的最大增益为23.8 dB, IP3 >18 dBm,噪声系数为6.5 dB。可变增益控制范围> 35db。该芯片展示了HBT集成电路技术的多功能性,它可以将数字、模拟和微波电路功能集成在一个单片芯片上,从而实现高性能。
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引用次数: 34
An ASIC chipset for optical communications 用于光通信的ASIC芯片组
Pub Date : 1993-10-10 DOI: 10.1109/GAAS.1993.394446
E.S. Chan, L. Lawrence
A transmitter/receiver chipset has been implemented in GaAs for a 1.3 Gbps optical communications link through free space media. The link encoding is Q=4 pulse position modulation (PPM), which economizes the power requirement of the lasers. The chipset offers an unprecedented integration of transmitter and receiver functions for this type of application.<>
一种用于通过自由空间介质的1.3 Gbps光通信链路的发送/接收芯片组已在GaAs中实现。链路编码为Q=4脉冲位置调制(PPM),节省了激光器的功率需求。该芯片组为这种类型的应用提供了前所未有的发射器和接收器功能集成。
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引用次数: 0
A VHF switched-capacitor band-pass filter using GaAs MESFET IC technology 采用GaAs MESFET集成电路技术的甚高频开关电容带通滤波器
Pub Date : 1993-10-10 DOI: 10.1109/GAAS.1993.394460
P. Katzin, B. Bedard
The authors describe the design of a narrowband, high-frequency GaAs IC switched-capacitor filter-based on a commutating RC circuit topology. They present measured performance of a two-section band-pass filter circuit with a center-frequency tunable to over 220 MHz with a -3 dB bandwidth of less than 2.6 MHz. The tuning frequency is controlled by a single-phase external clock signal at about two or four times the center-frequency, from which four-phase clock switching signals are generated on-chip. These results demonstrate that the broad tuning range and frequency stability of switched-capacitor filters is achievable well into the VHF frequency region. Such circuits can provide higher level of integration for fixed-frequency filters, clock recovery circuits, and for agile filtering in broadband communications and radar systems.<>
介绍了一种基于整流RC电路拓扑结构的窄带高频GaAs集成电路开关电容滤波器的设计。他们介绍了一种两段带通滤波器电路的实测性能,该电路的中心频率可调到220 MHz以上,-3 dB带宽小于2.6 MHz。调谐频率由一个单相外部时钟信号控制,其频率约为中心频率的两倍或四倍,由此产生芯片上的四相时钟开关信号。结果表明,在甚高频频段,开关电容滤波器具有较宽的调谐范围和频率稳定性。这种电路可以为固定频率滤波器、时钟恢复电路以及宽带通信和雷达系统中的敏捷滤波提供更高水平的集成。
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15th Annual GaAs IC Symposium
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