Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394429
M. Funabashi, K. Hosoya, K. Ohata, K. Onda, N. Iwata, M. Kuzuhara
High gain V-band medium power MMIC amplifiers have been successfully demonstrated using 0.15 /spl mu/m T-shaped gate AlGaAs/InGaAs heterojunction FETs. Optimization of the FET achieved high f/sub max/ of 227 GHz with high gate breakdown voltage of -13 V. A single-stage 65 GHz-band amplifier has exhibited 8.7 dB small signal gain with the 1 dB-gain-down bandwidth of 2 GHz. A single-stage 60 GHz-band amplifier has achieved 8.4 dB gain with 3 GHz bandwidth and good input and output impedance matching. The output power of 37.2 mW with high power-added-efficiency of 25.6% at 61.2 GHz has been obtained at 3 V drain bias.<>
{"title":"High gain V-band heterojunction FET MMIC power amplifiers","authors":"M. Funabashi, K. Hosoya, K. Ohata, K. Onda, N. Iwata, M. Kuzuhara","doi":"10.1109/GAAS.1993.394429","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394429","url":null,"abstract":"High gain V-band medium power MMIC amplifiers have been successfully demonstrated using 0.15 /spl mu/m T-shaped gate AlGaAs/InGaAs heterojunction FETs. Optimization of the FET achieved high f/sub max/ of 227 GHz with high gate breakdown voltage of -13 V. A single-stage 65 GHz-band amplifier has exhibited 8.7 dB small signal gain with the 1 dB-gain-down bandwidth of 2 GHz. A single-stage 60 GHz-band amplifier has achieved 8.4 dB gain with 3 GHz bandwidth and good input and output impedance matching. The output power of 37.2 mW with high power-added-efficiency of 25.6% at 61.2 GHz has been obtained at 3 V drain bias.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133114961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394448
M. Kasashima, K. Tanaka, H. Yamazaki, H. Nakamura
A Gilbert-cell mixer IC for a 2.5 Gb/s coherent optical fiber transmission system using 0.25 /spl mu/m gate GaAs MESFETs has been developed. The mixer IC operates 1-8.5 GHz RF 3 dB bandwidth and an ideal square-law characteristic was obtained around input level of -15 dBm to 0 dBm. The mixer IC was actually operated in a 2.5 Gb/s coherent optical transmission test system, and sensitivity of -41.3 dBm for 10/sup -11/ bit-error-rate was obtained.<>
{"title":"2 - 8 GHz Gilbert-cell mixer IC for 2.5 Gb/s coherent optical transmission","authors":"M. Kasashima, K. Tanaka, H. Yamazaki, H. Nakamura","doi":"10.1109/GAAS.1993.394448","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394448","url":null,"abstract":"A Gilbert-cell mixer IC for a 2.5 Gb/s coherent optical fiber transmission system using 0.25 /spl mu/m gate GaAs MESFETs has been developed. The mixer IC operates 1-8.5 GHz RF 3 dB bandwidth and an ideal square-law characteristic was obtained around input level of -15 dBm to 0 dBm. The mixer IC was actually operated in a 2.5 Gb/s coherent optical transmission test system, and sensitivity of -41.3 dBm for 10/sup -11/ bit-error-rate was obtained.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"10 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113994614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394478
F. Oehler, J. Sauerer, R. Hagelauer, D. Seitzer, U. Nowotny, B. Raynor, J. Schneider
A 0.3 /spl mu/m AlGaAs-HEMT technology was used to develop a high speed analog to digital converter (ADC). The 5-b converter based on a parallel architecture, operates up to a 3.6 GHz sampling rate. Excellent dynamic performance was achieved by an optimized comparator design and careful layout of the signal and clock lines. Each comparator is preceeded by a preamplifier to enhance its sensitivity and to minimize clock kickback. Using source follower buffers at the input, a very linear input capacitance was achieved. Thus the ADC's overall input capacitance is voltage independent.<>
{"title":"A 3.6 gigasample/s 5 bit analog to digital converter using 0.3 /spl mu/m AlGaAs-HEMT technology","authors":"F. Oehler, J. Sauerer, R. Hagelauer, D. Seitzer, U. Nowotny, B. Raynor, J. Schneider","doi":"10.1109/GAAS.1993.394478","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394478","url":null,"abstract":"A 0.3 /spl mu/m AlGaAs-HEMT technology was used to develop a high speed analog to digital converter (ADC). The 5-b converter based on a parallel architecture, operates up to a 3.6 GHz sampling rate. Excellent dynamic performance was achieved by an optimized comparator design and careful layout of the signal and clock lines. Each comparator is preceeded by a preamplifier to enhance its sensitivity and to minimize clock kickback. Using source follower buffers at the input, a very linear input capacitance was achieved. Thus the ADC's overall input capacitance is voltage independent.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"42 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114035596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394504
V. Nair, R. Vaitkus, D. Scheitlin, J. Kline, H. Swanson
A low current GaAs MMIC amplifier/mixer was designed and characterized for portable communication applications in the 900 MHz band. This single chip integrated front-end IC (90 mil /spl times/ 110 mil) achieved - 118 dBM sensitivity at the cellular band. The extremely low power dissipation, high level of integration, and very good RF performance of this monolithic IC make it an ideal candidate for portable communication applications.<>
设计了一种适用于900 MHz频段便携式通信的低电流GaAs MMIC放大器/混频器。该单芯片集成前端IC (90 mil /spl倍/ 110 mil)在蜂窝频段实现了- 118 dBM的灵敏度。这种单片IC极低的功耗、高集成度和非常好的射频性能使其成为便携式通信应用的理想选择。
{"title":"Low current GaAs integrated down converter for portable communication applications","authors":"V. Nair, R. Vaitkus, D. Scheitlin, J. Kline, H. Swanson","doi":"10.1109/GAAS.1993.394504","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394504","url":null,"abstract":"A low current GaAs MMIC amplifier/mixer was designed and characterized for portable communication applications in the 900 MHz band. This single chip integrated front-end IC (90 mil /spl times/ 110 mil) achieved - 118 dBM sensitivity at the cellular band. The extremely low power dissipation, high level of integration, and very good RF performance of this monolithic IC make it an ideal candidate for portable communication applications.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"346 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126030032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394433
F. Ali, M. Salib, A. Gupta, D. Dawson
A two-stage X-Ku band MMIC power amplifier has been designed and fabricated using common-emitter GaAs heterojunction bipolar transistors (HBTs). This monolithic amplifier has achieved 16 dB gain, 1.4 W (CW) peak output power and 48% peak power added efficiency (PAE) over 8-15 GHz. Input and output matching networks, as well as biasing circuits, are all contained within this HBT MMIC. To the authors' knowledge, this is the highest efficiency and the highest gain reported for any broadband monolithic power amplifier in the X-Ku band.<>
利用共发射极GaAs异质结双极晶体管(hbt)，设计并制作了一种两级X-Ku波段MMIC功率放大器。该单片放大器在8-15 GHz范围内实现了16 dB增益，1.4 W (CW)峰值输出功率和48%的峰值功率附加效率(PAE)。输入输出匹配网络，以及偏置电路，都包含在这个HBT MMIC中。据作者所知，这是在X-Ku波段的任何宽带单片功率放大器中报道的最高效率和最高增益。
{"title":"A 8-15 GHz, 1W HBT power MMIC with 16 dB gain and 48% peak power added efficiency","authors":"F. Ali, M. Salib, A. Gupta, D. Dawson","doi":"10.1109/GAAS.1993.394433","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394433","url":null,"abstract":"A two-stage X-Ku band MMIC power amplifier has been designed and fabricated using common-emitter GaAs heterojunction bipolar transistors (HBTs). This monolithic amplifier has achieved 16 dB gain, 1.4 W (CW) peak output power and 48% peak power added efficiency (PAE) over 8-15 GHz. Input and output matching networks, as well as biasing circuits, are all contained within this HBT MMIC. To the authors' knowledge, this is the highest efficiency and the highest gain reported for any broadband monolithic power amplifier in the X-Ku band.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129666613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394483
Y. Kaneko, H. Shimizu, K. Nagata, M. Koyanagi, M. Okamoto, M. Suzuki, S. Yokokawa, S. Shimizu, T. Maejima, J. Wada, H. Kawada, S. Ueno, M. Minamizawa, I. Yaegashi
The authors develop a 25 k-gate array with 0.8-/spl mu/m buried p-layer MESFET, three-level gold-based interconnects, and Au bump technology. They use differential push-pull circuits for the ECL interface circuits to obtain a sufficient margin, a low-voltage (-1.6 V) power supply for the internal gates to reduce the power consumption, and -2.0 V for the I/O circuits. The basic cell array combines DCFL and ECL compatible buffered DCFL gates (BDCFL). The basic delay times are 45 ps for 0.75 mW DCFL and 60 ps for 1.2 mW BDCFL gates. The gate array chip size is 10.7/spl times/10/7 mm, and contains 24,320 three-input BDCFL internal gates. The authors also use 80 /spl mu/m TAB to reduce the package delay time and simultaneous switching output noise. They use the array in a vector parallel processor which has a peak performance of 355 GFLOPS.<>
{"title":"A 25 k-gate BDCFL G/A with a differential push-pull ECL I/O","authors":"Y. Kaneko, H. Shimizu, K. Nagata, M. Koyanagi, M. Okamoto, M. Suzuki, S. Yokokawa, S. Shimizu, T. Maejima, J. Wada, H. Kawada, S. Ueno, M. Minamizawa, I. Yaegashi","doi":"10.1109/GAAS.1993.394483","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394483","url":null,"abstract":"The authors develop a 25 k-gate array with 0.8-/spl mu/m buried p-layer MESFET, three-level gold-based interconnects, and Au bump technology. They use differential push-pull circuits for the ECL interface circuits to obtain a sufficient margin, a low-voltage (-1.6 V) power supply for the internal gates to reduce the power consumption, and -2.0 V for the I/O circuits. The basic cell array combines DCFL and ECL compatible buffered DCFL gates (BDCFL). The basic delay times are 45 ps for 0.75 mW DCFL and 60 ps for 1.2 mW BDCFL gates. The gate array chip size is 10.7/spl times/10/7 mm, and contains 24,320 three-input BDCFL internal gates. The authors also use 80 /spl mu/m TAB to reduce the package delay time and simultaneous switching output noise. They use the array in a vector parallel processor which has a peak performance of 355 GFLOPS.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121913068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394493
S. Yinger, F. Lee, R. Huang, K. Schneider, E. Wang, K. F. Smith, M. Penugonda, S. Jacobs, T. Carter
A high speed HBT gate array has been developed for applications requiring data rates up to 5 Gbps. The array uses three levels of series gating enabling complex logic functions to be implemented efficiently. Chip size is 2.2 mm /spl times/ 2.2 mm and is packaged in a 68 pin leaded chip carrier with 20 pair of differential I/O signals. Typical power dissipation is 1 to 3 watts. The top level gate delay is 55 ps for a fanout of one and 60 fF load.<>
高速HBT门阵列已经开发用于需要高达5 Gbps数据速率的应用。该阵列采用三级串联门控，能够有效地实现复杂的逻辑功能。芯片尺寸为2.2 mm /spl倍/ 2.2 mm，封装在68引脚的芯片载波中，具有20对差分I/O信号。典型功耗为1 ~ 3瓦。当风扇输出为1，负载为60ff时，顶级栅极延迟为55ps
{"title":"HBT gate array for 5 GHz ASICs","authors":"S. Yinger, F. Lee, R. Huang, K. Schneider, E. Wang, K. F. Smith, M. Penugonda, S. Jacobs, T. Carter","doi":"10.1109/GAAS.1993.394493","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394493","url":null,"abstract":"A high speed HBT gate array has been developed for applications requiring data rates up to 5 Gbps. The array uses three levels of series gating enabling complex logic functions to be implemented efficiently. Chip size is 2.2 mm /spl times/ 2.2 mm and is packaged in a 68 pin leaded chip carrier with 20 pair of differential I/O signals. Typical power dissipation is 1 to 3 watts. The top level gate delay is 55 ps for a fanout of one and 60 fF load.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127023729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394441
M. Nishitsuji, A. Tamura, T. Kunihisa, K. Yaharta, M. Shibuya, M. Kitagawa, T. Hirao
The authors have developed a new GaAs-MMIC process technology using the low-temperature RF sputtered SrTiO/sub 3/ thin film capacitors which were combined with WSi-gate self-aligned FETs (SAFETs). The SrTiO/sub 3/ film with high dielectric constant (/spl epsi//sub r/) over 100 and low leakage current density under 10/sup -6/A/cm/sup 2/ at 1 MV/cm was obtained by RF sputtering method with the temperature range of 200/spl sim/300/spl deg/C. This SrTiO/sub 3/ capacitor exhibited no /spl epsi///sub r/ change up to 3.0 GHz, and low insertion losses of 0.29 dB and 0.05 dB were obtained for 32 pF-capacitor (S=10,000 /spl mu/m/sup 2/) at 0.2 GHz and 1.0 GHz, respectively. By integrating these on-chip SrTiO/sub 3/ bypass-capacitors into GaAs-IC, the parasitic inductance of the source-to-ground interconnection is successfully reduced, and the enhanced gain characteristic was obtained for self-biased amplifier circuit.<>
{"title":"Advanced GaAs-MMIC process technology using high-dielectric constant thin film capacitors by low-temperature RF sputtering method","authors":"M. Nishitsuji, A. Tamura, T. Kunihisa, K. Yaharta, M. Shibuya, M. Kitagawa, T. Hirao","doi":"10.1109/GAAS.1993.394441","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394441","url":null,"abstract":"The authors have developed a new GaAs-MMIC process technology using the low-temperature RF sputtered SrTiO/sub 3/ thin film capacitors which were combined with WSi-gate self-aligned FETs (SAFETs). The SrTiO/sub 3/ film with high dielectric constant (/spl epsi//sub r/) over 100 and low leakage current density under 10/sup -6/A/cm/sup 2/ at 1 MV/cm was obtained by RF sputtering method with the temperature range of 200/spl sim/300/spl deg/C. This SrTiO/sub 3/ capacitor exhibited no /spl epsi///sub r/ change up to 3.0 GHz, and low insertion losses of 0.29 dB and 0.05 dB were obtained for 32 pF-capacitor (S=10,000 /spl mu/m/sup 2/) at 0.2 GHz and 1.0 GHz, respectively. By integrating these on-chip SrTiO/sub 3/ bypass-capacitors into GaAs-IC, the parasitic inductance of the source-to-ground interconnection is successfully reduced, and the enhanced gain characteristic was obtained for self-biased amplifier circuit.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127144288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394430
A. Kurdoghlian, W. Lam, C. Chou, L. Jellian, A. Igawa, M. Matloubian, L. Larson, A. Brown, M. Thompson, C. Ngo
High-efficiency monolithic Q-band power amplifiers were developed using InP based HEMT MMIC technology. The amplifiers demonstrated state-of-the-art power performance including 33% power-added efficiency and 26 dBm of output power at 44 GHz. This is the highest output power reported with such a high efficiency for InP-based HEMT MMIC power amplifiers at Q-bands. The intended application is communication terminals.<>
{"title":"High-efficiency InP-based HEMT MMIC power amplifier","authors":"A. Kurdoghlian, W. Lam, C. Chou, L. Jellian, A. Igawa, M. Matloubian, L. Larson, A. Brown, M. Thompson, C. Ngo","doi":"10.1109/GAAS.1993.394430","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394430","url":null,"abstract":"High-efficiency monolithic Q-band power amplifiers were developed using InP based HEMT MMIC technology. The amplifiers demonstrated state-of-the-art power performance including 33% power-added efficiency and 26 dBm of output power at 44 GHz. This is the highest output power reported with such a high efficiency for InP-based HEMT MMIC power amplifiers at Q-bands. The intended application is communication terminals.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116978914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394501
M. Maeda, M. Nishijima, H. Takehara, C. Adachi, H. Fujimoto, Y. Ota, O. Ishikawa
A GaAs power multichip IC (MCIC) operating at 3.5 V for cellular phone has been developed. The MCIC can deliver an output power over 1.3 W with a power-added efficiency of 60% from 890 to 950 MHz. It is comprised of two GaAs MESFETs, three GaAs passive matching chips and a printed board on which biasing networks are fabricated. These components are mounted on an aluminum nitride (AlN) package. The volume of the MCIC is only 0.4 cc, half that of conventional power hybrid ICs. This MCIC will contribute to realization of high performance and very compact cellular phones.<>
{"title":"A 3.5V, 1.3W GaAs power multichip IC for cellular phone","authors":"M. Maeda, M. Nishijima, H. Takehara, C. Adachi, H. Fujimoto, Y. Ota, O. Ishikawa","doi":"10.1109/GAAS.1993.394501","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394501","url":null,"abstract":"A GaAs power multichip IC (MCIC) operating at 3.5 V for cellular phone has been developed. The MCIC can deliver an output power over 1.3 W with a power-added efficiency of 60% from 890 to 950 MHz. It is comprised of two GaAs MESFETs, three GaAs passive matching chips and a printed board on which biasing networks are fabricated. These components are mounted on an aluminum nitride (AlN) package. The volume of the MCIC is only 0.4 cc, half that of conventional power hybrid ICs. This MCIC will contribute to realization of high performance and very compact cellular phones.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132687426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：