Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394472
M. R. Wilson, D. Chasson, B. Krongard, R. Rosenberry, N. Shah, B. Welch
The implementation, optimization, and evaluation of an ion implanted, 0.5 /spl mu/m refractory self-aligned gate GaAs MESFET process for DCFL digital ICs for supercomputer applications is described. The MESFET performance has been optimized for minimal short channel effects, ultra high performance, minimal backgating, and improved manufacturability. This device process has been coupled together with a three or four level metal interconnect process for producing 1 GHz clock rate LSI to VLSI digital computer ICs. The interconnect process makes use of up to four levels of CVD tungsten via fill for planarity throughout the interconnect process. This process yields typical propagation delays of 25 pS for a 2/4 /spl mu/m inverter with unity fanout. Four input NOR gates with a fanout of four have a typical delay of 65 pS. Moreover, a four input NOR buffer driving a fanout of seven through 500 /spl mu/m of minimum geometry metal has a delay of 63 pS. This delay increases to 93 pS when the metal length is increased to 1500 /spl mu/m. This process is being used to produce 5 to 10 K gate digital circuits for the 1 GHz clock rate Cray-4 supercomputer. This work has resulted in a manufacturing process which produces devices and circuits with world class performance.<>
{"title":"Extending the performance envelope of 0.5 /spl mu/m implanted SAG-MESFET's for supercomputer applications","authors":"M. R. Wilson, D. Chasson, B. Krongard, R. Rosenberry, N. Shah, B. Welch","doi":"10.1109/GAAS.1993.394472","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394472","url":null,"abstract":"The implementation, optimization, and evaluation of an ion implanted, 0.5 /spl mu/m refractory self-aligned gate GaAs MESFET process for DCFL digital ICs for supercomputer applications is described. The MESFET performance has been optimized for minimal short channel effects, ultra high performance, minimal backgating, and improved manufacturability. This device process has been coupled together with a three or four level metal interconnect process for producing 1 GHz clock rate LSI to VLSI digital computer ICs. The interconnect process makes use of up to four levels of CVD tungsten via fill for planarity throughout the interconnect process. This process yields typical propagation delays of 25 pS for a 2/4 /spl mu/m inverter with unity fanout. Four input NOR gates with a fanout of four have a typical delay of 65 pS. Moreover, a four input NOR buffer driving a fanout of seven through 500 /spl mu/m of minimum geometry metal has a delay of 63 pS. This delay increases to 93 pS when the metal length is increased to 1500 /spl mu/m. This process is being used to produce 5 to 10 K gate digital circuits for the 1 GHz clock rate Cray-4 supercomputer. This work has resulted in a manufacturing process which produces devices and circuits with world class performance.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131153497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394494
O.M.K. Law, C. Salama
A GaAs five-transistor static memory cell is proposed. It is derived from nMOS Schmitt trigger. The memory cell overcomes the subthreshold leakage loss by using a self ground-shifting technique which limits the leakage current flow to the cell. Compared with conventional GaAs SRAM cells, it offers small design area and allows large memory arrays to be realized. A prototype was implemented in a 1 /spl mu/m non-self aligned GaAs MESFET technology with read and write access time of 1.0 ns and 1.25 ns, respectively.<>
{"title":"GaAs Schmitt trigger memory cell design","authors":"O.M.K. Law, C. Salama","doi":"10.1109/GAAS.1993.394494","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394494","url":null,"abstract":"A GaAs five-transistor static memory cell is proposed. It is derived from nMOS Schmitt trigger. The memory cell overcomes the subthreshold leakage loss by using a self ground-shifting technique which limits the leakage current flow to the cell. Compared with conventional GaAs SRAM cells, it offers small design area and allows large memory arrays to be realized. A prototype was implemented in a 1 /spl mu/m non-self aligned GaAs MESFET technology with read and write access time of 1.0 ns and 1.25 ns, respectively.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132306706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394484
H.R. Watts
The CRAY-3 system is operational. The first system to use GaAs for all logic and unique miniaturized packaging was first benchmarked in early 1993 with a subsequent delivery to the National Center for Atmospheric Research (NCAR) May 24, 1993. The system clock operates at 480 MHz and is competitive with any other system currently on the market. The investment in GaAs and packaging will be taken advantage of, allowing, rapid movement to the CRAY-4 system. The CRAY-4 will use higher density GaAs ICs and have a 1000 MHz clock. This system is expected to be the fastest system on the market when it is introduced in late 1994.<>
{"title":"The future of GaAs in the CRAY-3 and CRAY-4 supercomputers","authors":"H.R. Watts","doi":"10.1109/GAAS.1993.394484","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394484","url":null,"abstract":"The CRAY-3 system is operational. The first system to use GaAs for all logic and unique miniaturized packaging was first benchmarked in early 1993 with a subsequent delivery to the National Center for Atmospheric Research (NCAR) May 24, 1993. The system clock operates at 480 MHz and is competitive with any other system currently on the market. The investment in GaAs and packaging will be taken advantage of, allowing, rapid movement to the CRAY-4 system. The CRAY-4 will use higher density GaAs ICs and have a 1000 MHz clock. This system is expected to be the fastest system on the market when it is introduced in late 1994.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114977390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394485
D. J. Warner, C. E. Lindsay, C. Sansom
The application of statistical process control techniques intended for high volume continuous processes to the batch processes typical of GaAs MMIC manufacture can result in misleading data analysis. The moving range charting method has been successfully implemented for process control within the 3" fabrication facility. In addition, a revised method is presented for the assessment of process capability that takes into account the sampling strategy for data acquisition. Examples are given for both types of calculation. The introduction of control charting has allowed the quantity of in-process testing to be reduced, thus saving considerable time and expense.<>
{"title":"The use and misuse of statistical process control in GaAs MMIC manufacture","authors":"D. J. Warner, C. E. Lindsay, C. Sansom","doi":"10.1109/GAAS.1993.394485","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394485","url":null,"abstract":"The application of statistical process control techniques intended for high volume continuous processes to the batch processes typical of GaAs MMIC manufacture can result in misleading data analysis. The moving range charting method has been successfully implemented for process control within the 3\" fabrication facility. In addition, a revised method is presented for the assessment of process capability that takes into account the sampling strategy for data acquisition. Examples are given for both types of calculation. The introduction of control charting has allowed the quantity of in-process testing to be reduced, thus saving considerable time and expense.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124108755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394454
D. Whitefield, C. Wei, J.C.M. Hwang
An analysis of the heterojunction bipolar transistor (HBT) temperature effect has been performed directly at microwave frequencies using a combination of measurements and physical modeling. The most temperature sensitive elements, the base-emitter resistance and capacitance, and the transconductance, were extracted from S-parameter data at 28 bias points for five temperatures from 23/spl deg/C to 225/spl deg/C. The element values were compared to a physical model showing excellent agreement. The magnitude and direction of change for the element values is shown versus temperature and bias which, along with the physical model, describes the HBT behavior with a strong bias on device physics. The cutoff frequencies f/sub T/ and f/sub MAX/ were also measured and calculated, both showing a monotonic decrease with temperature. Over the 200/spl deg/C range f/sub T/ and f/sub MAX/ decreased by a total of 40% and 60%, respectively.<>
{"title":"Elevated temperature microwave characteristics of heterojunction bipolar transistors","authors":"D. Whitefield, C. Wei, J.C.M. Hwang","doi":"10.1109/GAAS.1993.394454","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394454","url":null,"abstract":"An analysis of the heterojunction bipolar transistor (HBT) temperature effect has been performed directly at microwave frequencies using a combination of measurements and physical modeling. The most temperature sensitive elements, the base-emitter resistance and capacitance, and the transconductance, were extracted from S-parameter data at 28 bias points for five temperatures from 23/spl deg/C to 225/spl deg/C. The element values were compared to a physical model showing excellent agreement. The magnitude and direction of change for the element values is shown versus temperature and bias which, along with the physical model, describes the HBT behavior with a strong bias on device physics. The cutoff frequencies f/sub T/ and f/sub MAX/ were also measured and calculated, both showing a monotonic decrease with temperature. Over the 200/spl deg/C range f/sub T/ and f/sub MAX/ decreased by a total of 40% and 60%, respectively.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122897358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394447
J. Riishoj, T. Nielsen, U. Gliese, K. Stubkjaer
A design of a 50 /spl Omega/ impedance matched two-to-four level converter GaAs IC for two-electrode semiconductor optical amplifier modulators is presented. Eye diagrams with good eye openings and 0.33 V spacing between adjacent logic levels are demonstrated for input bit rates up to 4 Gb/s. A novel differential super buffer output driver is applied and output reflection coefficients.<>
{"title":"4 Gb/s two-level to 2 symbol/s four-level converter GaAs IC for semiconductor optical amplifier modulators","authors":"J. Riishoj, T. Nielsen, U. Gliese, K. Stubkjaer","doi":"10.1109/GAAS.1993.394447","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394447","url":null,"abstract":"A design of a 50 /spl Omega/ impedance matched two-to-four level converter GaAs IC for two-electrode semiconductor optical amplifier modulators is presented. Eye diagrams with good eye openings and 0.33 V spacing between adjacent logic levels are demonstrated for input bit rates up to 4 Gb/s. A novel differential super buffer output driver is applied and output reflection coefficients.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128346141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394503
M. Nakatsugawa, Y. Yamaguchi, M. Muraguchi
A low-power-consumption variable-gain low noise amplifier (LNA) is developed. In order to achieve low noise, high gain, low distortion and low power consumption simultaneously, a cascode connection between an enhancement-mode GaAs MESFET (EFET) and a depletion-mode GaAs (DFET) is employed. The amplifier shows state-of-the-art performance with NF of 2.0 dB, gain of 12.2 dB and IP3 of 5.1 dBm at 1.9 GHz at power consumption of 2.0 mW, and NF of 2.4 dB, gain of 10.2 dB and IP3 of 2.7 dBm at 1 mW. Moreover, the LNA's gain is controllable according to the receiving level and it can be turned off while the transmitter is operating.<>
{"title":"An L-band ultra low power consumption monolithic low noise amplifier [for mobile communication]","authors":"M. Nakatsugawa, Y. Yamaguchi, M. Muraguchi","doi":"10.1109/GAAS.1993.394503","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394503","url":null,"abstract":"A low-power-consumption variable-gain low noise amplifier (LNA) is developed. In order to achieve low noise, high gain, low distortion and low power consumption simultaneously, a cascode connection between an enhancement-mode GaAs MESFET (EFET) and a depletion-mode GaAs (DFET) is employed. The amplifier shows state-of-the-art performance with NF of 2.0 dB, gain of 12.2 dB and IP3 of 5.1 dBm at 1.9 GHz at power consumption of 2.0 mW, and NF of 2.4 dB, gain of 10.2 dB and IP3 of 2.7 dBm at 1 mW. Moreover, the LNA's gain is controllable according to the receiving level and it can be turned off while the transmitter is operating.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117130677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394434
T. Apel, R. Bhatla, B. Lauterwasser
The authors describe two advanced MMIC power amplifiers covering the 6-18 GHz and 8-14.5 GHz bands. Both chips are based on a novel two section distributed amplifier structure that employs bandpass networks instead of the conventional lowpass image-parameter networks. A new matrix amplifier structure is also used in the first stage of the 8-14.5 GHz PA. Bias networks are fully integrated to allow automated assembly. Significant milestones in wideband power and efficiency have been achieved.<>
{"title":"High performance wide-band and medium-band power amplifier MMICs","authors":"T. Apel, R. Bhatla, B. Lauterwasser","doi":"10.1109/GAAS.1993.394434","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394434","url":null,"abstract":"The authors describe two advanced MMIC power amplifiers covering the 6-18 GHz and 8-14.5 GHz bands. Both chips are based on a novel two section distributed amplifier structure that employs bandpass networks instead of the conventional lowpass image-parameter networks. A new matrix amplifier structure is also used in the first stage of the 8-14.5 GHz PA. Bias networks are fully integrated to allow automated assembly. Significant milestones in wideband power and efficiency have been achieved.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131003331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394436
L. Aucoin, S. Bouthilette, A. Platzker, S. Shanfield, A. Bertrand, W. Hoke, P. Lyman
The authors have simultaneously demonstrated 10 W output power, 13.5 dB gain and 63% power-added efficiency on a single 16.8 mm pseudomorphic high electron mobility transistor (PHEMT) device at 2.45 GHz. This result represents the highest output power from a single transistor at S-band frequencies. The power density exhibited by the PHEMT device was 625 mW/mm which is significantly higher than a typical MESFET power density of 400 mW/mm.<>
{"title":"Large periphery, high power pseudomorphic HEMTs","authors":"L. Aucoin, S. Bouthilette, A. Platzker, S. Shanfield, A. Bertrand, W. Hoke, P. Lyman","doi":"10.1109/GAAS.1993.394436","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394436","url":null,"abstract":"The authors have simultaneously demonstrated 10 W output power, 13.5 dB gain and 63% power-added efficiency on a single 16.8 mm pseudomorphic high electron mobility transistor (PHEMT) device at 2.45 GHz. This result represents the highest output power from a single transistor at S-band frequencies. The power density exhibited by the PHEMT device was 625 mW/mm which is significantly higher than a typical MESFET power density of 400 mW/mm.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125698226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394444
T. Cordner, B. Marks
The impact of GaAs wafer breakage on processing facilities is discussed. Wafer strength and equipment assessment are detailed. The authors describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unassignable causes. When proper material and process control techniques are used, GaAs wafer breakage should not occur.<>
{"title":"GaAs wafer breakage: Causes and cures, growth and process","authors":"T. Cordner, B. Marks","doi":"10.1109/GAAS.1993.394444","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394444","url":null,"abstract":"The impact of GaAs wafer breakage on processing facilities is discussed. Wafer strength and equipment assessment are detailed. The authors describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unassignable causes. When proper material and process control techniques are used, GaAs wafer breakage should not occur.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131644816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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