Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584982
A. Goldberg, Birgit Manhica, S. Ziesche, M. Ebermann, A. Günther
The results developed in a research project resulted from the cooperation between Fraunhofer IKTS in the field of ceramic multilayer technology and InfraTec GmbH in the field of infrared sensors and measurement technology and were generated within the project’s duration of 4 years. New types of miniature heaters embedded in ceramics were developed and their properties regarding modulation, spectral emission, long term and high temperature stability were characterized and optimized. A new process chain based on ceramic multilayer technology was developed to produce the IR emitter, which is based on a combination of sacrificial paste technology using screen or stencil printing and Low Temperature Cofired Technology (LTCC) processing. The generated dielectric layer thicknesses of 15-20 µm are half as thick as with conventional LTCC tape manufacturing processes. To optimize the emission coefficient towards a black body, new ceramic pastes suitable for screen printing have been developed. In this way, black surfaces could be created on the radiators, which are characterized by high temperature stability and low thermal mass. First long-term studies of the IR emitter up to 2000 hours show functionality at 650 °C with low degradation.
{"title":"Monolithic Ceramic IR-Emitter for Gas Analyzer","authors":"A. Goldberg, Birgit Manhica, S. Ziesche, M. Ebermann, A. Günther","doi":"10.23919/empc53418.2021.9584982","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584982","url":null,"abstract":"The results developed in a research project resulted from the cooperation between Fraunhofer IKTS in the field of ceramic multilayer technology and InfraTec GmbH in the field of infrared sensors and measurement technology and were generated within the project’s duration of 4 years. New types of miniature heaters embedded in ceramics were developed and their properties regarding modulation, spectral emission, long term and high temperature stability were characterized and optimized. A new process chain based on ceramic multilayer technology was developed to produce the IR emitter, which is based on a combination of sacrificial paste technology using screen or stencil printing and Low Temperature Cofired Technology (LTCC) processing. The generated dielectric layer thicknesses of 15-20 µm are half as thick as with conventional LTCC tape manufacturing processes. To optimize the emission coefficient towards a black body, new ceramic pastes suitable for screen printing have been developed. In this way, black surfaces could be created on the radiators, which are characterized by high temperature stability and low thermal mass. First long-term studies of the IR emitter up to 2000 hours show functionality at 650 °C with low degradation.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"97 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132801711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9585013
Z. Gökdeniz, M. Lederer, G. Khatibi, J. Nicolics
In the field of power electronics device function leads to high operating temperatures. High stresses and strains are induced as a result of mismatch in Coefficient of Thermal Expansion (CTE) leading to plastic deformation in constrained joints. The thermomechanical stresses stimulate mechanisms such as dislocation glide or creep. Especially when the homologous temperature increases, time dependent creep failure becomes a dominant issue in the joint reliability. This work is devoted to the development of a temperature dependent material model for pressure assisted silver sintered joints. This model is validated on the basis of stress relaxation experiments aside from measurements of shear strength and mechanical fatigue. For this purpose, Ag-sintered copper joints were manufactured (0-hour) and heat treated at 250 °C for 250 hours in air and in protective atmosphere. Investigations of microstructure were made by scanning electron microscopy (SEM). Shear and stress relaxation tests were conducted in a tensile machine with thermal chamber at temperatures of 25 °C, 130 °C and 200 °C. For lifetime estimation of the samples Weibull probability plots for low cycle fatigue were determined. Further, Norton power law was employed to determine material parameters such as stress exponent n and creep activation energy Q. In conclusion, a unified model of plasticity and creep was established.
{"title":"Temperature Dependent Relaxation Behavior of Ag-Sintered Copper Joints","authors":"Z. Gökdeniz, M. Lederer, G. Khatibi, J. Nicolics","doi":"10.23919/empc53418.2021.9585013","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9585013","url":null,"abstract":"In the field of power electronics device function leads to high operating temperatures. High stresses and strains are induced as a result of mismatch in Coefficient of Thermal Expansion (CTE) leading to plastic deformation in constrained joints. The thermomechanical stresses stimulate mechanisms such as dislocation glide or creep. Especially when the homologous temperature increases, time dependent creep failure becomes a dominant issue in the joint reliability. This work is devoted to the development of a temperature dependent material model for pressure assisted silver sintered joints. This model is validated on the basis of stress relaxation experiments aside from measurements of shear strength and mechanical fatigue. For this purpose, Ag-sintered copper joints were manufactured (0-hour) and heat treated at 250 °C for 250 hours in air and in protective atmosphere. Investigations of microstructure were made by scanning electron microscopy (SEM). Shear and stress relaxation tests were conducted in a tensile machine with thermal chamber at temperatures of 25 °C, 130 °C and 200 °C. For lifetime estimation of the samples Weibull probability plots for low cycle fatigue were determined. Further, Norton power law was employed to determine material parameters such as stress exponent n and creep activation energy Q. In conclusion, a unified model of plasticity and creep was established.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122189499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9585009
J. Köszegi, Lars Schnelle, Xingdan Jia, O. Schwanitz, I. Ndip, M. Schneider-Ramelow, K. Lang
Split-ring resonators (SRRs) are one of the fundamental building blocks of electromagnetic metamaterials. These structures play a key role in the development of future millimeter-wave (mm-Wave) components and systems. In this work, we present a study on the scaling of split-ring resonators and their models to mm-Wave frequencies with special focus on their use in heterogeneous packaging and system-integration. We model, simulate, design and measure different configurations of SRRs. Very good correlation is obtained between the analytical calculations, simulation and measurements. Finally, we investigate the impact of process variations, which occur during fabrication of the resonators.
{"title":"Split-rings for heterogeneous integration of mm-Wave systems","authors":"J. Köszegi, Lars Schnelle, Xingdan Jia, O. Schwanitz, I. Ndip, M. Schneider-Ramelow, K. Lang","doi":"10.23919/empc53418.2021.9585009","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9585009","url":null,"abstract":"Split-ring resonators (SRRs) are one of the fundamental building blocks of electromagnetic metamaterials. These structures play a key role in the development of future millimeter-wave (mm-Wave) components and systems. In this work, we present a study on the scaling of split-ring resonators and their models to mm-Wave frequencies with special focus on their use in heterogeneous packaging and system-integration. We model, simulate, design and measure different configurations of SRRs. Very good correlation is obtained between the analytical calculations, simulation and measurements. Finally, we investigate the impact of process variations, which occur during fabrication of the resonators.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122192878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584960
V. Buiculescu, A. Baracu, C. Buiculescu
The paper presents a circuit technique aimed to integrate interdigital transducer (IDT) based sensors, provided with either coplanar waveguide (CPW) or microstrip ports, into substrate integrated waveguide (SIW) structures for operation as transmission-type sensors. Therefore, two electromagnetically coupled SIW sections are specifically configured to make possible this conversion. In order to demonstrate the validity of the proposed sensing concept, capacitors of different values, and fully compatible with surface-mounting technology, were assembled at the CPW port of the coupled SIW section to simulate various IDT capacitive sensors. Deviation of the maximum rejection frequency from 4.32 GHz to 7.56 GHz was obtained using capacitance values from 4.7 pF down to 0 pF (i.e. open ended CPW).
{"title":"Capacitive Sensors Integrated in SIW Structures – A Proof of Concept","authors":"V. Buiculescu, A. Baracu, C. Buiculescu","doi":"10.23919/empc53418.2021.9584960","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584960","url":null,"abstract":"The paper presents a circuit technique aimed to integrate interdigital transducer (IDT) based sensors, provided with either coplanar waveguide (CPW) or microstrip ports, into substrate integrated waveguide (SIW) structures for operation as transmission-type sensors. Therefore, two electromagnetically coupled SIW sections are specifically configured to make possible this conversion. In order to demonstrate the validity of the proposed sensing concept, capacitors of different values, and fully compatible with surface-mounting technology, were assembled at the CPW port of the coupled SIW section to simulate various IDT capacitive sensors. Deviation of the maximum rejection frequency from 4.32 GHz to 7.56 GHz was obtained using capacitance values from 4.7 pF down to 0 pF (i.e. open ended CPW).","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122590662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584987
Pei Lu, Huihui Wang, Yong Zhang, Yan Zhang, Johan Liu
Thermal performance of an epoxy resin reinforced by carbon fibers is studied by numerical simulation method. Various carbon fiber structures are taken into consideration and the effective thermal conductivity of the composite carbon fiber waved structure is obtained. The influences of the number, size, shape, spacing and arrangement of the carbon fibers on the thermal conduction of the composites are analyzed. The deformation of the composite under mechanical loading and the corresponding the thermal conductivity of the carbon fiber-reinforced epoxy resin are also investigated.
{"title":"Thermal Conduction of Fiber-Reinforced Polymer Under Loading","authors":"Pei Lu, Huihui Wang, Yong Zhang, Yan Zhang, Johan Liu","doi":"10.23919/empc53418.2021.9584987","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584987","url":null,"abstract":"Thermal performance of an epoxy resin reinforced by carbon fibers is studied by numerical simulation method. Various carbon fiber structures are taken into consideration and the effective thermal conductivity of the composite carbon fiber waved structure is obtained. The influences of the number, size, shape, spacing and arrangement of the carbon fibers on the thermal conduction of the composites are analyzed. The deformation of the composite under mechanical loading and the corresponding the thermal conductivity of the carbon fiber-reinforced epoxy resin are also investigated.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121274897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584961
N. B. Babaroud, R. Dekker, O. Holk, U. Tiringer, P. Taheri, Domonkos Horváth, T. Nánási, I. Ulbert, W. Serdijn, V. Giagka
In this paper, we investigate the long-term adhesion strength and barrier property of our recently proposed encapsulation stack that includes PDMS-Parylene C and PECVD interlayers (SiO2 and SiC) for adhesion improvement. To evaluate the adhesion strength of our proposed stack, the sample preparation consisted in depositing approximately 25 nm of SiC and 25 nm of SiO2 on half wafers, previously coated with Parylene C. Next, $50 mu mathrm{m}$ PDMS was spin-coated on top. Finally, the samples were detached from the Si wafer and soaked in a PBS solution at 67°C to accelerate the aging process. Two samples were also implanted, subcutaneously, on the left and right subscapular regions of a rat. The optical inspection and peel tests performed after two months confirmed our preliminary findings and showed a significant improvement of the adhesion in our proposed encapsulation stack compared to the case of PDMS on Parylene C alone. In addition, the X-ray photoelectron spectroscopy(XPS) analysis at the interface between SiC and Parylene C showed different peaks for the interface compared to the reference spectra, which could be an indication of a chemical bond. Finally, water vapor transmission rate (WVTR) tests were performed to investigate the barrier property of our proposed encapsulation stack against water vapor transmission. The results demonstrated that the proposed stack acts as a significantly (two orders of magnitude) higher barrier against moisture compared to only Parylene C and PDMS encapsulation layers. The proposed method yields a fully transparent encapsulation stack over a broad wavelength spectrum that can be used for the conformal encapsulation of flexible devices and thus, making them compatible with techniques such as optical imaging and optogenetics.
在本文中，我们研究了我们最近提出的封装堆栈的长期粘附强度和屏障性能，该封装堆栈包括pdms -聚对二甲苯C和PECVD中间层(SiO2和SiC)，以改善粘附性。为了评估我们所提出的堆栈的粘附强度，样品制备包括在半晶圆上沉积约25 nm的SiC和25 nm的SiO2，之前涂有聚对二甲苯c，然后在顶部旋转涂覆$50 mu math {m}$ PDMS。最后，将样品从硅片上分离出来，在67°C的PBS溶液中浸泡，以加速老化过程。两个样品也被皮下植入，在大鼠的左右肩胛下区域。两个月后进行的光学检查和剥离测试证实了我们的初步发现，并显示与单独在聚对二甲苯C上使用PDMS相比，我们提议的封装堆栈的附着力有了显着改善。此外，在SiC和对二甲苯界面处的x射线光电子能谱(XPS)分析显示，与参考光谱相比，界面峰不同，这可能是化学键的指示。最后，进行了水蒸气透过率(WVTR)测试，以考察我们提出的封装堆栈对水蒸气透过的阻隔性能。结果表明，与仅使用聚二甲苯和PDMS封装层相比，所提出的堆叠具有显着(两个数量级)更高的防潮屏障。所提出的方法在宽波长范围内产生完全透明的封装堆栈，可用于柔性器件的保形封装，从而使其与光学成像和光遗传学等技术兼容。
{"title":"Investigation of the long-term adhesion and barrier properties of a PDMS-Parylene stack with PECVD ceramic interlayers for the conformal encapsulation of neural implants","authors":"N. B. Babaroud, R. Dekker, O. Holk, U. Tiringer, P. Taheri, Domonkos Horváth, T. Nánási, I. Ulbert, W. Serdijn, V. Giagka","doi":"10.23919/empc53418.2021.9584961","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584961","url":null,"abstract":"In this paper, we investigate the long-term adhesion strength and barrier property of our recently proposed encapsulation stack that includes PDMS-Parylene C and PECVD interlayers (SiO2 and SiC) for adhesion improvement. To evaluate the adhesion strength of our proposed stack, the sample preparation consisted in depositing approximately 25 nm of SiC and 25 nm of SiO2 on half wafers, previously coated with Parylene C. Next, $50 mu mathrm{m}$ PDMS was spin-coated on top. Finally, the samples were detached from the Si wafer and soaked in a PBS solution at 67°C to accelerate the aging process. Two samples were also implanted, subcutaneously, on the left and right subscapular regions of a rat. The optical inspection and peel tests performed after two months confirmed our preliminary findings and showed a significant improvement of the adhesion in our proposed encapsulation stack compared to the case of PDMS on Parylene C alone. In addition, the X-ray photoelectron spectroscopy(XPS) analysis at the interface between SiC and Parylene C showed different peaks for the interface compared to the reference spectra, which could be an indication of a chemical bond. Finally, water vapor transmission rate (WVTR) tests were performed to investigate the barrier property of our proposed encapsulation stack against water vapor transmission. The results demonstrated that the proposed stack acts as a significantly (two orders of magnitude) higher barrier against moisture compared to only Parylene C and PDMS encapsulation layers. The proposed method yields a fully transparent encapsulation stack over a broad wavelength spectrum that can be used for the conformal encapsulation of flexible devices and thus, making them compatible with techniques such as optical imaging and optogenetics.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130266134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584968
N. Palavesam, J. Choi, W. Hell, G. Fiol, K. Velthaus, C. Zerna, H. Gieser, C. Landesberger
Here, we report flip-chip bonding processes based on Anisotropic Conductive Film (ACF) and Sn-Ag-Cu (SAC) solder implemented for bonding three test chips (two Silicon, Si ICs on either side of an Indium Phosphide, InP IC) in series on $25{mu}mathrm{m}$ thick polyimide foil substrates. Si ICs were bonded only with SAC solder, whereas both SAC and ACF were applied for the flip-chip integration of the fragile InP chips. RF measurements were then performed on the impedance controlled paths across the polyimide foil of the fabricated assemblies to evaluate as well as to compare the RF performance of ACF and SAC solder in terms of the differential S21 parameter. The measurements revealed that when ACF is employed for interconnecting the InP chip and SAC solder for the two Si chips, a higher 3 dB bandwidth of 42 GHz was obtained whereas a 3 dB bandwidth of only 31 – 34 GHz was measured when only SAC solder was used for bonding all three ICs. These measurement results confirm that a higher bandwidth can be obtained from the assemblies when ACF is used as the interconnection material. Therefore, it can be concluded that the ACF based integration technology could be favored over solder processes for bonding high performance multi Gbit/s subassemblies, especially with higher density of contact pads.
{"title":"Advanced integration technology for fabricating high-speed electro-optical sub-assembly","authors":"N. Palavesam, J. Choi, W. Hell, G. Fiol, K. Velthaus, C. Zerna, H. Gieser, C. Landesberger","doi":"10.23919/empc53418.2021.9584968","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584968","url":null,"abstract":"Here, we report flip-chip bonding processes based on Anisotropic Conductive Film (ACF) and Sn-Ag-Cu (SAC) solder implemented for bonding three test chips (two Silicon, Si ICs on either side of an Indium Phosphide, InP IC) in series on $25{mu}mathrm{m}$ thick polyimide foil substrates. Si ICs were bonded only with SAC solder, whereas both SAC and ACF were applied for the flip-chip integration of the fragile InP chips. RF measurements were then performed on the impedance controlled paths across the polyimide foil of the fabricated assemblies to evaluate as well as to compare the RF performance of ACF and SAC solder in terms of the differential S21 parameter. The measurements revealed that when ACF is employed for interconnecting the InP chip and SAC solder for the two Si chips, a higher 3 dB bandwidth of 42 GHz was obtained whereas a 3 dB bandwidth of only 31 – 34 GHz was measured when only SAC solder was used for bonding all three ICs. These measurement results confirm that a higher bandwidth can be obtained from the assemblies when ACF is used as the interconnection material. Therefore, it can be concluded that the ACF based integration technology could be favored over solder processes for bonding high performance multi Gbit/s subassemblies, especially with higher density of contact pads.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131216579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584971
Ruud de Wit
Smart Electronics’ market trends like 5G Telecom and Autonomous Driving are driving advanced semiconductor packaging innovations towards higher functionality, enhanced connectivity at higher frequencies, smaller form factors (miniaturization) and reduced power consumption. To meet these demands, semiconductor package designs continue to evolve towards Multiple and Thinner Die using System-in-Package and Wafer Level architectures. Especially for next generation smaller RF devices like Front End Modules, tight Keep-out-Zones, shorter interconnects and improved thermal management are key to enable next gen package designs. The industrial and automotive industry are looking in parallel for Pb solder replacement with improved (automotive) reliability for typically larger die size and metal lead frame components which is very challenging from stress point of view. This paper will describe the successful development of hybrid silver sintering die attach adhesives for RF applications and continued development work in progress to pass automotive temp cycling on larger die sizes in lead frame packages. Processing of such hybrid silver sintering adhesives on standard die attach equipment without pressure and maximum $200^{circ}mathrm{C}$ oven cure under N2 and or AIR conditions are other key development targets.
{"title":"Silver Sintering Die Attach Developments for RF, Power and Automotive Applications","authors":"Ruud de Wit","doi":"10.23919/empc53418.2021.9584971","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584971","url":null,"abstract":"Smart Electronics’ market trends like 5G Telecom and Autonomous Driving are driving advanced semiconductor packaging innovations towards higher functionality, enhanced connectivity at higher frequencies, smaller form factors (miniaturization) and reduced power consumption. To meet these demands, semiconductor package designs continue to evolve towards Multiple and Thinner Die using System-in-Package and Wafer Level architectures. Especially for next generation smaller RF devices like Front End Modules, tight Keep-out-Zones, shorter interconnects and improved thermal management are key to enable next gen package designs. The industrial and automotive industry are looking in parallel for Pb solder replacement with improved (automotive) reliability for typically larger die size and metal lead frame components which is very challenging from stress point of view. This paper will describe the successful development of hybrid silver sintering die attach adhesives for RF applications and continued development work in progress to pass automotive temp cycling on larger die sizes in lead frame packages. Processing of such hybrid silver sintering adhesives on standard die attach equipment without pressure and maximum $200^{circ}mathrm{C}$ oven cure under N2 and or AIR conditions are other key development targets.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128256353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584974
Kevin Kröhnert, M. Wöhrmann, M. Schiffer, Georg Friedrich, D. Starukhin, M. Schneider-Ramelow, W. Mayer, T. Chaloun, T. Galler, C. Waldschmidt, M. Schulz-Ruhtenberg, N. Ambrosius, U. Hansen
In this work, we present the realized versatile hermetically sealed sensor packaging platform based on glass interposers which is applicable in industrial metrology, MEMS, photonics, life sciences and process automation application, among others. The sealed glass package can include passives and different active devices (radar, pressure, infrared sensors, etc.). Glass is used because it offers ideal properties for such a package by providing excellent chemical resistance, mechanical strength, advantageous RF characteristics and low costs. The capabilities of the platform are demonstrated in form of a radar level sensor which is operated at 160GHz. The level sensor includes our sensor packaging platform with an integrated SiGe ASIC and an RF port. Due to the hermetic sealing of the ASIC inside, it is possible to utilize the package in hazardous environments, in this case in chemical microreactors. The package only measures 5.9 x 4.4 x 0.8 mm3 and uses TGVs (Through-Glass Vias) in this miniaturized sensor systems as vertical DC and RF interconnections with low parasitics which leads to low losses, while maintaining hermetic sealing. The performance of the TGVs regarding their reliability and their RF capabilities was investigated before and showed superior properties with less effort for fabrication. In this paper we will focus on all aspects of the final package with a fully functional radar ASIC inside. We consider the processing chain based on wafer-level processes, design and simulation, the analysis of the realized radar sensor demonstrator as well as the characterization and evaluation of the final package regarding reliability and hermeticity. The glass interposer processing steps and all the challenges which had to be solved for the via formation, the TGV filling and the hermetically sealing of the two interposers with the ASIC inside will be highlighted. The characterization and evaluation of the novel demonstrator system will consider RF performance, radar characteristics, reliability and hermetic sealing of the glass package
在这项工作中，我们提出了基于玻璃中间层的多功能密封传感器封装平台，该平台适用于工业计量，MEMS，光子学，生命科学和过程自动化等应用。密封玻璃封装可以包括无源器件和不同的有源器件(雷达、压力、红外传感器等)。之所以使用玻璃，是因为它具有优异的耐化学性、机械强度、有利的射频特性和低成本，为这种封装提供了理想的性能。该平台的能力以工作频率为160GHz的雷达液位计的形式进行了演示。液位传感器包括我们的传感器封装平台，集成SiGe ASIC和RF端口。由于ASIC内部的密封，可以在危险环境中使用该封装，在这种情况下是在化学微反应器中。该封装尺寸仅为5.9 x 4.4 x 0.8 mm3，并在这种小型化传感器系统中使用tgv (Through-Glass过孔)作为垂直DC和RF互连，具有低寄生性，可降低损耗，同时保持密封性。之前对tgv的可靠性和射频性能进行了研究，结果表明，tgv的性能优越，制造成本低。在本文中，我们将重点介绍具有全功能雷达ASIC内部的最终封装的各个方面。我们考虑了基于晶圆级工艺的加工链，设计和仿真，对实现的雷达传感器演示器进行分析，以及对最终封装的可靠性和密封性进行表征和评估。将重点介绍玻璃中间层的加工步骤和所有必须解决的挑战，包括通孔形成、TGV填充和两个中间层与内部ASIC的密封性。新型演示系统的表征和评估将考虑射频性能、雷达特性、可靠性和玻璃封装的密封性
{"title":"Versatile Hermetically Sealed Sensor Platform for High Frequency Applications","authors":"Kevin Kröhnert, M. Wöhrmann, M. Schiffer, Georg Friedrich, D. Starukhin, M. Schneider-Ramelow, W. Mayer, T. Chaloun, T. Galler, C. Waldschmidt, M. Schulz-Ruhtenberg, N. Ambrosius, U. Hansen","doi":"10.23919/empc53418.2021.9584974","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584974","url":null,"abstract":"In this work, we present the realized versatile hermetically sealed sensor packaging platform based on glass interposers which is applicable in industrial metrology, MEMS, photonics, life sciences and process automation application, among others. The sealed glass package can include passives and different active devices (radar, pressure, infrared sensors, etc.). Glass is used because it offers ideal properties for such a package by providing excellent chemical resistance, mechanical strength, advantageous RF characteristics and low costs. The capabilities of the platform are demonstrated in form of a radar level sensor which is operated at 160GHz. The level sensor includes our sensor packaging platform with an integrated SiGe ASIC and an RF port. Due to the hermetic sealing of the ASIC inside, it is possible to utilize the package in hazardous environments, in this case in chemical microreactors. The package only measures 5.9 x 4.4 x 0.8 mm3 and uses TGVs (Through-Glass Vias) in this miniaturized sensor systems as vertical DC and RF interconnections with low parasitics which leads to low losses, while maintaining hermetic sealing. The performance of the TGVs regarding their reliability and their RF capabilities was investigated before and showed superior properties with less effort for fabrication. In this paper we will focus on all aspects of the final package with a fully functional radar ASIC inside. We consider the processing chain based on wafer-level processes, design and simulation, the analysis of the realized radar sensor demonstrator as well as the characterization and evaluation of the final package regarding reliability and hermeticity. The glass interposer processing steps and all the challenges which had to be solved for the via formation, the TGV filling and the hermetically sealing of the two interposers with the ASIC inside will be highlighted. The characterization and evaluation of the novel demonstrator system will consider RF performance, radar characteristics, reliability and hermetic sealing of the glass package","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128980622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584966
A. Roshanghias, A. Rodrigues, J. Kaczyński, A. Binder, A. Schmidt
Thermosonic flipchip bonding of Cu pillars has gained increasing attention for the low-temperature chip-to-chip (C2C) and chip-to-wafer (C2W) integration. By exploiting ultrasonic energy, which activates the interface and causes the deformation-induced vibration, Cu-to-Cu direct bonding is facilitated in significantly lower bonding forces, shorter process windows and lower thermal budget. However, for thermosonic Cu pillar bonding, the tolerance of bump height variation is highly stringent and the coplanarity of the surfaces is critical. In order to address the need to improve coplanarity during thermosonic bonding, a low-cost planarization process was applied to the bump surfaces. As a result, Cu pillars with a uniform thickness distribution through the wafer and a flattened surface were produced. The proposed planarization process led to an increase of up to 60% in the contact area between the bumps during thermosonic bonding. As a result, the thermosonic bond strength of the joints was significantly improved.
{"title":"Cu Pillar Planarization to Enhance Thermosonic Flipchip Bonding","authors":"A. Roshanghias, A. Rodrigues, J. Kaczyński, A. Binder, A. Schmidt","doi":"10.23919/empc53418.2021.9584966","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584966","url":null,"abstract":"Thermosonic flipchip bonding of Cu pillars has gained increasing attention for the low-temperature chip-to-chip (C2C) and chip-to-wafer (C2W) integration. By exploiting ultrasonic energy, which activates the interface and causes the deformation-induced vibration, Cu-to-Cu direct bonding is facilitated in significantly lower bonding forces, shorter process windows and lower thermal budget. However, for thermosonic Cu pillar bonding, the tolerance of bump height variation is highly stringent and the coplanarity of the surfaces is critical. In order to address the need to improve coplanarity during thermosonic bonding, a low-cost planarization process was applied to the bump surfaces. As a result, Cu pillars with a uniform thickness distribution through the wafer and a flattened surface were produced. The proposed planarization process led to an increase of up to 60% in the contact area between the bumps during thermosonic bonding. As a result, the thermosonic bond strength of the joints was significantly improved.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124573704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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