Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584974
Kevin Kröhnert, M. Wöhrmann, M. Schiffer, Georg Friedrich, D. Starukhin, M. Schneider-Ramelow, W. Mayer, T. Chaloun, T. Galler, C. Waldschmidt, M. Schulz-Ruhtenberg, N. Ambrosius, U. Hansen
In this work, we present the realized versatile hermetically sealed sensor packaging platform based on glass interposers which is applicable in industrial metrology, MEMS, photonics, life sciences and process automation application, among others. The sealed glass package can include passives and different active devices (radar, pressure, infrared sensors, etc.). Glass is used because it offers ideal properties for such a package by providing excellent chemical resistance, mechanical strength, advantageous RF characteristics and low costs. The capabilities of the platform are demonstrated in form of a radar level sensor which is operated at 160GHz. The level sensor includes our sensor packaging platform with an integrated SiGe ASIC and an RF port. Due to the hermetic sealing of the ASIC inside, it is possible to utilize the package in hazardous environments, in this case in chemical microreactors. The package only measures 5.9 x 4.4 x 0.8 mm3 and uses TGVs (Through-Glass Vias) in this miniaturized sensor systems as vertical DC and RF interconnections with low parasitics which leads to low losses, while maintaining hermetic sealing. The performance of the TGVs regarding their reliability and their RF capabilities was investigated before and showed superior properties with less effort for fabrication. In this paper we will focus on all aspects of the final package with a fully functional radar ASIC inside. We consider the processing chain based on wafer-level processes, design and simulation, the analysis of the realized radar sensor demonstrator as well as the characterization and evaluation of the final package regarding reliability and hermeticity. The glass interposer processing steps and all the challenges which had to be solved for the via formation, the TGV filling and the hermetically sealing of the two interposers with the ASIC inside will be highlighted. The characterization and evaluation of the novel demonstrator system will consider RF performance, radar characteristics, reliability and hermetic sealing of the glass package
在这项工作中，我们提出了基于玻璃中间层的多功能密封传感器封装平台，该平台适用于工业计量，MEMS，光子学，生命科学和过程自动化等应用。密封玻璃封装可以包括无源器件和不同的有源器件(雷达、压力、红外传感器等)。之所以使用玻璃，是因为它具有优异的耐化学性、机械强度、有利的射频特性和低成本，为这种封装提供了理想的性能。该平台的能力以工作频率为160GHz的雷达液位计的形式进行了演示。液位传感器包括我们的传感器封装平台，集成SiGe ASIC和RF端口。由于ASIC内部的密封，可以在危险环境中使用该封装，在这种情况下是在化学微反应器中。该封装尺寸仅为5.9 x 4.4 x 0.8 mm3，并在这种小型化传感器系统中使用tgv (Through-Glass过孔)作为垂直DC和RF互连，具有低寄生性，可降低损耗，同时保持密封性。之前对tgv的可靠性和射频性能进行了研究，结果表明，tgv的性能优越，制造成本低。在本文中，我们将重点介绍具有全功能雷达ASIC内部的最终封装的各个方面。我们考虑了基于晶圆级工艺的加工链，设计和仿真，对实现的雷达传感器演示器进行分析，以及对最终封装的可靠性和密封性进行表征和评估。将重点介绍玻璃中间层的加工步骤和所有必须解决的挑战，包括通孔形成、TGV填充和两个中间层与内部ASIC的密封性。新型演示系统的表征和评估将考虑射频性能、雷达特性、可靠性和玻璃封装的密封性
{"title":"Versatile Hermetically Sealed Sensor Platform for High Frequency Applications","authors":"Kevin Kröhnert, M. Wöhrmann, M. Schiffer, Georg Friedrich, D. Starukhin, M. Schneider-Ramelow, W. Mayer, T. Chaloun, T. Galler, C. Waldschmidt, M. Schulz-Ruhtenberg, N. Ambrosius, U. Hansen","doi":"10.23919/empc53418.2021.9584974","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584974","url":null,"abstract":"In this work, we present the realized versatile hermetically sealed sensor packaging platform based on glass interposers which is applicable in industrial metrology, MEMS, photonics, life sciences and process automation application, among others. The sealed glass package can include passives and different active devices (radar, pressure, infrared sensors, etc.). Glass is used because it offers ideal properties for such a package by providing excellent chemical resistance, mechanical strength, advantageous RF characteristics and low costs. The capabilities of the platform are demonstrated in form of a radar level sensor which is operated at 160GHz. The level sensor includes our sensor packaging platform with an integrated SiGe ASIC and an RF port. Due to the hermetic sealing of the ASIC inside, it is possible to utilize the package in hazardous environments, in this case in chemical microreactors. The package only measures 5.9 x 4.4 x 0.8 mm3 and uses TGVs (Through-Glass Vias) in this miniaturized sensor systems as vertical DC and RF interconnections with low parasitics which leads to low losses, while maintaining hermetic sealing. The performance of the TGVs regarding their reliability and their RF capabilities was investigated before and showed superior properties with less effort for fabrication. In this paper we will focus on all aspects of the final package with a fully functional radar ASIC inside. We consider the processing chain based on wafer-level processes, design and simulation, the analysis of the realized radar sensor demonstrator as well as the characterization and evaluation of the final package regarding reliability and hermeticity. The glass interposer processing steps and all the challenges which had to be solved for the via formation, the TGV filling and the hermetically sealing of the two interposers with the ASIC inside will be highlighted. The characterization and evaluation of the novel demonstrator system will consider RF performance, radar characteristics, reliability and hermetic sealing of the glass package","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128980622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584966
A. Roshanghias, A. Rodrigues, J. Kaczyński, A. Binder, A. Schmidt
Thermosonic flipchip bonding of Cu pillars has gained increasing attention for the low-temperature chip-to-chip (C2C) and chip-to-wafer (C2W) integration. By exploiting ultrasonic energy, which activates the interface and causes the deformation-induced vibration, Cu-to-Cu direct bonding is facilitated in significantly lower bonding forces, shorter process windows and lower thermal budget. However, for thermosonic Cu pillar bonding, the tolerance of bump height variation is highly stringent and the coplanarity of the surfaces is critical. In order to address the need to improve coplanarity during thermosonic bonding, a low-cost planarization process was applied to the bump surfaces. As a result, Cu pillars with a uniform thickness distribution through the wafer and a flattened surface were produced. The proposed planarization process led to an increase of up to 60% in the contact area between the bumps during thermosonic bonding. As a result, the thermosonic bond strength of the joints was significantly improved.
{"title":"Cu Pillar Planarization to Enhance Thermosonic Flipchip Bonding","authors":"A. Roshanghias, A. Rodrigues, J. Kaczyński, A. Binder, A. Schmidt","doi":"10.23919/empc53418.2021.9584966","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584966","url":null,"abstract":"Thermosonic flipchip bonding of Cu pillars has gained increasing attention for the low-temperature chip-to-chip (C2C) and chip-to-wafer (C2W) integration. By exploiting ultrasonic energy, which activates the interface and causes the deformation-induced vibration, Cu-to-Cu direct bonding is facilitated in significantly lower bonding forces, shorter process windows and lower thermal budget. However, for thermosonic Cu pillar bonding, the tolerance of bump height variation is highly stringent and the coplanarity of the surfaces is critical. In order to address the need to improve coplanarity during thermosonic bonding, a low-cost planarization process was applied to the bump surfaces. As a result, Cu pillars with a uniform thickness distribution through the wafer and a flattened surface were produced. The proposed planarization process led to an increase of up to 60% in the contact area between the bumps during thermosonic bonding. As a result, the thermosonic bond strength of the joints was significantly improved.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124573704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584981
Hoang-Vu Nguyen, Lisette Hernandez Gonzalez, K. Imenes, K. Aasmundtveit
Reworkable anisotropic conductive adhesives (ACAs) are of interest when the material is used for assembling electronic modules with high value, such as in medical devices. Adhesive matrices comprising a blend of a thermosetting epoxy and a thermoplastic polymer are selected because it has shown potential to ensure good electrical and mechanical integrity whilst still allowing reworkability for ACA assemblies. Our previous work demonstrated the feasibility of using blends of an epoxy and a thermoplastic polysulfone as an adhesive matrix for the reworkable ACAs. The rework temperature, however, is relatively high (190°C) which causes disadvantages for the rework process and safety of sensitive electronic components nearby. ACA material with lower rework temperature is thus of interest. This paper presents the findings of favorable mixing ratio between an epoxy compatible with ACA applications and a thermoplastic polymer that offers good mechanical strength combined with reworkability at a temperature as low as 100°C. The results show that the adhesive blends with a high concentration of thermoplastic polymer (35–65 wt%) exhibit satisfactory die shear strength at temperatures relevant for production/storage (23°C) and operation of medical devices (50°C). Furthermore, successful rework at temperature as low as 100°C is confirmed for such adhesive blends.
{"title":"Enabling Low-Temperature Reworkability for Anisotropic Conductive Adhesives","authors":"Hoang-Vu Nguyen, Lisette Hernandez Gonzalez, K. Imenes, K. Aasmundtveit","doi":"10.23919/empc53418.2021.9584981","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584981","url":null,"abstract":"Reworkable anisotropic conductive adhesives (ACAs) are of interest when the material is used for assembling electronic modules with high value, such as in medical devices. Adhesive matrices comprising a blend of a thermosetting epoxy and a thermoplastic polymer are selected because it has shown potential to ensure good electrical and mechanical integrity whilst still allowing reworkability for ACA assemblies. Our previous work demonstrated the feasibility of using blends of an epoxy and a thermoplastic polysulfone as an adhesive matrix for the reworkable ACAs. The rework temperature, however, is relatively high (190°C) which causes disadvantages for the rework process and safety of sensitive electronic components nearby. ACA material with lower rework temperature is thus of interest. This paper presents the findings of favorable mixing ratio between an epoxy compatible with ACA applications and a thermoplastic polymer that offers good mechanical strength combined with reworkability at a temperature as low as 100°C. The results show that the adhesive blends with a high concentration of thermoplastic polymer (35–65 wt%) exhibit satisfactory die shear strength at temperatures relevant for production/storage (23°C) and operation of medical devices (50°C). Furthermore, successful rework at temperature as low as 100°C is confirmed for such adhesive blends.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126532210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584978
S. Klengel, A. Krombholz, Olaf Schwedler, H. Busch
Additive manufacturing of copper structures with selective laser melting offers promising possibilities for prototyping or production of unconventional structures for electronic assemblies. There are various copper powders from different manufacturers available that are suitable for processing with SLM technology. Simple structures produced with copper powder in SLM technology are increasingly being used. However, more complex structures with small dimensions are still the exception. As part of a public funded project, we are researching the potentials and limits of the copper materials and processes currently used for additive manufacturing in electronic systems using the example of a heat sink for microelectronic assemblies. Within the project we focus on the aspects of microstructure formation after processing (e.g. particle sintering, pore formation, binder residues, etc.). In our paper we summarize the research results achieved so far. In comparison to reference assemblies from conventional production, we show impressive high-resolution microstructural results of SEM on copper powder in initial state and manufactured structures and correlate these results to each other. The result is a current state of the art for the use of copper materials and SLM processes in additive manufacturing in the field of electronic systems.
{"title":"Material characterization of copper structures for electronic systems manufactured by selective laser melting (SLM)","authors":"S. Klengel, A. Krombholz, Olaf Schwedler, H. Busch","doi":"10.23919/empc53418.2021.9584978","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584978","url":null,"abstract":"Additive manufacturing of copper structures with selective laser melting offers promising possibilities for prototyping or production of unconventional structures for electronic assemblies. There are various copper powders from different manufacturers available that are suitable for processing with SLM technology. Simple structures produced with copper powder in SLM technology are increasingly being used. However, more complex structures with small dimensions are still the exception. As part of a public funded project, we are researching the potentials and limits of the copper materials and processes currently used for additive manufacturing in electronic systems using the example of a heat sink for microelectronic assemblies. Within the project we focus on the aspects of microstructure formation after processing (e.g. particle sintering, pore formation, binder residues, etc.). In our paper we summarize the research results achieved so far. In comparison to reference assemblies from conventional production, we show impressive high-resolution microstructural results of SEM on copper powder in initial state and manufactured structures and correlate these results to each other. The result is a current state of the art for the use of copper materials and SLM processes in additive manufacturing in the field of electronic systems.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134491017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584962
A. Velea, Joshua Wilson, A. Pak, M. Seckel, Sven Schmidt, Stefan Kosmider, Nasim Bakhshaee, W. Serdijn, V. Giagka
Our limited understanding of the nervous system forms a bottleneck which impedes the effective treatment of neurological disorders. In order to improve patient outcomes it is highly desirable to interact with the nervous tissue at the resolution of individual cells. As neurons number in the billions and transmit signals electrically, high-density, cellular-resolution microelectrode arrays will be a useful tool for both treatment and research.This paper investigates the advantages and versatility of laser-patterning technologies for the development of such high-density microelectrode arrays in flexible polymer substrates. In particular, it aims to elucidate the mechanisms involved in laser patterning of thin polymers on top of thin metal layers. For this comparative study, a pulsed picosecond laser (Schmoll Picodrill) with two separate wavelengths (1064 nm (infrared (IR)) and 355 nm (ultraviolet (UV))) was used. A 5 $mu$ m thick electroplated layer of gold (Au) was used to form the microelectrodes. Laser-patterning was investigated to expose the Au electrodes when encapsulated by two different thermoplastic polymers: thermoplastic polyurethane (TPU), and Parylene-C, with thicknesses of maximum 25 $mu$ m. The electrode diameter and the distance between electrodes were reduced down to 35 $mu$ m and 30 $mu$ m, respectively. The structures were evaluated using optical microscopy and white light interferometry and the results indicated that both laser wavelengths can be successfully used to create high-density microelectrode arrays in polymer substrates. However, due to the lower absorption coefficient of metals in the IR spectrum, a higher uniformity of the exposed Au layer was observed when IR-based lasers were used. This paper provides more insight into the mechanisms involved in laser-patterning of thin film polymers and demonstrates that it can be a reliable and cost-effective method for the rapid prototyping of thin-film neural interfaces.
{"title":"UV and IR Laser-Patterning for High-Density Thin-Film Neural Interfaces","authors":"A. Velea, Joshua Wilson, A. Pak, M. Seckel, Sven Schmidt, Stefan Kosmider, Nasim Bakhshaee, W. Serdijn, V. Giagka","doi":"10.23919/empc53418.2021.9584962","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584962","url":null,"abstract":"Our limited understanding of the nervous system forms a bottleneck which impedes the effective treatment of neurological disorders. In order to improve patient outcomes it is highly desirable to interact with the nervous tissue at the resolution of individual cells. As neurons number in the billions and transmit signals electrically, high-density, cellular-resolution microelectrode arrays will be a useful tool for both treatment and research.This paper investigates the advantages and versatility of laser-patterning technologies for the development of such high-density microelectrode arrays in flexible polymer substrates. In particular, it aims to elucidate the mechanisms involved in laser patterning of thin polymers on top of thin metal layers. For this comparative study, a pulsed picosecond laser (Schmoll Picodrill) with two separate wavelengths (1064 nm (infrared (IR)) and 355 nm (ultraviolet (UV))) was used. A 5 $mu$ m thick electroplated layer of gold (Au) was used to form the microelectrodes. Laser-patterning was investigated to expose the Au electrodes when encapsulated by two different thermoplastic polymers: thermoplastic polyurethane (TPU), and Parylene-C, with thicknesses of maximum 25 $mu$ m. The electrode diameter and the distance between electrodes were reduced down to 35 $mu$ m and 30 $mu$ m, respectively. The structures were evaluated using optical microscopy and white light interferometry and the results indicated that both laser wavelengths can be successfully used to create high-density microelectrode arrays in polymer substrates. However, due to the lower absorption coefficient of metals in the IR spectrum, a higher uniformity of the exposed Au layer was observed when IR-based lasers were used. This paper provides more insight into the mechanisms involved in laser-patterning of thin film polymers and demonstrates that it can be a reliable and cost-effective method for the rapid prototyping of thin-film neural interfaces.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"308 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132067299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584993
A. Zehri, T. Nilsson, Yifeng Fu, Johan Liu
The current development of the electronics system requires capabilities beyond conventional heat transfer approaches. New solutions based on advanced materials are being developed to tackle the current challenges in the development of electronics systems and the nanoscale 2D materials such as graphene are at the centre of the effort to exploit the intrinsic properties of carbon nanomaterials. In this work, we introduce a new concept of graphene-coated copper nanoparticles (G-CuNPs) and explore their multifunctional potential applications in metallic based paste used in electronics. The nanoscale powder was found to present a core/shell structure with the copper particle at its core and a disordered multilayer graphene structure continuously coating its surface. The composition of the particles was analysed, and the presence of the coating was found to provide oxidation protection for the metallic core. Thermogravimetric analysis (TGA) showed an additional role of the G-CuNPs with a reduction effect without the use of an additional reducing agent. Furthermore, due to the combined effect of the size of the particles and the oxidation-free metallic core, Differential Scanning Calorimetry (DSC) analysis revealed a melting depression at temperatures as low as $155 ^{circ}mathrm{C}$. Finally, the mechanical properties of the nanocoating were investigated and the results showed an enhanced ductility at the surface of the particles due to the presence of the multi-layered graphene structure, which might be exploited for powder flow and lubrication effect.
{"title":"Exploring Graphene Coated Copper Nanoparticles as a multifunctional Nanofiller for Micro-Scaled Copper Paste","authors":"A. Zehri, T. Nilsson, Yifeng Fu, Johan Liu","doi":"10.23919/empc53418.2021.9584993","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584993","url":null,"abstract":"The current development of the electronics system requires capabilities beyond conventional heat transfer approaches. New solutions based on advanced materials are being developed to tackle the current challenges in the development of electronics systems and the nanoscale 2D materials such as graphene are at the centre of the effort to exploit the intrinsic properties of carbon nanomaterials. In this work, we introduce a new concept of graphene-coated copper nanoparticles (G-CuNPs) and explore their multifunctional potential applications in metallic based paste used in electronics. The nanoscale powder was found to present a core/shell structure with the copper particle at its core and a disordered multilayer graphene structure continuously coating its surface. The composition of the particles was analysed, and the presence of the coating was found to provide oxidation protection for the metallic core. Thermogravimetric analysis (TGA) showed an additional role of the G-CuNPs with a reduction effect without the use of an additional reducing agent. Furthermore, due to the combined effect of the size of the particles and the oxidation-free metallic core, Differential Scanning Calorimetry (DSC) analysis revealed a melting depression at temperatures as low as $155 ^{circ}mathrm{C}$. Finally, the mechanical properties of the nanocoating were investigated and the results showed an enhanced ductility at the surface of the particles due to the presence of the multi-layered graphene structure, which might be exploited for powder flow and lubrication effect.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132024637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9585003
Madadnia Behnam, Bossuyt Frederick, V. Jan
This paper presents a novel approach for removing out-of-plane deformation in metal interconnects by adding a fractional structure to the original meander shape and using the optimised fabrication stack. In thermoformed electronics in cases where copper is used as the conductor, the twisting of meander-shaped structures caused by excessive mechanical stress can cause a non-uniform surface, delamination of the metal interconnect from the substrate, and in some cases, a short circuit to the adjacent tracks. Typically, stretchable electronics designers use various shapes and widths of the copper interconnect to tackle this issue. Using conventional meander shapes such as horseshoes and U shapes is not universally practical, especially when stretching is higher than 30 percent leading to significant out-of-plane deformation. Limiting this out-of-plane deformation by reducing the track width is not always applicable, as a minimum width is needed from a technology and conductivity perspective. The presented approach is inspired by computational and experimental studies of multiple meander shapes and fabrication methods. A geometry-based and fabrication-based approach is presented, which can reduce the mechanical stress of almost all possible meander shapes by increasing the meander’s path length to accommodate the metal track’s produced torque during stretching. An analytical approach is provided for calculating the optimal meander parameters, and the optimal fabrication stack is achieved based on simulation results. Experiments and finite-element modeling for an industrial case study show the improvement in the stress distribution and reduction of out-of-plane.
{"title":"Reducing out-of-plane deformation of metal interconnects in structural electronics","authors":"Madadnia Behnam, Bossuyt Frederick, V. Jan","doi":"10.23919/empc53418.2021.9585003","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9585003","url":null,"abstract":"This paper presents a novel approach for removing out-of-plane deformation in metal interconnects by adding a fractional structure to the original meander shape and using the optimised fabrication stack. In thermoformed electronics in cases where copper is used as the conductor, the twisting of meander-shaped structures caused by excessive mechanical stress can cause a non-uniform surface, delamination of the metal interconnect from the substrate, and in some cases, a short circuit to the adjacent tracks. Typically, stretchable electronics designers use various shapes and widths of the copper interconnect to tackle this issue. Using conventional meander shapes such as horseshoes and U shapes is not universally practical, especially when stretching is higher than 30 percent leading to significant out-of-plane deformation. Limiting this out-of-plane deformation by reducing the track width is not always applicable, as a minimum width is needed from a technology and conductivity perspective. The presented approach is inspired by computational and experimental studies of multiple meander shapes and fabrication methods. A geometry-based and fabrication-based approach is presented, which can reduce the mechanical stress of almost all possible meander shapes by increasing the meander’s path length to accommodate the metal track’s produced torque during stretching. An analytical approach is provided for calculating the optimal meander parameters, and the optimal fabrication stack is achieved based on simulation results. Experiments and finite-element modeling for an industrial case study show the improvement in the stress distribution and reduction of out-of-plane.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134375122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584977
Prabjit Singh, L. Palmer, Chen Xu, M. Pudas, J. Keeping, M. M. Khaw, Kok Lieh Tan, H. Fu
Conformal coatings are applied to protect printed circuit boards and components mounted on them from the deleterious effects of moisture, particulate matter and corrosive gases. The conventional method of testing the effectiveness of these coatings is to expose the conformally coated hardware to a corrosive environment for extended periods of time — often lasting many months — and determine the mean time to failure. iNEMI’s Conformal Coating Evaluation for Improved Environmental Protection project team is recommending a quicker test method that takes less than a week to evaluate conformal coatings. This method uses the corrosion rates of conformally coated thin films of copper and silver exposed to a sulfur gas environment as a measure if the coating performance. The project team investigated how temperature and humidity impact the corrosion rates of conformally coated copper and silver thin films compared to uncoated films. Performances of acrylic, silicone and atomic layer deposited (ALD) coatings were studied as a function of temperature and relative humidity. The team found that temperature affected the corrosion rates of conformally coated copper and silver thin films, whereas relative humidity had a lesser influence. The team also discovered significant differences in corrosion protection provided by the three coatings that were tested.
{"title":"Development of a Quick Test for Conformal Coatings","authors":"Prabjit Singh, L. Palmer, Chen Xu, M. Pudas, J. Keeping, M. M. Khaw, Kok Lieh Tan, H. Fu","doi":"10.23919/empc53418.2021.9584977","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584977","url":null,"abstract":"Conformal coatings are applied to protect printed circuit boards and components mounted on them from the deleterious effects of moisture, particulate matter and corrosive gases. The conventional method of testing the effectiveness of these coatings is to expose the conformally coated hardware to a corrosive environment for extended periods of time — often lasting many months — and determine the mean time to failure. iNEMI’s Conformal Coating Evaluation for Improved Environmental Protection project team is recommending a quicker test method that takes less than a week to evaluate conformal coatings. This method uses the corrosion rates of conformally coated thin films of copper and silver exposed to a sulfur gas environment as a measure if the coating performance. The project team investigated how temperature and humidity impact the corrosion rates of conformally coated copper and silver thin films compared to uncoated films. Performances of acrylic, silicone and atomic layer deposited (ALD) coatings were studied as a function of temperature and relative humidity. The team found that temperature affected the corrosion rates of conformally coated copper and silver thin films, whereas relative humidity had a lesser influence. The team also discovered significant differences in corrosion protection provided by the three coatings that were tested.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114564618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9585002
Xinjian Gong, Jin Chen, Yong Zhang, Xiuzhen Lu, Johan Liu
A flexible graphene and polyimide composite film was designed and fabricated in this study. A polyimide solution was used as an adhesive layer to connect graphene film and polyimide film by hot-pressing. Laser flash thermal analysis method was carried out to evaluate the thermal diffusion coefficient of different thicknesses of the fabricated films at various temperatures. Bending test was carried out to evaluate the stability and reliability of the composite film. Scanning electron microscopy was applied to characterize the cross-section of the composite film before and after the peel test. IR imaging was employed to compare the heat diffusion of the composite film and traditional flexible copper clad laminate. The results show that the composite film has significantly better thermal diffusion capacity than traditional flexible copper clad laminate.
{"title":"Fabrication and Characterization of Graphene/polyimide Composite Film","authors":"Xinjian Gong, Jin Chen, Yong Zhang, Xiuzhen Lu, Johan Liu","doi":"10.23919/empc53418.2021.9585002","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9585002","url":null,"abstract":"A flexible graphene and polyimide composite film was designed and fabricated in this study. A polyimide solution was used as an adhesive layer to connect graphene film and polyimide film by hot-pressing. Laser flash thermal analysis method was carried out to evaluate the thermal diffusion coefficient of different thicknesses of the fabricated films at various temperatures. Bending test was carried out to evaluate the stability and reliability of the composite film. Scanning electron microscopy was applied to characterize the cross-section of the composite film before and after the peel test. IR imaging was employed to compare the heat diffusion of the composite film and traditional flexible copper clad laminate. The results show that the composite film has significantly better thermal diffusion capacity than traditional flexible copper clad laminate.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"37 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120969013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584984
Romina Sattari, H. V. van Zeijl, Guoqi Zhang
This paper focuses on the design and fabrication of a new programmable thermal test chip as a flexible and cost-effective solution for simplification of characterization/prototyping of new packages. The cell-based design format makes the chip fit into any modular array configuration. One unit cell is as small as 4x4 mm2, including 6 individually programmable micro-heaters and 3 resistance temperature detectors (RTDs). All micro-heaters and sensors have 4-point Kelvin connections for improved measurement accuracy. The chip contains 2 metal layers: 100 nm thin-film Titanium to create micro-heaters and RTDs, and 2 μm Aluminum to add single bump measurement units and daisy chain connections. These structures facilitate bump reliability investigations during thermal/power cycling tests in flip-chip assembly technology. The calibration curves of RTDs show a sensitivity of 12 $Omega$/K which is improved by 50 percent compared to the state-of-the-art TTC. The proposed design provides higher spatial resolution in thermal mapping by accommodating 3 RTDs per cell. The dense configuration of micro-heaters increases the uniformity of the power dissipation, which enhances the accuracy of thermal interface material (TIM) characterizations. The steady-state infrared (IR) thermography of a 20x20 mm2 TTC, including 150 active micro-heaters, verifies the promising uniformity of the heat profile over the chip surface.
{"title":"Design and Fabrication of a Multi-Functional Programmable Thermal Test Chip","authors":"Romina Sattari, H. V. van Zeijl, Guoqi Zhang","doi":"10.23919/empc53418.2021.9584984","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584984","url":null,"abstract":"This paper focuses on the design and fabrication of a new programmable thermal test chip as a flexible and cost-effective solution for simplification of characterization/prototyping of new packages. The cell-based design format makes the chip fit into any modular array configuration. One unit cell is as small as 4x4 mm2, including 6 individually programmable micro-heaters and 3 resistance temperature detectors (RTDs). All micro-heaters and sensors have 4-point Kelvin connections for improved measurement accuracy. The chip contains 2 metal layers: 100 nm thin-film Titanium to create micro-heaters and RTDs, and 2 μm Aluminum to add single bump measurement units and daisy chain connections. These structures facilitate bump reliability investigations during thermal/power cycling tests in flip-chip assembly technology. The calibration curves of RTDs show a sensitivity of 12 $Omega$/K which is improved by 50 percent compared to the state-of-the-art TTC. The proposed design provides higher spatial resolution in thermal mapping by accommodating 3 RTDs per cell. The dense configuration of micro-heaters increases the uniformity of the power dissipation, which enhances the accuracy of thermal interface material (TIM) characterizations. The steady-state infrared (IR) thermography of a 20x20 mm2 TTC, including 150 active micro-heaters, verifies the promising uniformity of the heat profile over the chip surface.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125992543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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